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511FBA200M000BAG
Oscillator, 200 MHz, 50 ppm, SMD, 5mm x 3.2mm, 2.5 V, Si511 Series
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: SILICON LABS
- Product type: Standard Oscillators
- Frequency Nom:200MHz; Frequency Stability + / -:50ppm; Oscillator Case:SMD, 5mm x 3.2mm; Supply Voltage Nom:2.5V; Product Range:Si511 Series; Operat; Available until stocks are exhausted
- Frequency Nom: 200MHz
- Product Range: Si511
- Supply Voltage Nom: 2.5V
- Frequency Stability + / -: 50ppm
- Operating Temperature Max: 85°C
- Operating Temperature Min: -40°C
- Oscillator Case / Package: SMD, 5mm x 3.2mm
- Oscillator Output Compatibility: LVDS
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 3.52 € |
| Current stock | 200+ |
| Lead time | 30 days |
Datasheet
**Si510/511** ## **C RYSTAL O SCILLATOR (XO) 100 kH Z TO 250 MH Z** ## **Features** - Supports any frequency from 3.3, 2.5, or 1.8 V operation 100 kHz to 250 MHz Differential (LVPECL, LVDS, - Low jitter operation HCSL) or CMOS output options 2 to 4 week lead times Optional integrated 1:2 CMOS Total stability includes 10-year fanout buffer aging Runt suppression on OE and - Comprehensive production test power on coverage includes crystal ESR and Industry standard 5 x 7 and DLD 3.2 x 5 mm packages - On-chip LDO regulator for power Pb-free, RoHS compliant supply noise filtering –40 to 85[o] C operation ## **Applications** **Ordering Information:** See page 14. - SONET/SDH/OTN 3G-SDI/HD-SDI/SDI - Gigabit Ethernet Telecom Fibre Channel/SAS/SATA Switches/routers **Pin Assignments:** PCI Express FPGA/ASIC clock generation ~~pO~~ See page 12. ## **Description** The Si510/511 XO utilizes Silicon Laboratories' advanced DSPLL technology to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO where a different crystal is required for each output frequency, the Si510/511 uses one fixed crystal and Silicon Labs’ proprietary DSPLL synthesizer to generate any frequency across this range. This IC-based approach allows the crystal resonator to provide enhanced reliability, improved mechanical robustness, and excellent stability. In addition, this solution provides superior supply noise rejection, simplifying low jitter clock generation in noisy environments. Crystal ESR and DLD are individually production-tested to guarantee performance and enhance reliability. The Si510/511 is factoryconfigurable for a wide variety of user specifications, including frequency, supply voltage, output format, output enable polarity, and stability. Specific configurations are factory-programmed at time of shipment, eliminating long lead times and non-recurring engineering charges associated with custom frequency oscillators. **==> picture [423 x 319] intentionally omitted <==** **----- Start of picture text -----**<br> OE 1 4 VDD<br>to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO<br>where a different crystal is required for each output frequency, the Si510/511<br>uses one fixed crystal and Silicon Labs’ proprietary DSPLL synthesizer to<br>generate any frequency across this range. This IC-based approach allows<br>GND 2 3 CLK<br>the crystal resonator to provide enhanced reliability, improved mechanical<br>robustness, and excellent stability. In addition, this solution provides superior<br>supply noise rejection, simplifying low jitter clock generation in noisy Si510 (CMOS)<br>environments. Crystal ESR and DLD are individually production-tested to<br>guarantee performance and enhance reliability. The Si510/511 is factory- NC 1 6 VDD<br>configurable for a wide variety of user specifications, including frequency,<br>supply voltage, output format, output enable polarity, and stability. Specific<br>OE 2 5 CLK–<br>configurations are factory-programmed at time of shipment, eliminating long<br>lead times and non-recurring engineering charges associated with custom<br>GND 3 4 CLK+<br>gramram<br>Si510(LVDS/LVPECL/HCSL/<br>VDD Dual CMOS)<br>!<br>OE Low Noise Regulator OEOE 11 66 VVDDDD<br>Frequency Fixed Any-Frequency 0.1 to 250 MHz CLK+ NCNC 22 55 CLK–CLK–<br>Oscillator DSPLL [®] Synthesis CLK–<br>GNDGND 33 44 CLK+CLK+<br>eas Si511(LVDS/LVPECL/HCSL/ |<br>GND Dual CMOS)<br>**----- End of picture text -----**<br> **Functional Block Diagramram** **Copyright © 2015 by Silicon Laboratories** **Si510/511** **Rev. 1.2 7/15** **Si510/511** **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **2** **Si510/511** ## **TABLE OF C ONTENTS** |**Section**<br>**1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .**<br>**2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .**<br>2.1. Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<br>**3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .**<br>**4. Si510/511 Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .**<br>**5. Package Outline Diagram: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .**<br>**6. PCB Land Pattern: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .**<br>**7. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .**<br>**8. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .**<br>**9. Package Outline Diagram: 3.2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .**<br>**10. PCB Land Pattern: 3.2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .**<br>**11. Package Outline Diagram: 3.2 x 5 mm, 6-Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . .**<br>**12. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .**<br>**Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .**<br>**Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .**|**Page**<br>**. . . . .4**<br>**. . . .12**<br>. . . .13<br>**. . . .14**<br>**. . . .15**<br>**. . . .16**<br>**. . . .17**<br>**. . . .18**<br>**. . . .19**<br>**. . . .20**<br>**. . . .21**<br>**. . . .22**<br>**. . . .23**<br>**. . . .24**<br>**. . . .26**| |---|---| **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **3** **Si510/511** ## **1. Electrical Specifications** ## **Table 1. Operating Specifications** VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85[o] C |**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |Supply Voltage|VDD|3.3 V option|2.97|3.3|3.63|V| |||2.5 V option|2.25|2.5|2.75|V| |||1.8 V option|1.71|1.8|1.89|V| |Supply Current|IDD|CMOS, 100 MHz,<br>single-ended|—|21|26|mA| |||LVDS<br>(output enabled)|—|19|23|mA| |||LVPECL<br>(output enabled)|—|39|43|mA| |||HCSL<br>(output enabled)|—|41|44|mA| |||Tristate<br>(output disabled)|—|—|18|mA| |OE "1" Setting|VIH|See Note|0.80 x VDD|—|—|V| |OE "0" Setting|VIL|See Note|—|—|0.20 x VDD|V| |OE Internal Pull-Up/Pull-<br>Down Resistor*|RI||—|45|—|k| |Operating Temperature|TA||–40|—|85|oC| |***Note:**Active high and active low polarity OE options available. Active high option includes an internal pull-up.<br>Active low option includes an internal pull-down. See ordering information on page 14.||||||| ***Note:** Active high and active low polarity OE options available. Active high option includes an internal pull-up. Active low option includes an internal pull-down. See ordering information on page 14. **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **4** **Si510/511** ## **Table 2. Output Clock Frequency Characteristics** VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85[o] C |**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |Nominal Frequency|FO|CMOS, Dual CMOS|0.1|—|212.5|MHz| ||FO|LVDS/LVPECL/HCSL|0.1|—|250|MHz| |Total Stability*||Frequency Stability Grade C|–30|—|+30|ppm| |||Frequency Stability Grade B|–50|—|+50|ppm| |||Frequency Stability Grade A|–100|—|+100|ppm| |Temperature Stability||Frequency Stability Grade C|–20|—|+20|ppm| |||Frequency Stability Grade B|–25|—|+25|ppm| |||Frequency Stability Grade A|–50|—|+50|ppm| |Startup Time|TSU|Minimum VDDuntil output<br>frequency (FO) within specification|—|—|10|ms| |Disable Time|TD|FO10 MHz|—|—|5|µs| |||FO< 10 MHz|—|—|40|µs| |Enable Time|TE|FO10 MHz|—|—|20|µs| |||FO< 10 MHz|—|—|60|µs| |***Note:**Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and vibration<br>(not under operation), and 10 years aging at 40 oC.||||||| ***Note:** Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and vibration (not under operation), and 10 years aging at 40[o] C. **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **5** **Si510/511** ## **Table 3. Output Clock Levels and Symmetry** VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85[o] C |**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |CMOS Output Logic<br>High|VOH||0.85 x VDD|—|—|V| |CMOS Output Logic<br>Low|VOL||—|—|0.15 x VDD|V| |CMOS Output Logic<br>High Drive|IOH|3.3 V|–8|—|—|mA| |||2.5 V|–6|—|—|mA| |||1.8 V|–4|—|—|mA| |CMOS Output Logic<br>Low Drive|IOL|3.3 V|8|—|—|mA| |||2.5 V|6|—|—|mA| |||1.8 V|4|—|—|mA| |CMOS Output Rise/Fall<br>Time<br>(20 to 80% VDD)|TR/TF|0.1 to 212.5 MHz,<br>CL= 15 pF|0.45|0.8|1.2|ns| |||0.1 to 212.5 MHz,<br>CL= no load|0.3|0.6|0.9|ns| |LVPECL Output<br>Rise/Fall Time<br>(20 to 80% VDD)|TR/TF||100|—|565|ps| |HCSL Output Rise/Fall<br>Time (20 to 80% VDD)|TR/TF||100|—|470|ps| |LVDS Output Rise/Fall<br>Time (20 to 80% VDD)|TR/TF||350|—|800|ps| |LVPECL Output<br>Common Mode|VOC|50to VDD– 2 V,<br>single-ended|—|VDD–<br>1.4 V|—|V| |LVPECL Output Swing|VO|50to VDD– 2 V,<br>single-ended|0.55|0.8|0.90|VPPSE| |LVDS Output Common<br>Mode|VOC|100line-line<br>VDD= 3.3/2.5 V|1.13|1.23|1.33|V| |||100line-line, VDD= 1.8 V|0.83|0.92|1.00|V| |LVDS Output Swing|VO|Single-ended, 100differential<br>termination|0.25|0.35|0.45|VPPSE| |HCSL Output Common<br>Mode|VOC|50to ground|0.35|0.38|0.42|V| |HCSL Output Swing|VO|Single-ended|0.58|0.73|0.85|VPPSE| |Duty Cycle|DC|All formats|48|50|52|%| **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **6** **Si510/511** ## **Table 4. Output Clock Jitter and Phase Noise (LVPECL)** VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85[o] C; Output Format = LVPECL |**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |Period Jitter<br>(RMS)|JPRMS|10k samples1|—|—|1.3|ps| |Period Jitter<br>(Pk-Pk)|JPPKPK|10k samples1|—|—|11|ps| |Phase Jitter<br>(RMS)|φJ|1.875 MHz to 20 MHz integration<br>bandwidth2(brickwall)|—|0.31|0.5|ps| |||12 kHz to 20 MHz integration band-<br>width2(brickwall)|—|0.8|1.0|ps| |Phase Noise,<br>156.25 MHz|φN|100 Hz|—|–86|—|dBc/Hz| |||1 kHz|—|–109|—|dBc/Hz| |||10 kHz|—|–116|—|dBc/Hz| |||100 kHz|—|–123|—|dBc/Hz| |||1 MHz|—|–136|—|dBc/Hz| |Additive RMS<br>Jitter Due to<br>External Power<br>Supply Noise3|JPSR|10 kHz sinusoidal noise|—|3.0|—|ps| |||100 kHz sinusoidal noise|—|3.5|—|ps| |||500 kHz sinusoidal noise|—|3.5|—|ps| |||1 MHz sinusoidal noise|—|3.5|—|ps| |Spurious|SPR|LVPECL output, 156.25 MHz,<br>offset>10 kHz|—|–75|—|dBc| |**Notes:**<br>**1.** Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,<br>212.5, 250 MHz.<br>**2.**Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.<br>**3.**156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).||||||| ## **Notes:** **1.** Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 MHz. **2.** Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz. **3.** 156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP). **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **7** **Si510/511** **Table 5. Output Clock Jitter and Phase Noise (LVDS)** VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85[o] C; Output Format = LVDS |**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |Period Jitter<br>(RMS)|JPRMS|10k samples1|—|—|2.1|ps| |Period Jitter<br>(Pk-Pk)|JPPKPK|10k samples1|—|—|18|ps| |Phase Jitter<br>(RMS)|φJ|1.875 MHz to 20 MHz integration<br>bandwidth2(brickwall)|—|0.25|0.55|ps| |||12 kHz to 20 MHz integration band-<br>width2(brickwall)|—|0.8|1.0|ps| |Phase Noise,<br>156.25 MHz|φN|100 Hz|—|–86|—|dBc/Hz| |||1 kHz|—|–109|—|dBc/Hz| |||10 kHz|—|–116|—|dBc/Hz| |||100 kHz|—|–123|—|dBc/Hz| |||1 MHz|—|–136|—|dBc/Hz| |Spurious|SPR|LVPECL output, 156.25 MHz,<br>offset>10 kHz|—|–75|—|dBc| |**Notes:**<br>**1.** Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,<br>212.5, 250 MHz.<br>**2.**Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.||||||| ## **Notes:** **1.** Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 MHz. **2.** Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz. **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **8** **Si510/511** **Table 6. Output Clock Jitter and Phase Noise (HCSL)** VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85[o] C; Output Format = HCSL |**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |Period Jitter<br>(RMS)|JPRMS|10k samples*|—|—|1.2|ps| |Period Jitter<br>(Pk-Pk)|JPPKPK|10k samples*|—|—|11|ps| |Phase Jitter<br>(RMS)|φJ|1.875 MHz to 20 MHz integration<br>bandwidth*(brickwall)|—|0.25|0.30|ps| |||12 kHz to 20 MHz integration band-<br>width*(brickwall)|—|0.8|1.0|ps| |Phase Noise,<br>156.25 MHz|φN|100 Hz|—|–90|—|dBc/Hz| |||1 kHz|—|–112|—|dBc/Hz| |||10 kHz|—|–120|—|dBc/Hz| |||100 kHz|—|–127|—|dBc/Hz| |||1 MHz|—|–140|—|dBc/Hz| |Spurious|SPR|LVPECL output, 156.25 MHz,<br>offset>10 kHz|—|–75|—|dBc| |***Note:**Applies to an output frequency of 100 MHz.||||||| ***Note:** Applies to an output frequency of 100 MHz. **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **9** **Si510/511** **Table 7. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS (Complementary))** VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85[o] C; Output Format = CMOS, Dual CMOS (Complementary) |**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |Phase Jitter<br>(RMS)|φJ|1.875 MHz to 20 MHz integration<br>bandwidth2(brickwall)|—|0.25|0.35|ps| |||12 kHz to 20 MHz integration band-<br>width2(brickwall)|—|0.8|1.0|ps| |Phase Noise,<br>156.25 MHz|φN|100 Hz|—|–86|—|dBc/Hz| |||1 kHz|—|–108|—|dBc/Hz| |||10 kHz|—|–115|—|dBc/Hz| |||100 kHz|—|–123|—|dBc/Hz| |||1 MHz|—|–136|—|dBc/Hz| |Spurious|SPR|LVPECL output, 156.25 MHz,<br>offset>10 kHz|—|–75|—|dBc| |**Notes:**<br>**1.** Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,<br>212.5 MHz.<br>**2.**Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz.||||||| ## **Notes:** **1.** Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz. **2.** Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz. **Table 8. Environmental Compliance and Package Information** |**Parameter**|**Conditions/Test Method**| |---|---| |Mechanical Shock|MIL-STD-883, Method 2002| |Mechanical Vibration|MIL-STD-883, Method 2007| |Solderability|MIL-STD-883, Method 2003| |Gross and Fine Leak|MIL-STD-883, Method 1014| |Resistance to Solder Heat|MIL-STD-883, Method 2036| |Moisture Sensitivity Level|MSL 1| |Contact Pads|Gold over Nickel| **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **10** **Si510/511** ## **Table 9. Thermal Characteristics** |**Table 9. Thermal Characteristics**||||| |---|---|---|---|---| |**Parameter**|**Symbol**|**Test Condition**|**Value**|**Unit**| |Thermal Resistance Junction to Ambient|JA|Still air|110|°C/W| ## **Table 10. Absolute Maximum Ratings[1]** |**Table 10. Absolute Maximum Ratings1**|||| |---|---|---|---| |**Parameter**|**Symbol**|**Rating**|**Unit**| |Maximum Operating Temperature|TAMAX|85|oC| |Storage Temperature|TS|–55 to +125|oC| |Supply Voltage|VDD|–0.5 to +3.8|V| |Input Voltage (any input pin)|VI|–0.5 to VDD+ 0.3|V| |ESD Sensitivity (HBM, per JESD22-A114)<br>|HBM|2|kV| |Soldering Temperature (Pb-free profile)~~2~~<br>|TPEAK|260|oC| |Soldering Temperature Time at TPEAK(Pb-free profile)~~2~~|TP|20–40|sec| |**Notes:**<br>**1.** Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation or<br>specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended<br>periods may affect device reliability.<br>**2.**The device is compliant with JEDEC J-STD-020.|||| ## **Notes:** **1.** Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. **2.** The device is compliant with JEDEC J-STD-020. **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **11** **Si510/511** ## **2. Pin Descriptions** **==> picture [492 x 107] intentionally omitted <==** **----- Start of picture text -----**<br> OE 1 4 VDD NC 1 6 VDD OE 1 6 VDD<br>OE 2 5 CLK–* NC 2 5 CLK–*<br>GND 2 3 CLK GND 3 4 CLK+ GND 3 4 CLK+<br>Si510 (CMOS) Si510 (LVDS/LVPECL/HCSL/Dual CMOS*) Si511 (LVDS/LVPECL/HCSL/DualCMOS)*)<br>**----- End of picture text -----**<br> *Supports integrated 1:2 CMOS buffer. See ordering information and section 2.1“Dual CMOS Buffer”. **Table 11. Si510 Pin Descriptions (CMOS)** |**Pin**|**Name**|**CMOS Function**| |---|---|---| |1|OE|Output Enable. Includes internal pull-up for OE active high. Includes<br>internalpull-down for OE active low. See orderinginformation.| |2|GND|Electrical and Case Ground.| |3|CLK|Clock Output.| |4|VDD|Power Supply Voltage.| **Table 12. Si510 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 2)** |**Pin**|**Name**|**LVPECL/LVDS/HCSL Function**| |---|---|---| |1|NC|No connect. Make no external connection to this pin.| |2|OE|Output Enable. Includes internal pull-up for OE active high. Includes<br>internalpull-down for OE active low. See orderinginformation.| |3|GND|Electrical and Case Ground.| |4|CLK+|Clock Output.| |5|CLK–|Complementary Clock Output.| |6|VDD|Power Supply Voltage.| **Table 13. Si511 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 1)** |**Pin**|**Name**|**LVPECL/LVDS/HCSL Function**| |---|---|---| |1|OE|Output Enable. Includes internal pull-up for OE active high. Includes<br>internalpull-down for OE active low. See orderinginformation.| |2|NC|No connect. Make no external connection to this pin.| |3|GND|Electrical and Case Ground.| |4|CLK+|Clock Output.| |5|CLK–|Complementary Clock Output.| |6|VDD|Power Supply Voltage.| **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **12** **Si510/511** ## **2.1. Dual CMOS Buffer** Dual CMOS output format ordering options support either complementary or in-phase output signals. This feature enables replacement of multiple XOs with a single Si510/11 device. **==> picture [394 x 211] intentionally omitted <==** **----- Start of picture text -----**<br> ~<br>Complementary<br>Outputs<br>~<br>In-Phase<br>Outputs<br>**----- End of picture text -----**<br> **Figure 1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs** **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **13** **Si510/511** ## **3. Ordering Information** The Si510/511 supports a wide variety of options including frequency, stability, output format, and VDD. Specific device configurations are programmed into the Si510/511 at time of shipment. Configurations can be specified using the Part Number Configuration chart below. Silicon Labs provides a web browser-based part number configuration utility to simplify this process. Refer to www.silabs.com/VCXOpartnumber to access this tool. The Si510/511 XO series is supplied in industry-standard, RoHS compliant, lead-free, 3.2 x 5.0 mm and 5 x 7 mm packages. Tape and reel packaging is an ordering option. |||||||||||||||||||||| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| ||**Series**||**Output Format**|||**OE Pin**|||**Package**||||**A = Revision: A**<br>**G = Temp Range: -40°C to 85°C**<br>**R = Tape & Reel; Blank = Trays.**|||||||| ||**510**||**CMOS**|||**OE**|**on pin 1**|||**4-pin**||||||||||| ||**510**||**LVPECL, LVDS, HCSL, Dual CMOS**|||**OE**|**on pin 2**|||**6-pin**||||||||||| ||**511**||**LVPECL, LVDS, HCSL, Dual CMOS**|||**OE**|**on pin 1**|||**6-pin**||||||||||| ||**1st Option Code:**<br>**Output Format**<br>**VDD**<br>**Outut Format**|||||||||||||||||**AGR**||| ||||||||**51X**|||**X**||**X**<br>**X**<br>**XXXMXXX**<br>**X**||||||||| |||**VDD**||**Outut Format**||||||||||||||||| |||||**p**||||||||||||||||| ||**A**|**3.3V**||**LVPECL**||||||||||||||||| |||||||||||||||||||||| ||**B**|**3.3V**||**LVDS**||||||||||||||||| ||**C**|**3.3V**||**CMOS**||||||||||||||||| |||||||||||||||||||||| ||**D**|**3 3V**<br>**.**||**HCSL**||||||||**3rd Option Code:**<br>**Output Enable**<br>**OE Polarity**<br>**A**<br>**OE Active High**|||||**Package Option**<br>**Dimensions**<br>**A**<br>**5 x 7 mm**|||| ||**E**|**2.5V**||**LVPECL**||||||||||||||||| ||**F**|**2.5V**||**LVDS**||||||||||||||||| |||||||||||||||**OE Polarity**|||||**Dimensions**|| ||**G**|**2.5V**||**CMOS**||||||||||||||||| |||||||||||||**A**||**OE Active High**|||**A**||**5 x 7 mm**|| ||**H**|**2 5V**<br>**.**||**HCSL**||**2nd Option Code:**<br>||||||||||||||| ||**J**|**1.8V**||**LVDS**||||||||**B**||**OE Active Lo**|**w**||**B**||**3.2 x 5 mm**|| ||**K**|**1.8V**||**CMOS**||||||||||||||||| ||**L**|**1.8V**||**HCSL**||||||||||||||||| |||||<br><br>||||||||||||||||| ||**M**|**3 3V**<br>**.**||**D**<br>**l CMOS (I**<br>**h**<br>**)**<br>**ua**<br>**n-p ase**||**Frequency Stability**<br>**Total**<br>**Temperature**<br>**A**<br>**±100ppm**<br>**±50ppm**<br>**B**<br>**±50**<br>**±25**|||||||||**F**<br>**requency**||**D**<br>**i ti**<br>**escr p on**|||| ||**N**|**3.3V**||**Dual CMOS (Complementary)**||||**Total**|||**Temperature**||||**Mxxxxxx**|**fOUT < 1 M**|**Hz**|||| ||**P**|**2.5V**||**Dual CMOS (In-phase)**||**A**||**±100ppm**|||**±50ppm**||||**xMxxxxx**|**1 MHz �**|**fOUT < 10 MHz**|||| ||**Q**|**2.5V**||**Dual CMOS (Complementary)**|||||||||||**xxMxxxx**|**10 MHz �**|**fOUT < 100 MHz**|||| |||||||**B**||**±50**|||**±25**|||||||||| ||**R**|**1.8V**||**Dual CMOS (In-phase)**||||**ppm**|||**ppm**||||**xxxMxxx**|**100 MHz**|**� fOUT < 250 MHz**|||| ||**S**|**1.8V**||**Dual CMOS (Complementary)**||**C**||**±30ppm**|||**±20ppm**||||**xxxxxx**|**Code if frequency requires >6 digit resolution**||||| **Figure 2. Part Number Syntax** Example orderable part number: 510ECB156M250AAG supports 2.5 V LVPECL, ±30 ppm total stability, OE active low in 5 x 7 mm package across –40[o] C to 85[o] C temperature range. The output frequency is 156.25 MHz. **Note:** CMOS and Dual CMOS maximum frequency is 212.5 MHz. **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **14** **Si510/511** ## **4. Si510/511 Mark Specification** Figure 3 illustrates the mark specification for the Si510/511. Use the part number configuration utility located at: www.silabs.com/VCXOpartnumber to cross-reference the mark code to a specific device configuration. ## 0 C CC CC T T T T T T Y Y WW 0 = Si510, 1 = Si511 CCCCC = mark code TTTTTT = assembly manufacturing code YY = year WW = work week ## **Figure 3. Top Mark** **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **15** **Si510/511** ## **5. Package Outline Diagram: 5 x 7 mm, 4-pin** Figure 4 illustrates the package details for the 5 x 7 mm Si510/511. Table 14 lists the values for the dimensions shown in the illustration. **==> picture [460 x 217] intentionally omitted <==** **Figure 4. Si510/511 Outline Diagram** **Table 14. Package Diagram Dimensions (mm)** |**Dimension**|**Min**|**Nom**| |---|---|---| |A|1.50|1.65| |b|1.30|1.40| |c|0.50|0.60| |D||| |D1|4.30|4.40| |e||| |f||| |E||| |E1|6.10|6.20| |H|0.55|0.65| |L|1.17|1.27| |L1|0.05|0.10| |p|2.50|2.60| |aaa||| |bbb||| |ccc||| |ddd||| |eee||| ## **Notes:** **1.** All dimensions shown are in millimeters (mm) unless otherwise noted. **2.** Dimensioning and Tolerancing per ANSI Y14.5M-1994. **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **16** **Si510/511** ## **6. PCB Land Pattern: 5 x 7 mm, 4-pin** Figure 5 illustrates the 5 x 7 mm PCB land pattern for the 5 x 7 mm Si510/511. Table 15 lists the values for the dimensions shown in the illustration. **==> picture [226 x 222] intentionally omitted <==** **Figure 5. Si510/511 PCB Land Pattern** **Table 15. PCB Land Pattern Dimensions (mm)** |**Dimension**|**(mm)**| |---|---| |C1|4.20| |E|5.08| |X1|1.55| |Y1|1.95| ## **Notes:** ## **General** **1.** All dimensions shown are in millimeters (mm) unless otherwise noted. **2.** Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. **3.** This Land Pattern Design is based on the IPC-7351 guidelines. **4.** All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. ## **Solder Mask Design** **5.** All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. **Stencil Design** **6.** A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. **7.** The stencil thickness should be 0.125 mm (5 mils). **8.** The ratio of stencil aperture to land pad size should be 1:1. **Card Assembly** **9.** A No-Clean, Type-3 solder paste is recommended. **10.** The recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for Small Body Components. **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **17** **Si510/511** ## **7. Package Outline Diagram: 5 x 7 mm, 6-pin** Figure 6 illustrates the package details for the Si510/511. Table 16 lists the values for the dimensions shown in the illustration. **==> picture [442 x 207] intentionally omitted <==** **Figure 6. Si510/511 Outline Diagram** **Table 16. Package Diagram Dimensions (mm)** |**Dimension**|**Dimension**|**Min**|**Nom**|**Max**| |---|---|---|---|---| ||A|1.50|1.65|1.80| ||b|1.30|1.40|1.50| ||c|0.50|0.60|0.70| ||D||5.00 BSC|| ||D1|4.30|4.40|4.50| ||e||2.54 BSC|| ||E||7.00 BSC|| ||E1|6.10|6.20|6.30| ||H|0.55|0.65|0.75| ||L|1.17|1.27|1.37| ||L1|0.05|0.10|0.15| ||p|1.80|—|2.60| ||R||0.70 REF|| ||aaa||0.15|| ||bbb||0.15|| ||ccc||0.10|| ||ddd||0.10|| ||eee||0.05|| |**Notes:**||||| |**1.**|All dimensions shown are in millimeters (mm) unless otherwise noted.|||| |**2.**|Dimensioningand Tolerancing per ANSI Y14.5M-1994.|||| **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **18** **Si510/511** ## **8. PCB Land Pattern: 5 x 7 mm, 6-pin** Figure 7 illustrates the 5 x 7 mm PCB land pattern for the Si510/511. Table 17 lists the values for the dimensions shown in the illustration. **==> picture [198 x 188] intentionally omitted <==** **Figure 7. Si510/511 PCB Land Pattern** **Table 17. PCB Land Pattern Dimensions (mm)** ||**Dimension**|**(mm)**| |---|---|---| ||C1|4.20| ||E|2.54| ||X1|1.55| ||Y1|1.95| |**Notes:**||| |**General**||| **1.** All dimensions shown are in millimeters (mm) unless otherwise noted. **2.** Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. **3.** This Land Pattern Design is based on the IPC-7351 guidelines. **4.** All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. ## **Solder Mask Design** **5.** All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. - **Stencil Design** **6.** A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. **7.** The stencil thickness should be 0.125 mm (5 mils). **8.** The ratio of stencil aperture to land pad size should be 1:1. **Card Assembly** **9.** A No-Clean, Type-3 solder paste is recommended. **10.** The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **19** **Si510/511** ## **9. Package Outline Diagram: 3.2 x 5 mm, 4-pin** Figure 8 illustrates the package details for the 3.2 x 5 mm Si510/511. Table 18 lists the values for the dimensions shown in the illustration. **==> picture [394 x 205] intentionally omitted <==** **Figure 8. Si510/511 Outline Diagram** **Table 18. Package Diagram Dimensions (mm)** |**Dimension**<br>**Min**<br>**Nom**<br>**Max**<br>A<br>1.06<br>1.17<br>1.28<br>b<br>1.10<br>1.20<br>1.30<br>c<br>0.70<br>0.80<br>0.90<br>D<br>3.20 BSC<br>D1<br>2.55<br>2.60<br>2.65<br>e<br>2.54 BSC<br>f<br>0.40 TYP<br>E<br>5.00 BSC<br>E1<br>4.35<br>4.40<br>4.45<br>H<br>0.40<br>0.50<br>0.60<br>L<br>0.90<br>1.00<br>1.10<br>L1<br>0.05<br>0.10<br>0.15<br>p<br>1.17<br>1.27<br>1.37<br>aaa<br>0.15<br>bbb<br>0.15<br>ccc<br>0.10<br>ddd<br>0.10<br>eee<br>0.05<br>**Notes:**<br>**1.** All dimensions shown are in millimeters (mm) unless otherwise noted.<br>**2.**Dimensioningand Tolerancing per ANSI Y14.5M-1994.|**n**<br>**Min**|**Nom**|**Max**| |---|---|---|---| ||1.06|1.17|1.28| ||1.10|1.20|1.30| ||0.70|0.80|0.90| ||3.20 BSC||| ||2.55|2.60|2.65| ||2.54 BSC||| ||0.40 TYP||| ||5.00 BSC||| ||4.35|4.40|4.45| ||0.40|0.50|0.60| ||0.90|1.00|1.10| ||0.05|0.10|0.15| ||1.17|1.27|1.37| ||0.15||| ||0.15||| ||0.10||| ||0.10||| ||0.05||| **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **20** **Si510/511** ## **10. PCB Land Pattern: 3.2 x 5 mm, 4-pin** Figure 9 illustrates the 3.2 x 5 mm PCB land pattern for the Si510/511. Table 19 lists the values for the dimensions shown in the illustration. **==> picture [246 x 216] intentionally omitted <==** **Figure 9. Si510/511 PCB Land Pattern** **Table 19. PCB Land Pattern Dimensions (mm)** |**Dimension**|**(mm)**| |---|---| |C1|2.60| |E|2.54| |X1|1.35| |Y1|1.70| |**Notes:**<br>**General**<br>**1.** All dimensions shown are in millimeters (mm) unless otherwise noted.<br>**2.**Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.<br>**3.**This Land Pattern Design is based on the IPC-7351 guidelines.<br>**4.**All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition<br>(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.<br>**Solder Mask Design**<br>**5.**All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder<br>mask and the metal pad is to be 60 µm minimum, all the way around the pad.<br>**Stencil Design**<br>**6.**A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be<br>used to assure good solder paste release.<br>**7.**The stencil thickness should be 0.125 mm (5 mils).<br>**8.**The ratio of stencil aperture to land pad size should be 1:1.<br>**Card Assembly**<br>**9.**A No-Clean, Type-3 solder paste is recommended.<br>**10.**The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for<br>Small Body Components.|| **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **21** **Si510/511** ## **11. Package Outline Diagram: 3.2 x 5 mm, 6-Pin** Figure 10 illustrates the package details for the 3.2 x 5 mm Si510/511. Table 20 lists the values for the dimensions shown in the illustration. **==> picture [424 x 221] intentionally omitted <==** **Figure 10. Si510/511 Outline Diagram** **Table 20. Package Diagram Dimensions (mm)** |**Dimension**|**Min**|**Nom**|**Max**| |---|---|---|---| |A|1.06|1.17|1.28| |b|0.54|0.64|0.74| |c|0.35|0.45|0.55| |D|3.20 BSC||| |D1|2.55|2.60|2.65| |e|1.27 BSC||| |E|5.00 BSC||| |E1|4.35|4.40|4.45| |H|0.45|0.55|0.65| |L|0.90|1.00|1.10| |L1|0.05|0.10|0.15| |p|1.17|1.27|1.37| |R|0.32 REF||| |aaa|0.15||| |bbb|0.15||| |ccc|0.10||| |ddd|0.10||| |eee|0.05||| |**otes:**<br>**1.** All dimensions shown are in millimeters (mm) unless otherwise noted.<br>**2.**Dimensioningand Tolerancing per ANSI Y14.5M-1994.|||| **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **22** **Si510/511** ## **12. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin** Figure 11 illustrates the 3.2 x 5.0 mm PCB land pattern for the Si510/511. Table 21 lists the values for the dimensions shown in the illustration. **==> picture [274 x 213] intentionally omitted <==** **Figure 11. Si510/511 Recommended PCB Land Pattern** **Table 21. PCB Land Pattern Dimensions (mm)** |**Dimension**|**(mm)**| |---|---| |C1|2.60| |E|1.27| |X1|0.80| |Y1|1.70| **Notes: General** **1.** All dimensions shown are in millimeters (mm) unless otherwise noted. **2.** Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. **3.** This Land Pattern Design is based on the IPC-7351 guidelines. **4.** All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. - **Solder Mask Design** **5.** All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. - **Stencil Design** **6.** A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. **7.** The stencil thickness should be 0.125 mm (5 mils). **8.** The ratio of stencil aperture to land pad size should be 1:1. **Card Assembly** **9.** A No-Clean, Type-3 solder paste is recommended. **10.** The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **23** **Si510/511** ## **DOCUMENT CHANGE LIST** ## **Revision 0.9 to Revision 1.0** - Updated Table 1 on page 4. - Updates to supply current typical and maximum values for CMOS, LVDS, LVPECL and HCSL. - CMOS frequency test condition corrected to 100 MHz. - Updates to OE VIH minimum and VIL maximum values. - Updated Table 2 on page 5. - Dual CMOS nominal frequency maximum added. - Total stability footnotes clarified for 10 year aging at 40 °C. - Disable time maximum values updated. - Enable time parameter added. - Updated Table 3 on page 6. - CMOS output rise / fall time typical and maximum values updated. - LVPECL/HCSL output rise / fall time maximum value updated. - LVPECL output swing maximum value updated. - LVDS output common mode typical and maximum values updated. - HCSL output swing maximum value updated. - Duty cycle minimum and maximum values tightened to 48/52%. - Updated Table 4 on page 7. - Phase jitter test condition and maximum value updated. - Phase noise typical values updated. - Additive RMS jitter due to external power supply noise typical values updated. - Footnote 3 updated limiting the VDD to 2.5/3.3V - Added Tables 5, 6, 7 for LVDS, HCSL, CMOS, and Dual CMOS operations. - Moved Absolute Maximum Ratings table. - Added note to Figure 2 clarifying CMOS and Dual CMOS maximum frequency. - Updated Figure 10 outline diagram to correct pinout. ## **Revision 1.0 to Revision 1.1** - Updated Table 3. - CMOS Output Rise/Fall Time Test Condition updated. ## **Revision 1.1 to Revision 1.2** - Updated Table 3. - Separated LVPECL and HCSL output Rise/Fall time specs. - Min Rise/Fall times added. **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **24** **Si510/511** ## **NOTES:** **==> picture [72 x 54] intentionally omitted <==** **Rev. 1.2** **25** **==> picture [536 x 177] intentionally omitted <==** **----- Start of picture text -----**<br> ClockBuilder Pro<br>One-click access to Timing tools,<br>documentation, software, source<br>code libraries & more. Available for k<br>Windows and iOS (CBGo only). a<br>www.silabs.com/CBPro<br>anne<br>=| 10 |«=<br>S| YEAR| =<br>onan<br>Timing Portfolio SW/HW Quality Support and Community<br>www.silabs.com/timing www.silabs.com/CBPro www.silabs.com/quality community.silabs.com<br>**----- End of picture text -----**<br> ## **Disclaimer** Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. 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Updated at April 28, 2026
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