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453-00091C
Bluetooth Module, BLE 5.3, 2 Mbps, -95.9 dBm, 1.8 V to 3.8 V, -40 °C to 105 °C
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: EZURIO
- Product type: Bluetooth Modules & Adaptors
- SVHC: To Be Advised
- Interfaces: EUART, I2C, I2S, SPI, UART
- Product Range: Lyra Series
- Certifications: CE, FCC, IC, ISED, KC, MIC
- Bluetooth Class: -
- Bluetooth Version: Bluetooth 5.3
- Supply Voltage Range: 1.8 V to 3.8 V
- Receiver Sensitivity Rx: -95.9 dBm
- Operating Temperature Range: -40 °C to 105 °C
| Delivery and price | |
|---|---|
| Units per pack | 250 |
| Price | 3.81 € |
| Current stock | 500+ |
| Lead time | 30 days |
Datasheet
A
_Version 1.1_
|**Version**||**Date**|**Notes**|**Contributors**|**Approver**|
|---|---|---|---|---|---|
|1.0|18 Feb 2022|18 Feb 2022|Initial Release|Raj Khatri,|Jonathan Kaye|
|||||Dave Drogowski||
|1.1|10 June 2022|10 June 2022|Updates to5 Reference Diagramsand added|Greg Leach,|Jonathan Kaye|
||||5.3 Boot|Raj Khatri,||
|||||Dave Drogowski||
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|1|Introduction .......................................................................................................................................................................... 5|Introduction .......................................................................................................................................................................... 5|
|---|---|---|
||1.1|Key Features .............................................................................................................................................................. 5|
||1.2|Hardware Features..................................................................................................................................................... 6|
||1.3|Firmware Options ....................................................................................................................................................... 6|
|2|Ordering Information ............................................................................................................................................................ 7||
|3|System Overview ................................................................................................................................................................. 8||
||3.1|Introduction ................................................................................................................................................................ 8|
||3.2|EFR32BG22 SoC ....................................................................................................................................................... 9|
||3.3|Internal Antenna ......................................................................................................................................................... 9|
||3.4|External Antenna ........................................................................................................................................................ 9|
||3.5|Power Supply ............................................................................................................................................................. 9|
|4|Electrical Characteristics ................................................................................................................................................... 10||
||4.1|Absolute Maximum Ratings ...................................................................................................................................... 10|
||4.2|General Operating Conditions .................................................................................................................................. 11|
||4.3|MCU Current Consumption with 3 V Supply ............................................................................................................ 13|
||4.4|Radio Current Consumption with 3 V Supply ........................................................................................................... 14|
||4.5|RF Transmitter General Characteristics for the 2.4 GHz Band ................................................................................ 15|
||4.6|RF Receiver General Characteristics for the 2.4 GHz Band .................................................................................... 15|
||4.7|RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate ............................. 16|
||4.8|RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate ............................. 17|
||4.9|RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate .......................... 18|
||4.10|RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 125 kbps Data Rate .......................... 19|
||4.11|High-Frequency Crystal ............................................................................................................................................ 20|
||4.12|Low Frequency Crystal Oscillator ............................................................................................................................. 20|
||4.13|Precision Low Frequency RC Oscillator (LFRCO) ................................................................................................... 21|
||4.14|GPIO Pins ................................................................................................................................................................ 22|
||4.15|Microcontroller Peripherals ....................................................................................................................................... 23|
||4.16|Typical Performance Curves .................................................................................................................................... 23|
|5|Reference Diagrams .......................................................................................................................................................... 25||
||5.1|Network Co-Processor (NCP) Application with UART Host ..................................................................................... 25|
||5.2|SoC Application ........................................................................................................................................................ 26|
||5.3|Boot .......................................................................................................................................................................... 26|
|6|Pin Definitions .................................................................................................................................................................... 27|Pin Definitions .................................................................................................................................................................... 27|
||6.1|Lyra S 44-Pin SiP Module Device Pinout ................................................................................................................. 27|
||6.2|Alternate Function Table .......................................................................................................................................... 29|
||6.3|Analog Peripheral Connectivity ................................................................................................................................ 29|
||6.4|Digital Peripheral Connectivity ................................................................................................................................. 30|
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3
© Copyright 2022 Laird Connectivity All Rights Reserved
|7|Design Guidelines ............................................................................................................................................................. 32|Design Guidelines ............................................................................................................................................................. 32|
|---|---|---|
||7.1|Layout and Placement .............................................................................................................................................. 32|
||7.2|Best Design Practices .............................................................................................................................................. 35|
||7.3|Internal Antenna Radio Performance vs. Carrier Board Size ................................................................................... 37|
||7.4|Proximity to Other Materials ..................................................................................................................................... 37|
||7.5|Proximity to Human Body ......................................................................................................................................... 37|
||7.6|Lyra S module 50Ohms RF track design for connecting external antenna ............................................................... 38|
||7.7|External Antenna Integration with the Lyra S module .............................................................................................. 41|
|8|Mechanical Specifications ................................................................................................................................................. 42||
||8.1|Package Dimensions................................................................................................................................................ 42|
||8.2|Recommended PCB Land Pattern ........................................................................................................................... 43|
||8.3|Lyra S Top Marking .................................................................................................................................................. 44|
|9|Soldering Recommendations............................................................................................................................................. 45||
||9.1|Reflow for lead Free Solder Paste ........................................................................................................................... 45|
||9.2|Recommended Reflow Profile for lead Free Solder Paste ....................................................................................... 45|
|10|Miscellaneous .................................................................................................................................................................... 46||
||10.1|Cleaning ................................................................................................................................................................... 46|
||10.2|Rework ..................................................................................................................................................................... 46|
||10.3|Handling and Storage............................................................................................................................................... 46|
|11|Tape and Reel ................................................................................................................................................................... 47|Tape and Reel ................................................................................................................................................................... 47|
|12|Regulatory ......................................................................................................................................................................... 48||
|13|Bluetooth SIG Qualification ............................................................................................................................................... 49||
||13.1|Overview .................................................................................................................................................................. 49|
||13.2|Qualification Steps When Referencing on End Product Listing ................................................................................ 49|
|14|Additional Assistance ........................................................................................................................................................ 51||
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The Lyra S is a module designed and built to meet the performance, security, and reliability requirements of battery-powered IoT products running on Bluetooth networks.
Based on the EFR32BG22 SoC, the Lyra S enables Bluetooth[® ] Low Energy connectivity while delivering best-in-class RF range and performance, future-proof capability for feature and OTA firmware updates, enhanced security features, and low energy consumption.
Lyra S modules are a full solution that comes with fully-upgradeable, robust software stacks, world-wide regulatory certifications, advanced development and debugging tools, and support that will minimize and simplify the engineering and development of your end-products helping to accelerate their time-to-market.
The Lyra S is intended for a broad range of applications, including:
- Asset Tags and Beacons
- Portable Medical
- Sports, Fitness, and Wellness devices
- Connected Home
- Industrial and Building Automation
- Bluetooth mesh Low Power Nodes
- Bluetooth 5.3
- Built-in antenna or RF pin
- Up to 6 dBm TX power
- -98.6 dBm BLE RX sensitivity at 1 Mbps
- 512/32 kB of Flash/RAM memory
- Optimal selection of MCU peripherals
- ▪ 25 GPIO pins
- 6 mm × 6 mm × 1.1 mm
- 32-bit ARM Cortex-M33 core at up to 76.8 MHz
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## ▪ **Supported Protocols**
- Bluetooth Low Energy (Bluetooth 5.3)
- Direction finding
- 1M, 2M, and LE Coded PHYs
- Bluetooth Mesh Low Power Node
- Wireless System-on-Chip
- 2.4 GHz radio
- TX power up to 6 dBm
- High-performance 32-bit ARM Cortex-M33[® ] with DSP instruction and floating-point unit for efficient signal processing
- Up to 512 kB flash program memory
- 32 kB RAM data memory
- Embedded Trace Macrocell (ETM) for advanced debugging
## **High Receiver Performance**
-
- -106.4 dBm sensitivity (0.1% BER) at 125 kbps GFSK
- -102.3 dBm sensitivity (0.1% BER) at 500 kbps GFSK
- -98.6 dBm sensitivity (0.1% BER) at 1 Mbps GFSK
- -95.9 dBm sensitivity (0.1% BER) at 2 Mbps GFSK
## **Low-Energy Consumption**
## ▪
- 4.2 mA RX current at 1 Mbps GFSK
- 4.6 mA TX current at 0 dBm output power
- 26 µA/MHz in Active Mode (EM0)
- 1.40 μA EM2 Deep Sleep current (RTCC running from LFXO, Full RAM retention)
## **Regulatory Certifications**
-
- FCC
- CE
- IC/ISED
- MIC/TELEC
- KCC
## **Wide Operating Range**
-
- 1.8 to 3.8 V
- -40 to +105 °C
## ▪ **Dimensions**
- 6 mm × 6 mm × 1.1 mm
## **Security Features**
## ▪
– Secure Boot with Root of Trust and Secure Loader (RTSL)
- Hardware Cryptographic Acceleration for AES128/256, SHA-1, SHA-2 (up to 256-bit), ECC (up to 256-bit), ECDSA, and ECDH
- – True Random Number Generator (TRNG) compliant with NIST SP800-90 and AIS-31
- – ARM[® ] TrustZone[®]
- Secure Debug with lock/unlock
## ▪ **Wide Selection of MCU Peripherals**
- Analog to Digital Converter (ADC)
- 12-bit @ 1 Msps
- 16-bit @ 76.9 ksps
- 25 General Purpose I/O pins with output state retention and asynchronous interrupts
- 8 Channel DMA Controller
- 12 Channel Peripheral Reflex System (PRS)
- – 4 × 16-bit Timer/Counter with 3 Compare/Capture/PWM channels
- – 1 × 32-bit Timer/Counter with 3 Compare/Capture/PWM channels
- 32-bit Real Time Counter
- 24-bit Low Energy Timer for waveform generation
- – 1 × Watchdog Timer
- 2 × Universal Synchronous/Asynchronous Receiver/Transmitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I[2] S)
- 1 × Enhanced Universal Asynchronous Receiver/Transmitter (EUART)
- 2 × I[2] C interface with SMBus support
- Digital microphone interface (PDM) RFSENSE with selective OOK mode
-
-
The Lyra series supports three different firmware options for software development:
**AT Command Set –** fully featured and extensible to suit any developer’s needs.
- Proven over 5+ years
- Basic Bluetooth LE cable replacement
- Simplest implementation possible
- Includes all key features of Wireless Xpress and more
**Wireless Xpress –** Frozen at current release, path for existing Silicon Labs customers
- Basic Bluetooth LE cable replacement
- Secure FOTA capable FW
- Xpress command API for iOS & Android
**C Code –** Full software development with Silicon Labs SDK and Toolchain
- Native C code development
- Use Simplicity Studio IDE
- Full functionality of Silicon Labs HW / SW
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## _**Table 1: Ordering Information**_
|**Part**|**Description**|
|---|---|
|453-00091R|Lyra Series - Bluetooth v5.3 SIP Module with antenna options (Silicon Labs EFR32BG22) - Tape / Reel|
|453-000091C|Lyra Series - Bluetooth v5.3 SIP Module with antenna options (Silicon Labs EFR32BG22) – Cut / Tape|
|453-00091-K1|Lyra Series - Development Kit - Bluetooth v5.3 SIP Module with antenna options|
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The Lyra S module combines an energy-friendly MCU with a highly integrated radio transceiver in a SiP module with a robust, integrated antenna. This section gives a short introduction to the features of the module.
The block diagram for the Lyra S module is shown in the figure below. The wireless module includes the EFR32BG22 wireless System on a Chip (SoC), required decoupling capacitors and inductors, 38.4 MHz crystal, RF matching circuit, and integrated antenna.
_**Figure 1: Lyra S**_
A simplified internal schematic for the Lyra S module is shown in the figure below.
_**Figure 2: Lyra S Module Schematic**_
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The EFR32BG22 SoC features a 32-bit ARM Cortex M33 core, a 2.4 GHz high-performance radio, 512 kB of flash memory, a rich set of MCU peripherals, and various clock management and serial interfacing options. Consult the EFR32xG22 Wireless Gecko Reference Manual and the EFR32BG22 Data Sheet for details.
Lyra S module includes an integral antenna on board with the characteristics detailed in the tables below.
**Table 2: Antenna Efficiency and Peak Gain (Lyra S)**
|**Parameter**|**With optimal**<br>**layout**|**Note**|
|---|---|---|
|Efficiency|-1 to -2 dB|Antenna efficiency, gain and radiation pattern are highly dependent on the application|
|Peak gain|2.3 dBi|PCB layout and mechanical design. Refer toDesign Guidelines for recommendations<br>to achieve optimal antenna performance.|
Lyra S module can be used with external antennas (certified by Laird Connectivity) and requires a RF 50 Ohm track (Grounded Coplanar Waveguide) to be designed to run from Lyra S module RF_2G4 (pin3) to an RF antenna connector (IPEX MHF 4) on the host PCB. The 50Ohms RF track design and length MUST be copied as defined in section 7.6 Lyra S module 50Ohms RF track design for connecting external antenna.
The list of supported external antennas (certified by Laird Connectivity) are in listed in section 7.7 External Antenna Integration with the Lyra S module.
The Lyra S requires a single nominal supply level of 3.0 V to operate. All necessary decoupling and filtering components are included in the module, and the supply is fully regulated internally.
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All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
- Typical values are based on TA=25 °C and VREGVDD supply at 3.0 V, by production test and/or technology characterization.
- Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature, unless stated otherwise.
Stresses beyond those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions beyond those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
_**Table 3: Absolute Maximum Ratings**_
|**_Table 3: Absolute Maximum Ratings_**||||||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**|**Min**||**Typ**|**Max**|**Unit**|
|Storage temperature range|TSTG||-50|—|—|+150|°C|
|Voltage on any supply pin|VDDMAX||-0.3|—|—|3.8|V|
|Junction temperature|TJMAX|-G grade|—|—|—|+105|°C|
|||-N grade|—|—|—|+105|°C|
|Voltage ramp rate on any supply pin|VDDRAMPMAX||—|—|—|1.0|V / µs|
|DC voltage on any GPIO pin|VDIGPIN||-0.3|—|—|VIOVDD+ 0.3|V|
|Input RF level on RF pin RF_2G4|PRFMAX2G4||—|—|—|+10|dBm|
|Absolute voltage on RF pin RF_2G4|VMAX2G4||-0.3|—|—|VVREG+ 0.3|V|
|Total current into VDD power lines|IVDDMAX|Source|—|—|—|200|mA|
|Total current into VSS ground lines|IVSSMAX|Sink|—|—|—|200|mA|
|Current per I/O pin|IIOMAX|Sink|—|—|—|50|mA|
|||Source|—|—|—|50|mA|
|Current for all I/O pins|IIOALLMAX|Sink|—|—|—|200|mA|
|||Source|—|—|—|200|mA|
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This table specifies the general operating temperature range and supply voltage range for all supplies. The minimum and maximum values of all other tables are specified over this operating range, unless otherwise noted.
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Operating ambient temperature range|TA|-N temperature grade|-40|—|+105|°C|
|IOVDDx operating supply voltage (All|VIOVDDx||1.71|3.0|3.8|V|
|IOVDD pins)|||||||
|VREGVDD operating supply voltage|VVREGVDD|DCDC in regulation1|2.2|3.0|3.8|V|
|||DCDC in bypass|1.8|3.0|3.8|V|
|HCLK and SYSCLK frequency|fHCLK|VSCALE2, MODE =|—|—|76.8|MHz|
|||WS1|||||
|||VSCALE2, MODE =|—|—|40|MHz|
|||WS0|||||
|PCLK frequency|fPCLK|VSCALE2|—|—|50|MHz|
|||VSCALE1|—|—|40|MHz|
|EM01 Group A clock frequency|fEM01GRPACLK|VSCALE2|—|—|76.8|MHz|
|||VSCALE1|—|—|40|MHz|
|EM01 Group B clock frequency|fEM01GRPBCLK|VSCALE2|—|—|76.8|MHz|
|||VSCALE1|—|—|40|MHz|
|Radio HCLK frequency2|fRHCLK|VSCALE2 or|—|38.4|—|MHz|
|||VSCALE1|||||
## **Note:**
1. The supported maximum VVREGVDD in regulation mode is a function of temperature and 10-year lifetime average load current. See more details in DC-DC Operating Limits.
2. The recommended radio crystal frequency is 38.4 MHz. Any crystal frequency other than 38.4 is expressly not supported.
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The maximum supported voltage on the VREGVDD supply pin is limited under certain conditions. Maximum input voltage is a function of temperature and the average load current over a 10-year lifetime. Figure 3 shows the safe operating region under specific conditions. Exceeding this safe operating range may impact the reliability and performance of the DC-DC converter.
The average load current for an application can typically be determined by examining the current profile during the time the device is powered. For example, an application that is continuously powered which spends 99% of the time asleep consuming 2 µA and 1% of the time active and consuming 10 mA has an average lifetime load current of about 102 µA.
_**Figure 3: Lifetime average load current limit vs. Maximum input voltage**_
The minimum input voltage for the DC-DC in EM0/EM1 mode is a function of the maximum load current, and the peak current setting. Figure 4 shows the max load current vs. input voltage for different DC-DC peak inductor current settings.
_**Figure 4: Transient maximum load current vs. Minimum input voltage**_
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Unless otherwise indicated, typical conditions are: Module supply voltage = 3.0 V. Voltage scaling level = VSCALE1. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C.
_**Table 4: MCU Current Consumption with 3 V Supply**_
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Current consumption in EM0|IACTIVE|76.8 MHz HFRCO w/ DPLL referenced to|—|27|—|µA/MHz|
|mode with all peripherals||38.4 MHz crystal, CPU running while loop|||||
|disabled||from flash, VSCALE2|||||
|||76.8 MHz HFRCO w/ DPLL referenced to|—|37|—|µA/MHz|
|||38.4 MHz crystal, CPU running CoreMark|||||
|||loop from flash, VSCALE2|||||
|||38.4 MHz crystal, CPU running Prime|—|28|—|µA/MHz|
|||from flash|||||
|||38.4 MHz crystal, CPU running while loop|—|26|—|µA/MHz|
|||from flash|||||
|||38.4 MHz crystal, CPU running CoreMark|—|38|—|µA/MHz|
|||loop from flash|||||
|||38 MHz HFRCO, CPU running while loop|—|22|—|µA/MHz|
|||from flash|||||
|||76.8 MHz HFRCO w/ DPLL referenced to|—|28|—|µA/MHz|
|||38.4 MHz crystal, CPU running Prime|||||
|||from flash, VSCALE2|||||
|Current consumption in EM1|IEM1|76.8 MHz HFRCO w/ DPLL referenced to|—|17|—|µA/MHz|
|mode with all peripherals||38.4 MHz crystal, VSCALE2|||||
|disabled||38.4 MHz crystal|—|17|—|µA/MHz|
|||38 MHz HFRCO|—|13|—|µA/MHz|
|Current consumption in EM2|IEM2_VS|Full RAM retention and RTC running from|—|1.40|—|µA|
|mode, VSCALE0||LFXO|||||
|||Full RAM retention and RTC running from|—|1.40|—|µA|
|||LFRCO|||||
|||Full RAM retention and RTC running from|—|1.75|—|µA|
|||LFRCO in precision mode|||||
|||24 kB RAM retention and RTC running|—|1.32|—|µA|
|||from LFXO|||||
|||24 kB RAM retention and RTC running|—|1.66|—|µA|
|||from LFRCO in precision mode|||||
|||8 kB RAM retention and RTC running|—|1.21|—|µA|
|||from LFXO|||||
|||8 kB RAM retention and RTC running|—|1.20|—|µA|
|||from LFRCO|||||
|Current consumption in EM3|IEM3_VS|8 kB RAM retention and RTC running|—|1.05|—|µA|
|mode, VSCALE0||from ULFRCO|||||
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|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Current consumption in EM4|IEM4|No BURTC, No LF Oscillator, DCDC|—|0.17|—|µA|
|mode||bypassed|||||
|Additional current in EM2 or|IPD0B_VS||—|0.37|—|µA|
|EM3 when any peripheral in|||||||
|PD0B is enabled1|||||||
## **Note:**
1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See for a list of the peripherals in each power domain.
RF current consumption measured with MCU in EM1, HCLK = 38.4 MHz, and all MCU peripherals disabled. Unless otherwise indicated, typical conditions are: VREGVDD = 3.0 V. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C.
_**Table 5: Radio Current Consumption with 3 V Supply**_
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**||**Max**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|System current|IRX_ACTIVE|125 kbit/s, 2GFSK, f = 2.4 GHz,|—|—|4.2|—|—|mA|
|consumption in receive<br>mode, active packet<br>reception||Bluetooth stack running<br>500 kbit/s, 2GFSK, f = 2.4 GHz,<br>Bluetooth stack running|—|—|4.3|—|—|mA|
|||1 Mbit/s, 2GFSK, f = 2.4 GHz,|—|—|4.2|—|—|mA|
|||Bluetooth stack running|||||||
|||2 Mbit/s, 2GFSK, f = 2.4 GHz,|—|—|4.8|—|—|mA|
|||Bluetooth stack running|||||||
|System current|IRX_LISTEN|125 kbit/s, 2GFSK, f = 2.4 GHz,|—|—|4.3|—|—|mA|
|consumption in receive<br>mode, listening for packet||Bluetooth stack running<br>500 kbit/s, 2GFSK, f = 2.4 GHz,|—|—|4.3|—|—|mA|
|||Bluetooth stack running|||||||
|||1 Mbit/s, 2GFSK, f = 2.4 GHz,|—|—|4.2|—|—|mA|
|||Bluetooth stack running|||||||
|||2 Mbit/s, 2GFSK, f = 2.4 GHz,|—|—|4.7|—|—|mA|
|||Bluetooth stack running|||||||
|System current|ITX|f = 2.4 GHz, CW, 0 dBm output|—|—|4.6|—|—|mA|
|consumption in transmit<br>mode||power<br>f = 2.4 GHz, CW, 6 dBm output|—|—|8.8|—|—|mA|
|||power|||||||
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Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V. RF center frequency 2.45 GHz.
_**Table 6: RF Transmitter General Characteristics for the 2.4 GHz Band**_
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|RF tuning frequency range|FRANGE||2400|—|2483.5|MHz|
|Maximum TX power|POUTMAX|6 dBm output power|—|6.0|—|dBm|
|Minimum active TX Power|POUTMIN||—|-27|—|dBm|
|Output power variation vs VREGVDD|POUTVAR_V|6 dBm output power with|—|0.04|—|dB|
|supply voltage variation, frequency =||VREGVDD voltage swept from|||||
|2450 MHz||1.8 V to 3.0 V|||||
|Output power variation vs|POUTVAR_T|6 dBm output power, (-40 to|—|0.2|—|dB|
|temperature, Frequency = 2450 MHz||+105 °C)|||||
|Output power variation vs RF|POUTVAR_F|6 dBm output power|—|0.09|—|dB|
|frequency|||||||
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V. RF center frequency 2.45 GHz.
_**Table 7: RF Receiver General Characteristics for the 2.4 GHz Band**_
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|RF tuning frequency range|FRANGE||2400|—|2483.5|MHz|
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Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V. RF center frequency 2.45 GHz.
_**Table 8: RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate**_
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Max usable receiver|SAT|Signal is reference signal1|—|10|—|dBm|
|input level|||||||
|Sensitivity|SENS|Signal is reference signal, 37 byte payload2|—|-98.6|—|dBm|
|||Signal is reference signal, 255 byte payload1|—|-97.2|—|dBm|
|||With non-ideal signals3 1|—|-96.6|—|dBm|
|Signal to co-channel|C/ICC|(see notes)1 4|—|8.7|—|dB|
|interferer|||||||
|N ± 1 Adjacent channel|C/I1|Interferer is reference signal at +1 MHz offset1 5|—|-6.6|—|dB|
|selectivity||4 6|||||
|||Interferer is reference signal at -1 MHz offset1 5 4|—|-6.5|—|dB|
|||6|||||
|N ± 2 Alternate channel|C/I2|Interferer is reference signal at +2 MHz offset1 5|—|-40.9|—|dB|
|selectivity||4 6|||||
|||Interferer is reference signal at -2 MHz offset1 5 4|—|-39.9|—|dB|
|||6|||||
|N ± 3 Alternate channel|C/I3|Interferer is reference signal at +3 MHz offset1 5|—|-45.9|—|dB|
|selectivity||4 6|||||
|||Interferer is reference signal at -3 MHz offset1 5 4|—|-46.2|—|dB|
|||6|||||
|Selectivity to image|C/IIM|Interferer is reference signal at image frequency|—|-23.5|—|dB|
|frequency||with 1 MHz precision1 6|||||
|Selectivity to image|C/IIM_1|Interferer is reference signal at image frequency|—|-40.9|—|dB|
|frequency ± 1 MHz||+1 MHz with 1|||||
|||MHz precision1 6|||||
|||Interferer is reference signal at image frequency|—|-6.6|—|dB|
|||-1 MHz with 1 MHz precision1 6|||||
|Intermodulation|IM|n = 3 (see note7)|—|-17.1|—|dBm|
|performance|||||||
|**Note:**|||||||
1. 0.017% Bit Error Rate.
2. 0.1% Bit Error Rate.
3. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1
4. Desired signal -67 dBm.
5. Measured frequency is 2401 MHz ≤ Fc ≤ 2481 MHz.
6. With allowed exceptions.
7. As specified in Bluetooth Core specification version 5.1, Vol 6, Part A, Section 4.4
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Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V. RF center frequency 2.45 GHz.
_**Table 9: RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate**_
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Max usable receiver input|SAT|Signal is reference signal1|—|10|—|dBm|
|level|||||||
|Sensitivity|SENS|Signal is reference signal, 37 byte payload2|—|-95.9|—|dBm|
|||Signal is reference signal, 255 byte|—|-94.3|—|dBm|
|||payload1|||||
|||With non-ideal signals3 1|—|-94.0|—|dBm|
|Signal to co-channel|C/ICC|(see notes)1 4|—|8.8|—|dB|
|interferer|||||||
|N ± 1 Adjacent channel|C/I1|Interferer is reference signal at +2 MHz|—|-9.2|—|dB|
|selectivity||offset1 5 4 6|||||
|||Interferer is reference signal at -2 MHz|—|-6.6|—|dB|
|||offset1 5 4 6|||||
|N ± 2 Alternate|C/I2|Interferer is reference signal at +4 MHz|—|-43.3|—|dB|
|channel selectivity||offset1 5 4 6|||||
|||Interferer is reference signal at -4 MHz|—|-44.0|—|dB|
|||offset1 5 4 6|||||
|N ± 3 Alternate channel|C/I3|Interferer is reference signal at +6 MHz|—|-48.6|—|dB|
|selectivity||offset1 5 4 6|||||
|||Interferer is reference signal at -6 MHz|—|-50.7|—|dB|
|||offset1 5 4 6|||||
|Selectivity to image|C/IIM|Interferer is reference signal at image|—|-23.8|—|dB|
|frequency||frequency with 1 MHz precision1 6|||||
|Selectivity to image|C/IIM_1|Interferer is reference signal at image|—|-43.3|—|dB|
|frequency ± 2 MHz||frequency +2 MHz with 1|||||
|||MHzprecision1 6|||||
|||Interferer is reference signal at image|—|-9.2|—|dB|
|||frequency -2 MHz with 1 MHz precision1 6|||||
|Intermodulation|IM|n = 3 (see note7)|—|-18.8|—|dBm|
|performance|||||||
|**Note:**|||||||
1. 0.017% Bit Error Rate.
2. 0.1% Bit Error Rate.
3. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1
4. Desired signal -64 dBm.
5. Measured frequency is 2401 MHz ≤ Fc ≤ 2481 MHz.
6. With allowed exceptions.
7. As specified in Bluetooth Core specification version 5.1, Vol 6, Part A, Section 4.4
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Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V. RF center frequency 2.45 GHz.
_**Table 10: RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate**_
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Max usable receiver input|SAT|Signal is reference signal1|—|10|—|dBm|
|level|||||||
|Sensitivity|SENS|Signal is reference signal, 37 byte payload2|—|-102.3|—|dBm|
|||Signal is reference signal, 255 byte|—|-100.9|—|dBm|
|||payload1|||||
|||With non-ideal signals3 1|—|-99.8|—|dBm|
|Signal to co-channel|C/ICC|(see notes)1 4|—|2.7|—|dB|
|interferer|||||||
|N ± 1 Adjacent channel|C/I1|Interferer is reference signal at +1 MHz|—|-8.0|—|dB|
|selectivity||offset1 5 4 6|||||
|||Interferer is reference signal at -1 MHz|—|-7.9|—|dB|
|||offset1 5 4 6|||||
|N ± 2 Alternate channel|C/I2|Interferer is reference signal at +2 MHz|—|-46.5|—|dB|
|selectivity||offset1 5 4 6|||||
|||Interferer is reference signal at -2 MHz|—|-49.9|—|dB|
|||offset1 5 4 6|||||
|N ± 3 Alternate channel|C/I3|Interferer is reference signal at +3 MHz|—|-48.9|—|dB|
|selectivity||offset1 5 4 6|||||
|||Interferer is reference signal at -3 MHz|—|-53.8|—|dB|
|||offset1 5 4 6|||||
|Selectivity to image|C/IIM|Interferer is reference signal at image|—|-48.3|—|dB|
|frequency||frequency with 1 MHz precision1 6|||||
|Selectivity to image|C/IIM_1|Interferer is reference signal at image|—|-49.9|—|dB|
|frequency ± 1 MHz||frequency +1 MHz with 1 MHz precision1 6|||||
|||Interferer is reference signal at image|—|-46.5|—|dB|
|||frequency -1 MHz with 1 MHz precision1 6|||||
## **Note:**
1. 0.017% Bit Error Rate.
2. 0.1% Bit Error Rate.
3. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1
4. Desired signal -72 dBm.
5. Measured frequency is 2401 MHz ≤ Fc ≤ 2481 MHz.
6. With allowed exceptions.
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## 4.10 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V. RF center frequency 2.45 GHz.
_**Table 11: RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 125 kbps Data Rate**_
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Max usable|SAT|Signal is reference signal1|—|10|—|dBm|
|receiver input level|||||||
|Sensitivity|SENS|Signal is reference signal, 37 byte payload2|—|-106.4|—|dBm|
|||Signal is reference signal, 255 byte|—|-106.0|—|dBm|
|||payload1|||||
|||With non-ideal signals3 1|—|-105.6|—|dBm|
|Signal to co-channel|C/ICC|(see notes)1 4|—|0.9|—|dB|
|interferer|||||||
|N ± 1 Adjacent|C/I1|Interferer is reference signal at +1 MHz|—|-13.6|—|dB|
|channel selectivity||offset1 5 4 6|||||
|||Interferer is reference signal at -1 MHz|—|-13.4|—|dB|
|||offset1 5 4 6|||||
|N ± 2 Alternate|C/I2|Interferer is reference signal at +2 MHz|—|-52.6|—|dB|
|channel selectivity||offset1 5 4 6|||||
|||Interferer is reference signal at -2 MHz|—|-55.8|—|dB|
|||offset1 5 4 6|||||
|N ± 3 Alternate|C/I3|Interferer is reference signal at +3 MHz|—|-53.7|—|dB|
|channel selectivity||offset1 5 4 6|||||
|||Interferer is reference signal at -3 MHz|—|-59.0|—|dB|
|||offset1 5 4 6|||||
|Selectivity to image|C/IIM|Interferer is reference signal at image|—|-52.7|—|dB|
|frequency||frequency with 1 MHz precision1 6|||||
|Selectivity to image|C/IIM_1|Interferer is reference signal at image|—|-53.7|—|dB|
|frequency ± 1 MHz||frequency +1 MHz with 1 MHz precision1 6|||||
|||Interferer is reference signal at image|—|-52.6|—|dB|
|||frequency -1 MHz with 1 MHz precision1 6|||||
## **Note:**
1. 0.017% Bit Error Rate.
2. 0.1% Bit Error Rate.
3. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1
4. Desired signal -79 dBm.
5. Measured frequency is 2401 MHz ≤ Fc ≤ 2481 MHz.
6. With allowed exceptions.
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**Table 12: High-Frequency Crystal**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Crystal frequency|fHFXTAL||—|38.4|—|MHz|
|Initial calibrated accuracy|ACCHFXTAL||-10|+/-5|10|ppm|
|Temperature drift|DRIFTHFXTAL|Across specified temperature range|-20|—|20|ppm|
## 4.12 Low Frequency Crystal Oscillator
_**Table 13: Low Frequency Crystal Oscillator**_
|**_Table 13: Low Frequency Crystal Oscillator_**|**_Table 13: Low Frequency Crystal Oscillator_**||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|Crystal Frequency|FLFXO||—|32.768|—|kHz|
|Supported Crystal equivalent|ESRLFXO|GAIN = 0|—|—|80|kΩ|
|series resistance (ESR)||GAIN = 1 to 3|—|—|100|kΩ|
|Supported range of crystal|CLFXO_CL|GAIN = 0|4|—|6|pF|
|load capacitance1||GAIN = 1|6|—|10|pF|
|||GAIN = 2|10|—|12.5|pF|
|||GAIN = 3(see note2)|12.5|—|18|pF|
|Current consumption|ICL12p5|ESR = 70 kOhm, CL = 12.5|—|357|—|nA|
|||pF, GAIN3= 2, AGC4= 1|||||
|Startup Time|TSTARTUP|ESR = 70 kOhm, CL = 7|—|63|—|ms|
|||pF, GAIN3= 1, AGC4= 1|||||
|On-chip tuning cap step size|SSLFXO||—|0.26|—|pF|
|On-chip tuning capacitor value|CLFXO_MIN|CAPTUNE = 0|—|4|—|pF|
|at minimum setting5|||||||
|On-chip tuning capacitor value|CLFXO_MAX|CAPTUNE = 0x4F|—|24.5|—|pF|
|at maximum setting5|||||||
## **Note:**
1. Total load capacitance seen by the crystal
2. Crystals with a load capacitance of greater than 12 pF require external load capacitors.
3. In LFXO_CAL Register
4. In LFXO_CFG Register
5. The effective load capacitance seen by the crystal will be CLFXO/2. This is because each XTAL pin has a tuning cap and the two caps will be seen in series by the crystal
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_**Table 14: Precision Low Frequency RC Oscillator (LFRCO)**_
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Nominal oscillation|FLFRCO||—|32.768|—|kHz|
|frequency|||||||
|Frequency accuracy|FLFRCO_ACC|Normal mode|-3|—|3|%|
|||Precision mode1, across|-500|—|500|ppm|
|||operating temperature|||||
|||range2|||||
|Startup time|tSTARTUP|Normal mode|—|204|—|µs|
|||Precision mode1|—|11.7|—|ms|
|Current consumption|ILFRCO|Normal mode|—|175|—|nA|
|||Precision mode1, T = stable|—|655|—|nA|
|||at 25 °C3|||||
|**Note:**|||||||
1. The LFRCO operates in high-precision mode when CFG_HIGHPRECEN is set to 1. High-precision mode is not available in EM4.
2. Includes ± 40 ppm frequency tolerance of the HFXO crystal.
3. Includes periodic re-calibration against HFXO crystal oscillator.
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## 4.14 GPIO Pins
Unless otherwise indicated, typical conditions are: IOVDD = 3.0 V.
_**Table 15: GPIO Pins**_
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Leakage|ILEAK_IO|MODEx = DISABLED, IOVDD = 1.71 V|—|1.9|—|nA|
|current||MODEx = DISABLED, IOVDD = 3.0 V|—|2.5|—|nA|
|Input low|VIL|AnyGPIOpin|—|—|0.3*IOVDD|V|
|voltage1||RESETn|—|—|0.3*DVDD|V|
|Input high|VIH|AnyGPIOpin|0.7*IOVDD|—|—|V|
|voltage1||RESETn|0.7*DVDD|—|—|V|
|Hysteresis|VHYS|Any GPIO pin|0.05*IOVDD|—|—|V|
|of input<br>voltage||RESETn|0.05*DVDD|—|—|V|
|Output|VOH|Sourcing 20mA, IOVDD = 3.0 V|0.8*OVDD|—|—|V|
|high<br>voltage||Sourcing 8mA, IOVDD = 1.71 V|0.6*IOVDD|—|—|V|
|Output low|VOL|Sinking 20mA, IOVDD = 3.0 V|—|—|0.2*IOVDD|V|
|voltage||Sinking 8mA, IOVDD = 1.71 V|—|—|0.4*IOVDD|V|
|GPIO rise|TGPIO_RISE|IOVDD = 3.0 V, Cload= 50pF,|—|8.4|—|ns|
|time||SLEWRATE = 4, 10% to 90%|||||
|||IOVDD = 1.71 V, Cload= 50pF,|—|13|—|ns|
|||SLEWRATE = 4, 10% to 90%|||||
|GPIO fall|TGPIO_FALL|IOVDD = 3.0 V, Cload= 50pF,|—|7.1|—|ns|
|time||SLEWRATE = 4, 90% to 10%|||||
|||IOVDD = 1.71 V, Cload= 50pF,|—|11.9|—|ns|
|||SLEWRATE = 4, 90% to 10%|||||
|Pull|RPULL|Any GPIO pin.|35|44|55|kΩ|
|up/down<br>resistance2||Pull-up to IOVDD:<br>MODEn = DISABLE DOUT=1.|||||
|||Pull-down to VSS: MODEn =|||||
|||WIREDORPULLDOWN DOUT = 0.|||||
|||RESETnpin. Pull-upto DVDD|35|44|55|kΩ|
|Maximum|TGF|MODE = INPUT, DOUT = 1|—|27|—|ns|
|filtered|||||||
|glitch width|||||||
## **Note:**
1. GPIO input thresholds are proportional to the IOVDD pin. RESETn input thresholds are proportional to DVDD.
2. GPIO pull-ups connect to IOVDD supply, pull-downs connect to VSS. RESETn pull-up connects to DVDD.
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## 4.15 Microcontroller Peripherals
The MCU peripherals set available in Lyra S modules includes:
- ADC: 12-bit at 1 Msps, 16-bit at 76.9 ksps
- 16-bit and 32-bit Timers/Counters
- 24-bit Low Energy Timer for waveform generation
- 32-bit Real Time Counter
- USART (UART/SPI/SmartCards/IrDA/I2S)
- EUART (UART/IrDA)
- I[2] C peripheral interfaces
- PDM interface
- 12 Channel Peripheral Reflex System
For details on their electrical performance, consult the relevant portions of Section 4 in the SoC datasheet.
To learn which GPIO ports provide access to every peripheral, consult Analog Peripheral Connectivity and Digital Peripheral Connectivity.
## 4.16 Typical Performance Curves
Typical performance curves indicate typical characterized performance under the stated conditions.
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## 4.16.1 Internal Antenna Typical Characteristics
Typical Lyra S radiation patterns for the on-board chip antenna under optimal operating conditions are plotted in the figures that follow. Antenna gain and radiation patterns have a strong dependence on the size and shape of the application PCB the module is mounted on, as well as on the proximity of any mechanical design to the antenna.
Phi 0[o]
Phi 90[o]
Theta 90[o]
_**Figure 5: Lyra S Internal Antenna Typical 2D Antenna Radiation Patterns on 55 mm x 20 mm board**_
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The Lyra S can be controlled over the UART interface as a peripheral to an external host processor. Typical power supply, programming/debug interface, and host interface connections are shown in the figure below.
**Note** : For boot pin, see section 5.3 Boot.
## _**Figure 6: UART NCP Configuration**_
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The Lyra S can be used in a stand-alone SoC configuration without an external host processor. Typical power supply and programming/debug interface connections are shown in the figure below.
_**Figure 7: Stand-Alone SoC Configuration**_
The BOOT pin is used to determine when execution of the bootloader is required. Upon reset, execution of the bootloader begins. The state of the BOOT pin is read immediately upon start-up of the bootloader. If LOW, execution of the bootloader continues, facilitating firmware update via the UART. If the BOOT pin is HIGH, the bootloader will stop execution and pass control to the main application firmware.
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## _**Figure 8: 44-Pin SiP Module Device Pinout**_
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see Alternate Function Table and Digital Peripheral Connectivity.
|**Pin**<br>**Name**|**Pin(s)**|**Description**|||**Pin Name**|**Pin(s)**|**Description**|
|---|---|---|---|---|---|---|---|
|NC|1|Do not connect|||ANT_IN|2|Antenna In|
|RF_2G4|3|2.4 GHz RF input/output|||GND|4|Ground|
|GND|5|Ground|||PB04|6|GPIO|
|PB03|7|GPIO|||PB02|8|GPIO|
|PB01|9|GPIO|||PB00|10|GPIO|
|PA00|11|GPIO|||PA01|12|GPIO|
||||||||Decouple output for on-chip|
|PA02|13|GPIO|||DECOUPLE|14|voltage regulator. This pin is|
||||||||internally decoupled, and|
||||||||should be left disconnected.|
|PA03|15|GPIO|||PA04|16|GPIO|
|PA05|17|GPIO|||PA06|18|GPIO|
|PA07|19|GPIO|||PA08|20|GPIO|
|||Regulated supply voltage. This pin is|||||Module input power supply.|
|||internallyconnected to the SoC|||||Thispin is internallyconnected|
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|**Pin**<br>**Name**|**Pin(s)**|**Description**|||**Pin Name**|**Pin(s)**|**Description**|
|---|---|---|---|---|---|---|---|
|VREG|21|DVDD, RFVDD, and PAVDD supply|||VREGVDD|22|to the SoC AVDD and|
|||lines. It is not intended to power|||||VREGVDD supply lines.|
|||external circuitry.||||||
|IOVDD|23|I/O power supply|||PD03|24|GPIO|
|PD02|25|GPIO|||PD01|26|GPIO|
|PD00|27|GPIO|||PC00|28|GPIO|
|PC01|29|GPIO|||PC02|30|GPIO|
|PC03|31|GPIO|||PC04|32|GPIO|
|PC05|33|GPIO|||PC06|34|GPIO|
|RESETn|35|Reset Pin. The RESETn pin is|||GND|36|Ground|
|||internally pulled up to VREG (DVDD).||||||
|NC|37|Do not connect|||NC|38|Do not connect|
|NC|39|Do not connect|||ANT_OUT|40|Antenna Out|
|GND|41|Ground|||GND|42|Ground|
|GND|43|Ground|||GND|44|Ground|
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A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows what functions are available on each device pin.
|**GPIO**||**Alternate Functions**|
|---|---|---|
|PB03|GPIO.EM4WU4||
|PB01|GPIO.EM4WU3||
|PB00||IADC0.VREFN|
|PA00||IADC0.VREFP|
|PA01|GPIO.SWCLK||
|PA02|GPIO.SWDIO||
|PA03|GPIO.SWV GPIO.TDO||
||GPIO.TRACEDATA0||
|PA04|GPIO.TDI||
||GPIO.TRACECLK||
|PA05|GPIO.EM4WU0||
|PD02|GPIO.EM4WU9||
|PD01||LFXO.LFXTAL_I|
|||LFXO.LF_EXTCLK|
|PD00||LFXO.LFXTAL_O|
|PC00|GPIO.EM4WU6||
||GPIO.THMSW_EN||
|PC05|GPIO.EM4WU7||
Many analog resources are routable and can be connected to numerous GPIO's. The table below indicates which peripherals are available on each GPIO port. When a differential connection is being used Positive inputs are restricted to the EVEN pins and Negative inputs are restricted to the ODD pins. When a single ended connection is being used positive input is available on all pins. See the device Reference Manual for more details on the ABUS and analog peripherals.
|**Peripheral**|**Signal**|**EVEN**|**PA**<br>**ODD**|**PA**<br>**ODD**|**EVEN**|**PB**<br>**ODD**|**PB**<br>**ODD**|**EVEN**|**PC**<br>**ODD**|**PC**<br>**ODD**|**EVEN**|**PD**<br>**ODD**|**PD**<br>**ODD**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|IADC0|ANA_NEG|Yes||Yes|Yes||Yes|Yes||Yes|Yes||Yes|
||ANA_POS|Yes||Yes|Yes||Yes|Yes||Yes|Yes||Yes|
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Many digital resources are routable and can be connected to numerous GPIO's. The table below indicates which peripherals are available on each GPIO port.
_**Table 16: DBUS Routing Table**_
|**Peripheral.Resource**|**PA**|**PB**|**PORT**|**PORT**|**PC**|**PD**|
|---|---|---|---|---|---|---|
|CMU.CLKIN0|||||Available|Available|
|CMU.CLKOUT0|||||Available|Available|
|CMU.CLKOUT1|||||Available|Available|
|CMU.CLKOUT2|Available|Available|||||
|EUART0.CTS|Available|Available|||Available|Available|
|EUART0.RTS|Available|Available|||Available|Available|
|EUART0.RX|Available|Available|||Available|Available|
|EUART0.TX|Available|Available|||Available|Available|
|FRC.DCLK|||||Available|Available|
|FRC.DFRAME|||||Available|Available|
|FRC.DOUT|||||Available|Available|
|I2C0.SCL|Available|Available|||Available|Available|
|I2C0.SDA|Available|Available|||Available|Available|
|I2C1.SCL|||||Available|Available|
|I2C1.SDA|||||Available|Available|
|LETIMER0.OUT0|Available|Available|||||
|LETIMER0.OUT1|Available|Available|||||
|MODEM.ANT0|Available|Available|||Available|Available|
|MODEM.ANT1|Available|Available|||Available|Available|
|MODEM.ANT_ROLL_OVER|||||Available|Available|
|MODEM.ANT_RR0|||||Available|Available|
|MODEM.ANT_RR1|||||Available|Available|
|MODEM.ANT_RR2|||||Available|Available|
|MODEM.ANT_RR3|||||Available|Available|
|MODEM.ANT_RR4|||||Available|Available|
|MODEM.ANT_RR5|||||Available|Available|
|MODEM.ANT_SW_EN|||||Available|Available|
|MODEM.ANT_SW_US|||||Available|Available|
|MODEM.ANT_TRIG|||||Available|Available|
|MODEM.ANT_TRIG_STOP|||||Available|Available|
|MODEM.DCLK|Available|Available|||||
|MODEM.DIN|Available|Available|||||
|MODEM.DOUT|Available|Available|||||
|PDM.CLK|Available|Available|||Available|Available|
|PDM.DAT0|Available|Available|||Available|Available|
|PDM.DAT1|Available|Available|||Available|Available|
|PRS.ASYNCH0|Available|Available|||||
|PRS.ASYNCH1|Available|Available|||||
|PRS.ASYNCH10|||||Available|Available|
|PRS.ASYNCH11|||||Available|Available|
|PRS.ASYNCH2|Available|Available|||||
|PRS.ASYNCH3|Available|Available|||||
|PRS.ASYNCH4|Available|Available|||||
|PRS.ASYNCH5|Available|Available|||||
|PRS.ASYNCH6|||||Available|Available|
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|**Peripheral.Resource**|**PA**|**PB**|**PORT**|**PORT**|**PC**|**PD**|
|---|---|---|---|---|---|---|
|PRS.ASYNCH7|||||Available|Available|
|PRS.ASYNCH8|||||Available|Available|
|PRS.ASYNCH9|||||Available|Available|
|PRS.SYNCH0|Available|Available|||Available|Available|
|PRS.SYNCH1|Available|Available|||Available|Available|
|PRS.SYNCH2|Available|Available|||Available|Available|
|PRS.SYNCH3|Available|Available|||Available|Available|
|TIMER0.CC0|Available|Available|||Available|Available|
|TIMER0.CC1|Available|Available|||Available|Available|
|TIMER0.CC2|Available|Available|||Available|Available|
|TIMER0.CDTI0|Available|Available|||Available|Available|
|TIMER0.CDTI1|Available|Available|||Available|Available|
|TIMER0.CDTI2|Available|Available|||Available|Available|
|TIMER1.CC0|Available|Available|||Available|Available|
|TIMER1.CC1|Available|Available|||Available|Available|
|TIMER1.CC2|Available|Available|||Available|Available|
|TIMER1.CDTI0|Available|Available|||Available|Available|
|TIMER1.CDTI1|Available|Available|||Available|Available|
|TIMER1.CDTI2|Available|Available|||Available|Available|
|TIMER2.CC0|Available|Available|||||
|TIMER2.CC1|Available|Available|||||
|TIMER2.CC2|Available|Available|||||
|TIMER2.CDTI0|Available|Available|||||
|TIMER2.CDTI1|Available|Available|||||
|TIMER2.CDTI2|Available|Available|||||
|TIMER3.CC0|||||Available|Available|
|TIMER3.CC1|||||Available|Available|
|TIMER3.CC2|||||Available|Available|
|TIMER3.CDTI0|||||Available|Available|
|TIMER3.CDTI1|||||Available|Available|
|TIMER3.CDTI2|||||Available|Available|
|TIMER4.CC0|Available|Available|||||
|TIMER4.CC1|Available|Available|||||
|TIMER4.CC2|Available|Available|||||
|TIMER4.CDTI0|Available|Available|||||
|TIMER4.CDTI1|Available|Available|||||
|TIMER4.CDTI2|Available|Available|||||
|USART0.CLK|Available|Available|||Available|Available|
|USART0.CS|Available|Available|||Available|Available|
|USART0.CTS|Available|Available|||Available|Available|
|USART0.RTS|Available|Available|||Available|Available|
|USART0.RX|Available|Available|||Available|Available|
|USART0.TX|Available|Available|||Available|Available|
|USART1.CLK|Available|Available|||||
|USART1.CS|Available|Available|||||
|USART1.CTS|Available|Available|||||
|USART1.RTS|Available|Available|||||
|USART1.RX|Available|Available|||||
|USART1.TX|Available|Available|||||
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## 7.1__Layout and Placement
For optimal performance of the Lyra S the following guidelines are recommended:
- Place the module 1.50 mm from the edge of the copper “keep-in” area at the middle of the long edge of the application PCB, as illustrated in Figure 9.
- Copy the exact antenna design from Figure 9 with the values for coordinates A to L given in Figure 10.
- Make a cutout in all lower layers aligned with the right edge and the bottom edge of the antenna as indicated by the yellow box in Figure 11.
- Connect all ground pads directly to a solid ground plane in the top layer.
- Connect RF_2G4 to ANT_IN through a 0-ohm resistor (for using Lyra S module Internal Antenna. See section 7.6 Lyra S module 50Ohms RF track design for connecting external antenna for connecting Lyra S to an external antenna).
- The 0-ohm gives the ability to test conducted and to evaluate the antenna impedance in the design.
- Place ground vias as close to the ground pads of the Lyra S as possible.
- Place ground vias along the antenna loop right and bottom side.
- Place ground vias along the edges of the application board.
- Do not place plastic or any other dielectric material in contact with the Internal antenna.
- A minimum clearance of 0.5 mm is advised.
- Solder mask, conformal coating and other thin dielectric layers are acceptable directly on top of the antenna region.
_**Figure 9: Recommended Layout for Lyra S**_
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_**Figure 10: Internal Antenna Layout With Coordinates**_
_**Table 17: Antenna Polygon Coordinates, Referenced to Center of Lyra S**_
|**_Table 17: Antenna Polygon Coordinates, Referenced to Center of Lyra S_**|**_Table 17: Antenna Polygon Coordinates, Referenced to Center of Lyra S_**|
|---|---|
|**Point**|**Lyra S**|
|A|(2.87, 2.13)|
|B|(2.54, 2.13)|
|C|(2.54, 3.69)|
|D|(3.36, 4.51)|
|E|(7.75, 4.51)|
|F|(7.75, 4.15)|
|G|(6.84, 4.15)|
|H|(6.21, 3.52)|
|I|(4.26, 3.52)|
|J|(3.97, 3.81)|
|K|(3.10, 3.81)|
|L|(2.87, 3.58)|
|Wloop|4.88|
|Hloop|4.15|
|Note:||
|1. All coordinates and dimensions listed in mm.||
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_**Figure 11: Antenna Clearance in Inner and Bottom Layers**_
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The design of a good RF system relies on thoughtful placement and routing of the RF signals. The following guidelines are recommended:
- Place the Lyra S and antenna close to the center of the longest edge of the application board.
- Do not place any circuitry between the board edge and the antenna.
- Make sure to tie all GND planes in the application board together with as many vias as can be fitted.
- Generally ground planes are recommended in all areas of the application board except in the antenna keep-out area shown in Figure 11.
- Open-ended stubs of copper in the outer layer ground planes must be removed if they are more than 5 mm long to avoid radiation of spurious emissions.
- The width of the GND plane to the sides of the Lyra S will impact the efficiency of the on-board chip antenna.
- For optimal performance, a GND plane width of 55 mm for Lyra S22A is recommended as seen on Figure 12.
- See Internal Antenna Typical Characteristics for reference.
Figure 13 illustrates non-optimal layout examples scenarios that will lead to severely degraded RF performance for the application board.
_**Figure 12: Illustration of Recommended Board Width**_
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_**Figure 13: Non-Optimal Layout Examples**_
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For many applications, the carrier board size is determined by the overall form factor or size of the additional circuitry. The recommended carrier board width 55 mm for the Lyra S is thus not always possible in the end-application. If another form factor is required, the antenna performance of the integrated antenna will be compromised but it may still be sufficiently good for providing the required link quality and range of the end-application. Figure 14 shows the total efficiency of the integrated antenna for different carrier board sizes. As can be seen the best performance is achieved for the carrier board size of 55 mm x 25 mm for the Lyra S, with relatively constant performance for larger boards and rapidly declining performance for smaller boards.
The performance of all the sizes tested will be adequate for more than 15 m line-of-sight range and all of the sizes are thus usable.
**WARNING: Any antenna tuning or change of the loop dimensions will void the modular certification of modules with modular certification. In that case, a Permissive Change to the modular approval is required.**
_**Figure 14: Efficiency of the Integrated Antenna as Function of the Carrier Board Size for Lyra S**_
Placing plastic or any other dielectric material directly in contact with the antenna may cause performance degradation. A clearance of minimum 0.5 mm is recommended to avoid excessive detuning of the antenna. Solder mask, conformal coating, and other thin dielectric layers are acceptable directly on top of the antenna region. Any metallic objects in close proximity to the antenna will prevent the antenna from radiating freely. The minimum recommended distance of metallic and/or conductive objects is 10 mm in any direction from the antenna except in the directions of the application PCB ground planes.
Placing the module in contact with or very close to the human body will negatively impact antenna efficiency and reduce range. Furthermore, additional certification may be required if the module is used in a wearable device.
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Lyra S module can be used with external antennas (certified by Laird Connectivity), and requires a 50 Ohm RF trace (GCPW, that Grounded Coplanar Waveguide) to be designed to run from Lyra S module RF_2G4 (pin3) to a RF antenna connector (IPEX MHF4) on host PCB. The 50 Ohms RF track design and length MUST be copied (as specified in this section). On the RF path, 0R series resistor connects Lyra S module RF_2G4 (pin3) to RF track. Lyra S module GND pin4 and GND pin5 used to support GCPW 50Ohm RF trace.
## **Checklist for SCH**
## **Lyra S External antenna connection**
1. Fit IPEX MHF4 RF connector (20449-001E)
2. Fit 0R resistor (position R937 in below SCH) between Lyra S module pin3 (RF_2G4) and IPEX MHF4 RF connector (20449-001E).
3. Leave Lyra S module pin2 (ANT_IN) open circuited.
## **Lyra S Internal antenna connection**
1. Fit 0R resistor (position R936 in below SCH) between Lyra S module pin3 (RF_2G4) and pin2 (ANT_IN).
2. Do not Fit R937 and J3 (positions in below SCH).
3. Lyra S pin40 (ANT_OUT) internal antenna PCB layout MUST be followed.
_**Figure 15: Lyra S for External antenna connection host PCB 50-Ohm RF trace schematic (0R resistor and RF connector)**_
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**Layer1 (RF Track and RF GND)**
**Layer2 (RF GND)**
_**Figure 16: 50-Ohm RF trace design (Layer1 and Layer2) on DVK-Lyra S development board 453-00091-K1 (or host PCB) for use with Lyra S (453-00091) module**_
## **Checklist for PCB:**
▪ MUST use a 50-Ohm RF trace (GCPW, that is Grounded Coplanar Waveguide) from RF_2G4 pad (pin3) of the Lyra S module (453-00091) to RF antenna connector (IPEX MHF4 Receptable (MPN: 20449-001E)) on host PCB.
▪ To ensure regulatory compliance, MUST follow exactly the following considerations for 50-Ohms RF trace design and test verification:
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||**Thickness**|**Dielectric**||
|---|---|---|---|
||**mil**|**Constant Er**||
|Solder Mask|1.18|3.5|Stack up for<br>50Ohms GCPW<br>RF track.|
|Layer1 Copper 1oz+plating|1.3|||
|Core 0.6mm|59.06|4.2||
|Layer2 Copper 1oz+plating|1.3|||
|Solder Mask|1.18|3.5||
_**Figure 17: Lyra S development board PCB stack-up and 50-Ohms Grounded CPW RF trace design using GND on L1 and L2**_
**Note 1** : The plating (ENIG) above base 1ounce copper is not listed, but plating expected to be ENIG.
- The 50-Ohms RF trace design MUST be Grounded Coplanar Waveguide (GCPW) with
- Layer1 RF track width (W) of 20 mil and
- Layer1 gap (S) to GND of 4.5 mil and where the
- Layer1 to Layer 2 dielectric thickness (H) MUST be 59.06 mil (dielectric constant Er 4.2).
- Further the Layer1 base copper must be 1-ounce base copper (that is 1.3 mil) plus the plating and
- Layer1 MUST be covered by solder mask of 1.18 mil thickness (dielectric constant Er 3.5).
- The 50-Ohms RF trace design MUST follow the PCB stack-up shown in Figure 17. (Layer1 to Layer2 thickness MUST be identical to the Lyra S development board).
- The 50-Ohms RF track should be a controlled-impedance trace e.g., ±10%.
- The 50-Ohms RF trace length MUST be identical (as seen in Figure 16) (167.274mil) to that on the Lyra S development board from Lyra S module RF_2G4 RF pad (pin3) to the RF connector IPEX MHF4 Receptable (MPN: 20449-001E).
- Place GND vias regularly spaced either side of 50-Ohms RF trace to form GCPW (Grounded coplanar waveguide) transmission line as shown in Figure 16 and use Lyra S module GND pin4 and GND pin5.
- Use spectrum analyzer to confirm the radiated (and conducted) signal is within the certification limit.
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Please refer to the Lyra S Regulatory Information Guide for details on using Lyra S module with external antennas in each regulatory region.
The Lyra S has been designed to operate with the below external antennas (with a maximum gain of 2.0 dBi). The required antenna impedance is 50 ohms. See Table 18. External antennas improve radiation efficiency.
_**Table 18: External antennas for the Lyra S**_
|**Manufacturer**|**Model**|**Laird Connectivity**<br>**Part Number**|**Laird Connectivity**<br>**Type**|**Connector**|**Connector**<br>**2400-2500 MHz**|**Peak Gain**<br>**2400-2500 MHz**|**Peak Gain**<br>**2400-2500 MHz**<br>**2400-2480 MHz**|**Peak Gain**<br>**2400-2500 MHz**<br>**2400-2480 MHz**|
|---|---|---|---|---|---|---|---|---|
|Laird<br>Connectivity|NanoBlue|EBL2400A1-<br>10MH4L|PCB Dipole|IPEX<br>MHF4|2 dBi|2 dBi||-|
|Laird<br>Connectivity|FlexPIFA|001-0022|PIFA|IPEX<br>MHF4|-|||2 dBi|
|Mag.Layers|EDA-8709-2G4C1-B27-CY|0600-00057|Dipole|IPEX<br>MHF4|2 dBi|2 dBi||-|
|Laird<br>Connectivity|mFlexPIFA|EFA2400A3S-<br>10MH4L|PIFA|IPEX<br>MHF4|-|||2 dBi|
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The package dimensions are shown in Figure 18
_**Figure 18: Mechanical Dimensions – Full**_
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The recommended PCB Land Pattern is shown in Figure 19.
_**Figure 19: Module Land Pattern**_
## **Notes:**
1. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05mm is assumed.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
4. The stencil thickness should be 0.100 mm (4 mils).
5. The stencil aperture to land pad size recommendation is 80% paste coverage.
_**Above notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use different parameters and fine tune their SMT process as required for their application and tooling.**_
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_**Figure 20: Lyra S Top Marking**_
_**Table 19: Top Marking Definition**_ **Part Number Line 1 Marking Line 2 Marking Line 3 Marking** ~~eeee eee~~ 453-00091 453-00091 Lyra-S See note below **Note:** YY = Year. WW = Work Week, TTTTTTT = Trace Code
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- Optimal solder reflow profile depends on solder paste properties and should be optimized as part of an overall process development.
- It is important to provide a solder reflow profile that matches the solder paste supplier's recommendations.
- Temperature ranges beyond that of the solder paste supplier's recommendation could result in poor solderability.
- ▪ All solder paste suppliers recommend an ideal reflow profile to give the best solderability.
## _**Figure 21: Recommended Reflow Profile**_
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In general, cleaning the populated modules is strongly discouraged. Residuals under the module cannot be easily removed with any cleaning process.
- Cleaning with water can lead to capillary effects where water is absorbed into the gap between the host board and the module. The combination of soldering flux residuals and encapsulated water could lead to short circuits between neighboring pads. Water could also damage any stickers or labels.
- Cleaning with alcohol or a similar organic solvent will likely flood soldering flux residuals into the RF shield, which is not accessible for post-washing inspection. The solvent could also damage any stickers or labels.
- Ultrasonic cleaning could damage the module permanently
## 10.2 Rework
The Lyra S module can be unsoldered from the host board if the Moisture Sensitivity Level (MSL) requirements are met as described in this datasheet.
Never attempt a rework on the module itself, e.g. replacing individual components. Such actions terminate warranty coverage.
## 10.3 Handling and Storage
## 10.3.1 Handling
The Lyra S modules contain a highly sensitive electronic circuitry. Handling without proper ESD protection may damage the module permanently
## 10.5.2Moisture Sensitivity Level (MSL)
Per J-STD-020, devices rated as MSL 4 and not stored in a sealed bag with desiccant pack should be baked prior to use.
Devices are packaged in a Moisture Barrier Bag with a desiccant pack and Humidity Indicator Card (HIC). Devices that will be subjected to reflow should reference the HIC and J-STD-033 to determine if baking is required.
If baking is required, refer to J-STD-033 for bake procedure.
## 10.3.5Storage
Per J-STD-033, the shelf life of devices in a Moisture Barrier Bag is 12 months at <40C and <90% room humidity (RH).
Do not store in salty air or in an environment with a high concentration of corrosive gas, such as Cl2, H2S, NH3, SO2, or NOX. Do not store in direct sunlight.
The product should not be subject to excessive mechanical shock.
## 10.3.4Repeated Reflow Soldering
Only a single reflow soldering process is encouraged for host boards.
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Lyra S modules are delivered to the customer in Cut Tape (600 pcs) or reel (2500 pcs / reel) packaging with the dimensions below. All dimensions are given in mm unless otherwise indicated.
_**Figure 22: Carrier Tape Dimensions**_
_**Figure 23: Reel Dimensions**_
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**Note:** For complete regulatory information, refer to the Lyra S Regulatory Information document which is also available from the Lyra Series product page.
The Lyra S holds current certifications in the following countries:
|**Country/Region**|**Regulatory ID**|
|---|---|
|USA (FCC)|SQG-LyraS|
|Canada (ISED)|3147A-LyraS|
|UK (UKCA)|N/A|
|EU|N/A|
|Japan (MIC)|209-J00457|
|Korea (KC)|R-C-L7C-LyraS|
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The Lyra S Series module is listed on the Bluetooth SIG website as a qualified End Product, using the combination of a RFPHY, LL and Host Stack Components.
|**Design**<br>**Name**|**Owner**|**Declaration**<br>**ID**|**Reference**<br>**QDID**|**Link to listing on the SIG website**|
|---|---|---|---|---|
|Lyra S|Laird<br>Connectivity|D057227|178495<br>178212<br>175341|https://launchstudio.bluetooth.com/ListingDetails/147725|
|**Design Name**|**Owner**|**Reference**<br>**QDID**|**Link to listing on the SIG website**|
|---|---|---|---|
|BGM220S<br>RF-PHY|Silicon Laboratories|178495|https://launchstudio.bluetooth.com/ListingDetails/141475|
|Wireless Gecko<br>Link Layer|Silicon Laboratories|178212|https://launchstudio.bluetooth.com/ListingDetails/141145|
|Wireless Gecko<br>Host|Silicon Laboratories|175341|https://launchstudio.bluetooth.com/ListingDetails/137791|
It is a mandatory requirement of the Bluetooth Special Interest Group (SIG) that every product implementing Bluetooth technology has a Declaration ID. Every Bluetooth design is required to go through the qualification process, even when referencing a Bluetooth Design that already has its own Declaration ID. The Qualification Process requires each company to registered as a member of the Bluetooth SIG – https://www.bluetooth.com/
The following link provides a link to the Bluetooth Registration page: https://www.bluetooth.org/login/register/
For each Bluetooth Design, it is necessary to purchase a Declaration ID. This can be done before starting the new qualification, either through invoicing or credit card payment. The fees for the Declaration ID will depend on your membership status, please refer to the following webpage:
https://www.bluetooth.com/develop-with-bluetooth/qualification-listing/qualification-listing-fees/
For a detailed procedure of how to obtain a new Declaration ID for your design, please refer to the following SIG document:
https://www.bluetooth.org/DocMan/handlers/DownloadDoc.ashx?doc_id=283698&vId=317486
For this qualification, follow these steps:
1. To start a listing, go to: https://www.bluetooth.org/tpg/QLI_SDoc.cfm
2. Select Start the Bluetooth Qualification Process with **No Required Testing** .
3. Project Basics:
- Enter the Project Name (this can be the product name or the Bluetooth Design name).
- For Referenced Qualified Designs, enter QDID 182889.
4. Product Declaration:
- Enter the Listing Date (this can any date ranging from the date of entry up to 90 days after submission) – Your design is qualified immediately but the listing does not go public until the specified date.
5. Add End Product(s) – Each end product that uses the Qualified Design (without modification) can be added in this section. The Bluetooth SIG requires that you add each individual model number separately.
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6. Declaration ID:
- Select a Declaration ID from the list.
**Important!** To complete this step, you must have already paid your Bluetooth SIG Declaration ID fee. If you have not, refer to the Bluetooth SIG Qualification Overview section for instructions. You also have the option of clicking **Pay Declaration Fee** accessible from this step of the Bluetooth SIG Qualification process.
7. Review and Submit – With this, some automatic checks occur to ensure all sections are complete. ▪ Review all entered information and make corrections, if needed.
- Once you have reviewed your information, tick all of the check boxes and add your name to the signature page.
- Click **Signature Confirmed – Complete Project & Submit Product(s) for Qualification** . (You will be asked to confirm to proceed with the final listing one more time)
8. Once the listing is confirmed please download the SDoC and place a copy in the compliance folder.
For further information, please refer to the following webpage: https://www.bluetooth.com/develop-with-bluetooth/qualification-listing/
https://www.lairdconnect.com/
**Americas** : +1-800-492-2320 **Europe** : +44-1628-858-940 **Hong Kong** : +852-2762-4823
50 © Copyright 2022 Laird Connectivity All Rights Reserved
Please contact your local sales representative or our support team for further assistance:
Laird Connectivity Support Centre: https://www.lairdconnect.com/resources/support Email: wireless.support@lairdconnectivity.com Phone: Americas: +1-800-492-2320 Europe: +44-1628-858-940 Hong Kong: +852-2762-4823 Web: https://www.lairdconnect.com/products
**Note:** Information contained in this document is subject to change.
© Copyright 2022 Laird Connectivity. All Rights Reserved. Patent pending. Any information furnished by Laird Connectivity and its agents is believed to be accurate and reliable. All specifications are subject to change without notice. Responsibility for the use and application of Laird Connectivity materials or products rests with the end user since Laird Connectivity and its agents cannot be aware of all potential uses. Laird Connectivity makes no warranties as to non-infringement nor as to the fitness, merchantability, or sustainability of any Laird Connectivity materials or products for any specific or general uses. Laird Connectivity or any of its affiliates or agents shall not be liable for incidental or consequential damages of any kind. All Laird Connectivity products are sold pursuant to the Laird Connectivity Terms and Conditions of Sale in effect from time to time, a copy of which will be furnished upon request. Nothing herein provides a license under any Laird Connectivity or any third-party intellectual property right.
https://www.lairdconnect.com/
**Americas** : +1-800-492-2320 **Europe** : +44-1628-858-940 **Hong Kong** : +852-2762-4823
51 © Copyright 2022 Laird Connectivity All Rights Reserved
Updated at June 5, 2026
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