2N7002K

## Field Effect Transistor - N-Channel, Enhancement Mode 

## 2N7002K 

## **Features** 

## **www.onsemi.com** 

- Low On−Resistance 

- Low Gate Threshold Voltage 

- Low Input Capacitance 

- Fast Switching Speed 

- Low Input / Output Leakage 

**SOT−23 (TO−236) CASE 318−08** 

- Ultra−Small Surface Mount Package 

- ESD HBM = 2000 V (Typical: 3000 V) as per JESD22 A114 and ESD CDM = 2000 V as per JESD22 C101 

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|||||||||
|---|---|---|---|---|---|---|---|
|ESD CDM = 2000 V as per JESD22 C101|MARKING DIAGRAM|
|•|This Device is Pb−Free, Halogen Free/BFR Free and is RoHS|
|Compliant|
|7K M|
|ABSOLUTE MAXIMUM RATINGS|(TA = 25|°|C unless otherwise specified)|
|1|
|Symbol|Parameter|Value|Unit|
|7K|= Specific Device Code|
|VDSS|Drain−Source Voltage|60|V|M|= Date Code|
|——|iv|
|VDGR|Drain−Gate Voltage (RGS|≤|1.0 M|)|60|V|
|VGSS|Gate−Source Voltage|±|20|V|FUNCTIONAL SCHEMATIC|
|ID|Drain Current|Continuous|300|mA|
|Pulsed|800|D|
|TJ|Operating Junction Temperature Range|−55 to +150|°|C|
|TSTG|Storage Temperature Range|−55 to +150|°|C|
|Stresses exceeding those listed in the Maximum Ratings table may damage the|
|device. If any of these limits are exceeded, device functionality should not be|
|assumed, damage may occur and reliability may be affected.|
|THERMAL CHARACTERISTICS|(TA = 25|°|C unless otherwise specified)|G|S|
|—————|a.|
|Symbol|Parameter|Value|Unit|
|a|
|PD|Total Device Dissipation|350|mW|
|ORDERING INFORMATION|
|Derate Above TA = 25|°|C|2.8|mW/|°|C|See detailed ordering and shipping information on page 4 of|
|R|JA|Thermal Resistance, Junction−to−Ambient|350|°|C/W|this data sheet.|
|(Note 1)|
|a|eeeee|ee|
|1.|Device mounted on FR−4 PCB, 1 inch x 0.85 inch x 0.062 inch;Minimum land|
|pad size|.|

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Publication Order Number: **2N7002K−FSC/D** 

**1** 

© Semiconductor Components Industries, LLC, 2020 **October, 2020 − Rev. 2** 

**2N7002K** 

**ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**ELECTRIC**|**AL CHARACTERISTICS**(TJ= 25°C unless|otherwise noted)||||
|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**(Note 2)||||||
|BVDSS|Drain−Source Breakdown Voltage|VGS= 0 V, ID= 10�A|60|−|V|
|IDSS|Zero Gate Voltage Drain Current|VDS= 60 V, VGS= 0 V|−|1.0|�A|
|||VDS= 60 V, VGS= 0 V, TJ= 125°C|−|500||
|IGSS|Gate−Body Leakage|VGS=±20 V, VDS= 0 V|−|±10|�A|
|**ON CHARACTERISTICS**(Note 2)||||||
|VGS(th)|Gate Threshold Voltage|VDS= VGS, ID= 250�A|1.0|2.5|V|
|RDS(ON)|Static Drain−Source On−Resistance|VGS= 10 V, ID= 0.5 A|−|2|�|
|||VGS= 4.5 V, ID= 200 mA|−|4||
|ID(ON)|On−State Drain Current|VGS= 10 V, VDS= 7.5 V|1.5|−|A|
|gFS|Forward Transconductance|VDS= 10 V, ID= 0.2 A|200|−|mS|
|**DYNAMIC CHARACTERISTICS**||||||
|Ciss|Input Capacitance|VDS= 25 V, VGS= 0 V, f = 1.0 MHz|−|50|pF|
|Coss|Output Capacitance||−|15|pF|
|Crss|Reverse Transfer Capacitance||−|6|pF|
|**SWITCHING CHARACTERISTICS**||||||
|tD(ON)|Turn−On Delay Time|VDD= 30 V, IDSS= 200 mA, RG= 10�,<br>VGS= 10 V|−|5|ns|
|tD(OFF)|Turn−Off Delay Time||−|30|ns|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Short duration test pulse used to minimize self−heating effect. 

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**2** 

**2N7002K** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

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2.0 3.0<br>VGS = 10 V VGS = 3 V<br>4 V<br>5 V 2.5<br>1.5 4.5 V<br>5 V<br>4 V 2.0 6 V<br>7 V<br>1.0<br>1.5<br>3 V<br>0.5<br>1.0<br>8 V 9 V 10 V<br>2 V<br>0.0 0.5<br>0 2 4 6 8 10 0.0 0.2 0.4 0.6 0.8 1.0<br>VDS, DRAIN−SOURCE VOLTAGE (V) ID, DRAIN−SOURCE CURRENT (A)<br>) �<br>, DRAIN−SOURCE<br>DS(on) ON−RESISTANCE (<br>R<br>, DRAIN−SOURCE CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 1. On−Region Characteristics** 

**Figure 2. On−Resistance Variation with Gate Voltage and Drain Current** 

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3.0 2.0<br>VDS = 10 V<br>ID = 500 mA<br>2.5<br>1.5<br>2.0<br>1.0<br>1.5<br>ID = 500 mA<br>0.5<br>1.0 ID = 50 mA<br>0.5 0.0<br>−50 0 50 100 150 2 3 4 5 6 7 8 9 10<br>TJ, JUNCTION TEMPERATURE ( ° C) VGS, GATE−SOURCE VOLTAGE (V)<br>Figure 3. On−Resistance Variation with Figure 4. On−Resistance Variation with<br>Temperature Gate−Source Voltage<br>1.0 2.0<br>VDS = 10 V 25 ° C VDS = VGS<br>0.8 1.8<br>TJ = −25 ° C 150 ° C ID = 1 mA<br>0.6 1.6<br>125 ° C ID = 0.25 mA<br>0.4 1.4<br>75 ° C<br>0.2 1.2<br>0.0 1.0<br>2 3 4 5 6 −50 0 50 100 150<br>VGS, GATE−SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE ( ° C)<br>) � ) �<br>, DRAIN−SOURCE (on), DRAIN−SOURCE<br>DS(on) ON−RESISTANCE ( DS ON−RESISTANCE (<br>R R<br>VOLTAGE (V)<br>, DRAIN−SOURCE CURRENT (A)<br>ID Vth, GATE−SOURCE THRESHOLD<br>**----- End of picture text -----**<br>


**Figure 5. Transfer Characteristics** 

**Figure 6. Gate Threshold Variation with Temperature** 

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**3** 

**2N7002K** 

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VDS = 10 V<br>100<br>TA = 150 ° C<br>25 ° C<br>10<br>−55 ° C<br>1<br>0.0 0.2 0.4 0.6 0.8 1.0<br>VDS, DRAIN−SOURCE VOLTAGE (V)<br>, REVERSE DRAIN CURRENT (mA)<br>IS<br>**----- End of picture text -----**<br>


**Figure 7. Reverse Drain Current Variation with Diode Forward Voltage and Temperature** 

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10<br>8<br>6<br>500 mA<br>280 mA<br>4<br>2<br>115 mA<br>0<br>0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1<br>Qg, GATE CHARGE<br>, GATE−SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 8. Gate Charge Characteristics** 

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1<br>0.5 100  � s<br>RDS(ON) LIMIT<br>1 ms<br>0.05<br>SINGLE PULSE 10ms<br>R � JA = 350 ° C/W<br>TA = 25 ° C 100 ms<br>1 s<br>10 s<br>DC<br>0.005<br>0.01 0.1 1 10 100 200<br>VDS, DRAIN−SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 9. Maximum Safe Operating Area** 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**||||
|---|---|---|---|
|**Part Number**|**Top Mark**|**Package**|**Shipping**†|
|2N7002K|7K|SOT−23 3L<br>(Pb−Free)|3000 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

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**4** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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SOT−23 (TO−236)<br>CASE 318−08<br>ISSUE AS<br>2 DATE 30 JAN 2018<br>SCALE 4:1<br>D NOTES:<br>1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.<br>0.25 MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF<br>“a 3 t = THE BASE MATERIAL.<br>| E HE T 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,PROTRUSIONS, OR GATE BURRS.<br>1 2<br>MILLIMETERS INCHES<br>DIM MIN NOM MAX MIN NOM MAX<br>L A 0.89 1.00 1.11 0.035 0.039 0.044<br>3X b L1 A1b 0.010.37 0.060.44 0.100.50 0.0000.015 0.0020.017 0.0040.020<br>e VIEW C c 0.08 0.14 0.20 0.003 0.006 0.008<br>TOP VIEW D 2.80 2.90 3.04 0.110 0.114 0.120<br>E 1.20 1.30 1.40 0.047 0.051 0.055<br>e 1.78 1.90 2.04 0.070 0.075 0.080<br>L 0.30 0.43 0.55 0.012 0.017 0.022<br>A L1 0.35 0.54 0.69 0.014 0.021 0.027<br>H E 2.10 2.40 2.64 0.083 0.094 0.104<br>= T 0 ° −−− 10 ° 0 ° −−− 10 °<br>a A1 SIDE VIEW SEE VIEW C c<br>GENERIC<br>END VIEW<br>MARKING DIAGRAM*<br>RECOMMENDED<br>SOLDERING FOOTPRINT XXXM<br>1<br>2.90 i 0.903X XXX = Specific Device Code oo<br>M = Date Code<br>= Pb−Free Package<br>LO | cr ,<br>*This information is generic. Please refer to<br>3X 0.80 a) LL 0.95 device data sheet for actual part marking.<br>PITCH Pb−Free indicator, “G” or microdot “ ”, |<br>DIMENSIONS: MILLIMETERS may or may not be present.<br>STYLE 1 THRU 5: STYLE 6: STYLE 7: STYLE 8:<br>CANCELLED PIN 1. BASE PIN 1. EMITTER PIN 1. ANODE<br>2. EMITTER 2. BASE 2. NO CONNECTION<br>3. COLLECTOR 3. COLLECTOR 3. CATHODE<br>STYLE 9: STYLE 10: STYLE 11: STYLE 12: STYLE 13: STYLE 14:<br>PIN 1. ANODE PIN 1. DRAIN PIN 1. ANODE PIN 1. CATHODE PIN 1. SOURCE PIN 1. CATHODE<br>2. ANODE 2. SOURCE 2. CATHODE 2. CATHODE 2. DRAIN 2. GATE<br>3. CATHODE 3. GATE 3. CATHODE−ANODE 3. ANODE 3. GATE 3. ANODE<br>STYLE 15: STYLE 16: STYLE 17: STYLE 18: STYLE 19: STYLE 20:<br>PIN 1. GATE PIN 1. ANODE PIN 1. NO CONNECTION PIN 1. NO CONNECTION PIN 1. CATHODE PIN 1. CATHODE<br>2. CATHODE 2. CATHODE 2. ANODE 2. CATHODE 2. ANODE 2. ANODE<br>3. ANODE 3. CATHODE 3. CATHODE 3. ANODE 3. CATHODE−ANODE 3. GATE<br>STYLE 21: STYLE 22: STYLE 23: STYLE 24: STYLE 25: STYLE 26:<br>PIN 1. GATE PIN 1. RETURN PIN 1. ANODE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE<br>2. SOURCE 2. OUTPUT 2. ANODE  2. DRAIN  2. CATHODE  2. ANODE<br>3. DRAIN 3. INPUT 3. CATHODE  3. SOURCE  3. GATE  3. NO CONNECTION<br>STYLE 27: STYLE 28:<br>PIN 1. CATHODE PIN 1. ANODE<br> 2. CATHODE  2. ANODE<br> 3. CATHODE  3. ANODE<br>Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>DOCUMENT NUMBER: 98ASB42226B Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.<br>DESCRIPTION: SOT−23 (TO−236) PAGE 1 OF 1<br>aes<br>ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.<br>ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding<br>the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically<br>disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the<br>rights of others.<br>**----- End of picture text -----**<br>


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© Semiconductor Components Industries, LLC, 2019 

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