2N5192G

## 2N5190G, 2N5191G, 2N5192G 

## Silicon NPN Power Transistors 

Silicon NPN power transistors are for use in power amplifier and switching circuits − excellent safe area limits. Complement to PNP 2N5194, 2N5195. 

## **http://onsemi.com** 

|switching circuits − excellent safe area limits. Complement to PNP<br>2N5194, 2N5195.|switching circuits − excellent safe area limits. Complement to PNP||**http://onsemi.com**||
|---|---|---|---|---|
||||**4.0 AMPERES**||
|**Features**|||**NPN SILICON**||
|• Epoxy Meets UL 94 V−0 @ 0.125 in.|||**POWER TRANSISTORS**||
|• These Devices are Pb−Free and are RoHS Compliant*|||**40, 60, 80 VOLTS − 40 WATTS**|**40, 60, 80 VOLTS − 40 WATTS**|
|**MAXIMUM RATINGS**|||COLLECTOR||
|**Rating**<br>**Symbol**<br>**Value**<br>**Unit**<br>Collector−Emitter Voltage<br>2N5190G<br>2N5191G<br>2N5192G<br>VCEO<br>40<br>60<br>80<br>Vdc<br>Collector−Base Voltage<br>2N5190G<br>2N5191G<br>2N5192G<br>VCBO<br>40<br>60<br>80<br>Vdc<br>Emitter−Base Voltage<br>VEBO<br>5.0<br>Vdc<br>Collector Current<br>IC<br>4.0<br>Adc<br>Base Current<br>IB<br>1.0<br>Adc<br>Total Device Dissipation<br>@ TC= 25°C<br>Derate above 25°C<br>PD<br>40<br>320<br>W<br>mW/°C<br>Operating and Storage Junction<br>Temperature Range<br>TJ, Tstg<br>–65 to +150<br>°C<br>ESD − Human Body Model<br>HBM<br>3B<br>V<br>ESD − Machine Model<br>MM<br>C<br>V<br>Stresses exceeding those listed in the Maximum Ratings table may damage the<br>device. If any of these limits are exceeded, device functionality should not be<br>assumed, damage may occur and reliability may be affected.<br>**MARKING DIAGRAM**<br>3<br>BASE<br>1<br>EMITTER<br>2, 4<br>**TO−225**<br>**CASE 77−09**<br>**STYLE 1**<br>1 2 3<br>YWW<br>2<br>N519xG<br>~~&)~~<br>~~ue~~|||||



## **THERMAL CHARACTERISTICS** 

Y = Year WW = Work Week 2N519x = Device Code x = 0, 1, or 2 G = Pb−Free Package 

|**THERMAL CHARACTERISTICS**||||Y||= Year|
|---|---|---|---|---|---|---|
|**Characteristic**|**Symbol**|**Max**|**Unit**|WW||= Work Week|
|Thermal Resistance, Junction−to−Case|R JC|3.12|°C/W|2N519x||= Device Code<br>x = 0, 1, or 2|
|||||G||= Pb−Free Package|
|||||**ORDERING INFORMATION**|||
|*For additional information on our Pb−Free strategy  and soldering details, please<br>download the ON Semiconductor Soldering and Mounting Techniques||*For additional information on our Pb−Free strategy  and soldering details, please<br>download the ON Semiconductor Soldering and Mounting Techniques||**Device**<br>**Package**<br>**Shipping**<br>2N5191G<br>TO−225<br>(Pb−Free)<br>500 Units/Box<br>2N5192G<br>TO−225<br>(Pb−Free)<br>500 Units/Box<br>2N5190G<br>TO−225<br>(Pb−Free)<br>500 Units/Box<br>~~===~~|||
|Reference Manual, SOLDERRM/D.|||||||
|©Semiconductor Components Industries, LLC, 2013|||**1**|||Publication Order Number:|



- *For additional information on our Pb−Free strategy  and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

© Semiconductor Components Industries, LLC, 2013 **December, 2013 − Rev. 15** 

**2N5191/D** 

## **2N5190G, 2N5191G, 2N5192G** 

## **ELECTRICAL CHARACTERISTICS*** (TC = 25 � C unless otherwise noted) 

|**ELECTRICAL CHARACTERISTICS***(TC= 25�C unless otherwis|e noted)||||
|---|---|---|---|---|
|**Characteristic**|**Symbol**|**Min**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**|||||
|Collector−Emitter Sustaining Voltage (Note 1)<br>(IC= 0.1 Adc, IB= 0)<br>2N5190G<br>2N5191G<br>2N5192G|VCEO(sus)|40<br>60<br>80|−<br>−<br>−|Vdc|
|Collector Cutoff Current<br>(VCE= 40 Vdc, IB= 0)<br>2N5190G<br>(VCE= 60 Vdc, IB= 0)<br>2N5191G<br>(VCE= 80 Vdc, IB= 0)<br>2N5192G|ICEO|−<br>−<br>−|1.0<br>1.0<br>1.0|mAdc|
|Collector Cutoff Current<br>(VCE= 40 Vdc, VEB(off)= 1.5 Vdc)<br>2N5190G<br>(VCE= 60 Vdc, VEB(off)= 1.5 Vdc)<br>2N5191G<br>(VCE= 80 Vdc, VEB(off)= 1.5 Vdc)<br>2N5192G<br>(VCE= 40 Vdc, VEB(off)= 1.5 Vdc, TC= 125�C)<br>2N5190G<br>(VCE= 60 Vdc, VEB(off)= 1.5 Vdc, TC= 125�C)<br>2N5191G<br>(VCE= 80 Vdc, VEB(off)= 1.5 Vdc, TC= 125�C)<br>2N5192G|ICEX|−<br>−<br>−<br>−<br>−<br>−|0.1<br>0.1<br>0.1<br>2.0<br>2.0<br>2.0|mAdc|
|Collector Cutoff Current<br>(VCB= 40 Vdc, IE= 0)<br>2N5190G<br>(VCB= 60 Vdc, IE= 0)<br>2N5191G<br>(VCB= 80 Vdc, IE= 0)<br>2N5192G|ICBO|−<br>−<br>−|0.1<br>0.1<br>0.1|mAdc|
|Emitter Cutoff Current<br>(VBE= 5.0 Vdc, IC= 0)|IEBO|−|1.0|mAdc|
|**ON CHARACTERISTICS**(Note 1)|||||
|DC Current Gain<br>(IC= 1.5 Adc, VCE= 2.0 Vdc)<br>2N5190G/2N5191G<br>2N5192G<br>(IC= 4.0 Adc, VCE= 2.0 Vdc)<br>2N5190G/2N5191G<br>2N5192G|hFE|25<br>20<br>10<br>7.0|100<br>80<br>−<br>−|−|
|Collector−Emitter Saturation Voltage<br>(IC= 1.5 Adc, IB= 0.15 Adc)<br>(IC= 4.0 Adc, IB= 1.0 Adc)|VCE(sat)|**−**<br>**−**|0.6<br>1.4|Vdc|
|Base−Emitter On Voltage<br>(IC= 1.5 Adc, VCE= 2.0 Vdc)|VBE(on)|−|1.2|Vdc|
|**DYNAMIC CHARACTERISTICS**|||||
|Current−Gain − Bandwidth Product<br>(IC= 1.0 Adc, VCE= 10 Vdc, f = 1.0 MHz)|fT|2.0|−|MHz|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. *JEDEC Registered Data. 

1. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2.0%. 

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**2N5190G, 2N5191G, 2N5192G** 

**==> picture [490 x 594] intentionally omitted <==**

**----- Start of picture text -----**<br>
10<br>7.0 TJ = 150°C V CE = 2.0 V<br>5.0 V CE  = 10 V<br>3.0<br>2.0<br>1.0<br>0.7 25°C -�55°C<br>0.5<br>0.3<br>0.2<br>0.1<br>0.004 0.007 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 4.0<br>IC, COLLECTOR CURRENT (AMP)<br>Figure 1. DC Current Gain<br>2.0<br>T J  = 25°C<br>1.6<br>1.2 I C  = 10 mA 100 mA 1.0 A 3.0 A<br>0.8<br>0.4<br>0<br>0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 200 300 500<br>IB, BASE CURRENT (mA)<br>Figure 2. Collector Saturation Region<br>2.0 +�2.5<br>TJ = 25°C +�2.0 *APPLIES FOR IC/IB ≤ hFE�@�VCE� ��2.0�V<br>2<br>1.6 +�1.5 TJ = -�65°C to +150°C<br>+�1.0<br>1.2 +�0.5 *�V for VCE(sat)<br>0<br>0.8 -�0.5<br>VBE(sat) @ IC/IB = 10<br>VBE @ VCE = 2.0 V -�1.0<br>0.4 -�1.5 �V for VBE<br>VCE(sat) @ IC/IB = 10 -�2.0<br>0 -�2.5<br>0.005 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 4.0 0.005 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 4.0<br>IC, COLLECTOR CURRENT (AMP) IC, COLLECTOR CURRENT (AMP)<br>hFE, DC CURRENT GAIN (NORMALIZED)<br>VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)<br>C)°<br>V, TEMPERATURE COEFFICIENTS (mV/<br>θ<br>**----- End of picture text -----**<br>


**Figure 3. “On” Voltages** 

**Figure 4. Temperature Coefficients** 

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**3** 

**2N5190G, 2N5191G, 2N5192G** 

**==> picture [489 x 607] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 [[3]] 10 [7]<br>VCE = 30 VCE = 30 V = 30 V IC = 10 x ICES VCE = 30 V<br>10 [[2]]<br>10 [6]<br>TJ = 150°CJ = 150°C = 150°C°CC<br>10 [[1]] IC ≈ ICES<br>10 [5]<br>10 [[0]] 100°C°CC IC = 2 x ICES<br>10 [4]<br>REVERSE FORWARD<br>10 [[-1]]<br>10 [[-�2]] 25°C°CC 10 [3] (TYPICAL ICES VALUES<br>OBTAINED FROM FIGURE 5)<br>ICESCES<br>10 [[-�3]] 10 [2]<br>-�0.4 -�0.3 -�0.2 -�0.1 0 +�0.1 +�0.2 +�0.3 +�0.4 +�0.5 +�0.6 20 40 60 80 100 120 140 160<br>VBE, BASE-EMITTER VOLTAGE (VOLTS)BE, BASE-EMITTER VOLTAGE (VOLTS), BASE-EMITTER VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)<br>Figure 5. Collector Cut−Off Region Figure 6. Effects of Base−Emitter Resistance<br>300<br>TURN-ON PULSE VCC RC TJ = +�25°C<br>APPROX<br>200<br>+11 V Vin SCOPE<br>RB<br>Vin 0 Cjd�<<�Ceb<br>VEB(off) t1 -�4.0 V 100<br>t3 Ceb<br>APPROX+11 V t1 ≤ 7.0 ns Rto obtain desiredB and RC varied 70<br>100 < t2 < 500 �s current levels<br>Vin t3 < 15 ns 50 Ccb<br>t2 DUTY CYCLE ≈ 2.0% 30<br>APPROX -�9.0 V 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 40<br>TURN-OFF PULSE<br>VR, REVERSE VOLTAGE (VOLTS)<br>Figure 7. Switching Time Equivalent Test Circuit<br>Figure 8. Capacitance<br>2.0 2.0<br>IC/IB = 10 ts′<br>1.0 TJ = 25°C 1.0<br>0.7 tr @ VCC = 30 V 0.7 tf @ VCC = 30 V<br>0.5 0.5<br>0.3 tr @ VCC = 10 V 0.3 tf @ VCC = 10 V<br>0.2 0.2<br>0.1 0.1 IB1 = IB2<br>0.070.05 td @ VEB(off) = 2.0 V 0.070.05 tITCsJ′/I = t = 25B = 10s - 1/8 t°C f<br>0.03 0.03<br>0.02 0.02<br>0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 4.0 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 4.0<br>IC, COLLECTOR CURRENT (AMP) IC, COLLECTOR CURRENT (AMP)<br>RBE, EXTERNAL BASE-EMITTER RESISTANCE (OHMS)<br>CAPACITANCE (pF)<br>μ<br>t, TIME (��s)<br>**----- End of picture text -----**<br>


**==> picture [230 x 174] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 [[3]]<br>VCE = 30 VCE = 30 V = 30 V<br>10 [[2]]<br>TJ = 150°CJ = 150°C = 150°C°CC<br>10 [[1]]<br>10 [[0]] 100°C°CC<br>REVERSE FORWARD<br>10 [[-1]]<br>10 [[-�2]]<br>25°C°CC<br>ICESCES<br>10 [[-�3]]<br>-�0.4 -�0.3 -�0.2 -�0.1 0 +�0.1 +�0.2 +�0.3 +�0.4 +�0.5 +�0.6<br>VBE, BASE-EMITTER VOLTAGE (VOLTS)BE, BASE-EMITTER VOLTAGE (VOLTS), BASE-EMITTER VOLTAGE (VOLTS)<br>**----- End of picture text -----**<br>


**Figure 9. Turn−On Time** 

**Figure 10. Turn−Off Time** 

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**4** 

**2N5190G, 2N5191G, 2N5192G** 

**==> picture [491 x 384] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 There are two limitations on the power handling ability of<br>100��s a transistor; average junction temperature and second<br>5.0 5.0�ms<br>1.0�ms breakdown. Safe operating area curves indicate IC − VCEC − VCE − VCECE<br>TJ = 150°C limits of the transistor that must be observed for reliable<br>2.0 dc operation; i.e., the transistor must not be subjected to greater<br>dissipation than the curves indicate.<br>1.0 The data of Figure 11 is based on TJ(pk) = 150�C; TC isJ(pk) = 150�C; TC is = 150�C; TC is�C; TC isC; TC isC is is<br>SECONDARY BREAKDOWN LIMIT variable depending on conditions. Second breakdown pulse<br>0.5 CURVES APPLY BELOW RATED VTHERMAL LIMIT AT TBONDING WIRE LIMITC = 25CEO°C limits are valid for duty cycles to 10% provided T≤ 150�C. At high case temperatures, thermal limitationsJ(pk)≤ 150�C. At high case temperatures, thermal limitationsJ(pk) 150�C. At high case temperatures, thermal limitationsJ(pk)�C. At high case temperatures, thermal limitationsJ(pk)C. At high case temperatures, thermal limitationsJ(pk)<br>0.2 2N5191 will reduce the power that can be handled to values less than<br>2N5192 the limitations imposed by second breakdown.<br>0.1<br>1.0 2.0 5.0 10 20 50 100<br>VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)<br>Figure 11. Rating and Thermal Data<br>Active−Region Safe Operating Area<br>1.0<br>0.7<br>D = 0.5<br>0.5 � JC(max)  = 3.12°C/W — 2N5190-92<br>0.3<br>0.2<br>0.2<br>0.1<br>0.1 0.05<br>0.07<br>0.02<br>0.05<br>0.03 0.01<br>SINGLE PULSE<br>0.02<br>0.010.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 50 100 200 500 1000<br>t, TIME OR PULSE WIDTH (ms)<br>IC, COLLECTOR CURRENT (AMP)<br>r(t), EFFECTIVE TRANSIENT<br>THERMAL RESISTANCE (NORMALIZED)<br>**----- End of picture text -----**<br>


There are two limitations on the power handling ability of a transistor; average junction temperature and second breakdown. Safe operating area curves indicate IC − VCEC − VCE − VCECE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. 

The data of Figure 11 is based on TJ(pk) = 150�C; TC isJ(pk) = 150�C; TC is = 150�C; TC is�C; TC isC; TC isC is is variable depending on conditions. Second breakdown pulse J(pk) limits are valid for duty cycles to 10% provided T≤ 150�C. At high case temperatures, thermal limitationsJ(pk)≤ 150�C. At high case temperatures, thermal limitationsJ(pk) 150�C. At high case temperatures, thermal limitationsJ(pk)�C. At high case temperatures, thermal limitationsJ(pk)C. At high case temperatures, thermal limitationsJ(pk) will reduce the power that can be handled to values less than the limitations imposed by second breakdown. 

**Figure 12. Thermal Response** 

## **DESIGN NOTE: USE OF TRANSIENT THERMAL RESISTANCE DATA** 

**==> picture [185 x 160] intentionally omitted <==**

**----- Start of picture text -----**<br>
t P<br>PP PP<br>t1<br>1/f<br>t1<br>DUTY CYCLE, D = t1 f - tP<br>PEAK PULSE POWER = PP<br>Figure A<br>**----- End of picture text -----**<br>


A train of periodical power pulses can be represented by the model shown in Figure A. Using the model and the device thermal response, the normalized effective transient thermal resistance of Figure 12 was calculated for various duty cycles. 

To find �JC(t), multiply the value obtained from Figure 12 by the steady state value �JC. 

Example: 

The 2N5190 is dissipating 50 watts under the following conditions: t1 = 0.1 ms, tp = 0.5 ms. (D = 0.2). 

Using Figure 12, at a pulse width of 0.1 ms and D = 0.2, the reading of r(t1, D) is 0.27. 

The peak rise in function temperature is therefore: 

� T = r(t) × PP × � JC = 0.27 × 50 × 3.12 = 42.2 � C 

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**5** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**==> picture [472 x 503] intentionally omitted <==**

**----- Start of picture text -----**<br>
TO−225<br>CASE 77−09<br>4 ISSUE AD<br>DATE 25 MAR 2015<br>1 3<br>2 3 2 1<br>FRONT VIEW BACK VIEW<br>SCALE 1:1<br>E NOTES:<br>1. DIMENSIONING AND TOLERANCING PER<br>A1 ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>Q A 3. NUMBER AND SHAPE OF LUGS OPTIONAL.<br>a<br>PIN 4 MILLIMETERS<br>BACKSIDE TAB DIM MIN MAX<br>A 2.40 3.00<br>A1 1.00 1.50<br>b 0.60 0.90<br>D b2 0.51 0.88<br>P c 0.39 0.63<br>D 10.60 11.10<br>E 7.40 7.80<br>1 2 3<br>a t e 2.04 2.54<br>L 14.50 16.63<br>Jt L1 1.27 2.54<br>P 2.90 3.30<br>L1 Q 3.80 4.20<br>GENERIC<br>L<br>MARKING DIAGRAM*<br>YWW<br>XX<br>XXXXXG<br>2X b2 Y = Year<br>WW = Work Week<br>2X e XXXXX = Device Code<br>b c G = Pb−Free Package<br>*This information is generic. Please refer to<br>FRONT VIEW SIDE VIEW<br>device data sheet for actual part marking.<br>Pb−Free indicator, “G” or microdot “ ”,<br>may or may not be present.<br>STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5:<br>PIN 1. EMITTER PIN 1. CATHODE PIN 1. BASE PIN 1. ANODE 1 PIN 1. MT 1<br>2., 4. COLLECTOR 2., 4. ANODE 2., 4. COLLECTOR 2., 4. ANODE 2 2., 4. MT 2<br>3. BASE 3. GATE 3. EMITTER 3. GATE 3. GATE<br>STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10:<br>PIN 1. CATHODE PIN 1. MT 1 PIN 1. SOURCE PIN 1. GATE PIN 1. SOURCE<br>2., 4. GATE 2., 4. GATE 2., 4. GATE 2., 4. DRAIN 2., 4. DRAIN<br>3. ANODE 3. MT 2 3. DRAIN 3. SOURCE 3. GATE<br>**----- End of picture text -----**<br>


DATE 25 MAR 2015 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42049B** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: TO−225 PAGE 1 OF 1** ~~re~~ ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

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