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XFP236312.500000I
PLL Oscillator, Ultra Low Phase Noise, 312.5 MHz, 3.135 to 3.465 V Supply, -40 to 85 °C, DFN-EP-12
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: RENESAS
- Product type: Timers, Oscillators & Pulse Generators
- MSL:MSL 1 - Unlimited; SVHC:No SVHC (15-Jan-2019)
- MSL: MSL 1 - Unlimited
- SVHC: No SVHC (12-Jan-2017)
- Frequency: 312.5MHz
- No. of Pins: 12Pins
- Product Range: -
- Digital IC Case: DFN-EP
- Supply Voltage Max: 3.465V
- Supply Voltage Min: 3.135V
- Operating Temperature Max: 85°C
- Operating Temperature Min: -40°C
| Delivery and price | |
|---|---|
| Units per pack | 1 |
| Price | 5.22 € |
| Current stock | 200+ |
| Lead time | 7 days |
Datasheet
XF Family of Low Phase Noise Quartz-based PLL Oscillators XF Datasheet ## Description The XF devices are ultra-low phase noise quartz-based PLL oscillators supporting a large range of frequencies and output interface types. These devices are designed to operate at three different power supplies with several pinout configurations, as well as two operational temperature ranges. The XF devices can be programmed to generate an output frequency from 15MHz to 2100MHz with a resolution as low as 1Hz accuracy. The configuration capability of this family of devices allows for fast delivery times for both sample and large production orders. Parts are for one time programming (OTP) at the factory for a fixed frequency application, or can be field programmable using I2C, based on system needs (see notes under Pin Descriptions). ## Pin Assignments |NC<br>OE<br>SDA<br>Voltage Control<br>NC<br>SCL||||||Output 0<br>Output 0b<br>Ground Output<br>VDDCore<br>Ground Core<br>VDDOutput| |---|---|---|---|---|---|---| |||1||12||| |||||||| |||2||11||| |||||||| |||3||10||| |||||||| |||4||9||| |||||||| |||5||8||| |||||||| |||6||7||| |||||||| ## Features - Output types: LVDS, LVPECL, CML - Frequency range: 15MHz to 2100MHz - Output type: HCSL - Frequency range: 15MHz to 725MHz - Supply voltage options: 1.8V, 2.5V, or 3.3V - Phase jitter (12kHz to 20MHz): 120fs typical - Package: 2.5 × 2.0 mm, 0.4mm pitch DFN - Operating temperatures and frequency stability: - -40°C to +85°C, ±25ppm - -40°C to +105°C, ±50ppm ## Typical Applications - FOM Gear Box - Data centers - 10G / 40G / 100G / 400G Ethernet ## Table 1. Pin Descriptions |**Pin Number**|**Pin Name**|**Description**| |---|---|---| |1|NC|No connect.| |2|NC|No connect.| |3|Voltage Control2|Voltage control for VCXO option.| |4|SDA1|Serial data.| |5|OE|Output enable.| |6|SCL1|Serial clock.| |7|VDDOutput|Supply voltage.| |8|Output 0|Output 0.| |9|Output 0b|Complementary output 0.| |10|Ground Output|Connect to ground.| |11|VDDCore|Supply voltage.| |12|Ground Core|Connect to ground.| |13|EPAD (dotted area shown in Pin Assignments diagram)|Connect to ground (required for heat dissipation).| - 1 Pins 4 and 6 are no connect for I2C applications. 2 Pin 3 is no connect for analog VCXO applications. See Ordering Information for more details. ©2019 Integrated Device Technology, Inc. 1 July 22, 2019 XF Datasheet ## Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ESD Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Mechanical Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Solder Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Termination for 3.3V LVPECL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Termination for 2.5V LVPECL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LVDS Driver Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Recommended Termination for HCSL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CML Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package Outline Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ©2019 Integrated Device Technology, Inc. 2 July 22, 2019 XF Datasheet ## Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the device. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Thermal characteristics, in actual applications, should be assessed case by case to guarantee junction temperature does not exceed 125°C. Table 2. Absolute Maximum Ratings |**Item**|**Rating**| |---|---| |VDD|-0.5V to +3.8V| |E/D|-0.5V to +3.8V| |Storage Temperature|-55°C to 125°C| |Maximum Junction Temperature<br>|125°C| |Theta JA(Still air, 2s2p board)~~1~~<br>|97.0 C/W| |Theta JB(Still air, 2s2p board)~~1~~|62.2 C/W| - 1 Thermal characteristics are based on simulation in standard condition. ## ESD Compliance ## Table 3. ESD Compliance Human Body Model (HBM) 2000V ## Mechanical Testing Table 4. Mechanical Testing * |**Parameter**|**Test Method**| |---|---| |Mechanical Shock|Half-sine wave with 0.3ms 3000G. X, Y, Z each direction 1 time.| |Mechanical Vibration|Frequency: 10 to 55MHz amplitude: 1.5mm.<br>Frequency: 55–2000Hz peak value: 20G.<br>Duration time: 4H for each X,Y,Z axis; total 12hours.| |High Temp Operating Life (HTOL)|1000 hours at 125°C (under power).| |Hermetic Seal|Gross leak (air leak test). Fine leak (Helium leak test) He-pressure: 6kgf/cm² 2 hours.| - MSL level does not apply. ## Solder Reflow Profile **==> picture [380 x 156] intentionally omitted <==** **----- Start of picture text -----**<br> tP 10 seconds Max within 5°C of<br>260°C peak<br>260°C<br>Ramp up 3°C/s Max<br>225°C Ramp down not to<br>180°C 50 ±10 seconds exceed 6°C/s<br>above 225°C<br>reflow area<br>160°C<br>120 ±20 seconds in<br>pre-heating area<br>25°C<br>400 seconds Max from +25°C to 260°C peak<br>**----- End of picture text -----**<br> ©2019 Integrated Device Technology, Inc. 3 July 22, 2019 XF Datasheet ## DC Electrical Characteristics Note for all DC Electrical Characteristics tables: A pull-up resistor from VDD to OE enables output when pin 5 is left open. ## Table 5. 3.3V IDD DC Electrical Characteristics VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. |**Symbol**|**Parameter**|**Output Type**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**| |---|---|---|---|---|---|---|---| |IDD|Current Consumption|LVDS<br>LVPECL<br>HCSL<br>CML|15MHz to 400MHz.<br>400MHz to 2.1GHz.|—|59|67|mA| |||||—|—|85|| ||||15MHz to 212.5MHz.<br>212MHz to 400MHz.<br>400MHz to 2.1GHz.|—|84|94|| |||||—|—|110|| |||||—|—|110|| ||||15MHz to 725MHz.|—|74|83|| ||||15MHz to 2.1GHz.|—|45|61|| Table 6. 2.5V IDD DC Electrical Characteristics VDD = 2.5V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. |**Symbol**|**Parameter**|**Output Type**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**| |---|---|---|---|---|---|---|---| |IDD|Current Consumption|LVDS|15MHz to 400MHz.|—|59|66|mA| ||||400MHz to 2.1GHz.|—|—|85|| |||LVPECL|15MHz to 156.25MHz.|—|84|94|| ||||156.25MHz to 400MHz.|—|—|110|| ||||400MHz to 2.1GHz.|—|—|110|| |||HCSL|15MHz to 400MHz.|—|—|95|| ||||400MHz to 725MHz.|—|74|82|| |||CML|15MHz to 2.1GHz.|—|54|61|| ## Table 7. 1.8V IDD DC Electrical Characteristics VDD = 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. |**Symbol**|**Parameter**|**Output Type**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**| |---|---|---|---|---|---|---|---| |IDD|Current Consumption|LVDS|15MHz to 400MHz.|—|59|66|mA| ||||400MHz to 2.1GHz.|—|—|85|| |||LVPECL|15MHz to 250MHz.|—|84|93|| ||||250MHz to 2.1GHz.|—|—|110|| |||HCSL|15MHz to 400MHz.|—|—|95|| ||||400MHz to 725MHz.|—|74|81|| |||CML|15MHz to 2.1GHz.|—|54|61|| ©2019 Integrated Device Technology, Inc. July 22, 2019 4 XF Datasheet ## Table 8. LVCMOS DC Electrical Characteristics VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. |**Symbol**|**Parameter**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**| |---|---|---|---|---|---|---| |VIH|Input High Voltage (OE pin only)|VDD= 3.3V, 2.5V, 1.8V ±5%|0.7 × VDD|—|VDD+ 0.3|V| |VIL|Input Low Voltage (OE pin only)|VDD= 3.3V, 2.5V, 1.8V ±5%|GND - 0.3|—|0.3 × VDD|V| ## Table 9. LVDS DC Electrical Characteristics VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. |**Symbol**|**Parameter**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**| |---|---|---|---|---|---|---| |VOD|Differential Output Voltage|VDD= 3.3V, 2.5V, 1.8V ±5%|0.30|0.44|0.60|V| |VOS|Output Offset Voltage|VDD= 3.3V ±5%|1.11|1.26|1.41|| |||VDD= 2.5V ±5%|1.08|1.25|1.41|| |||VDD= 1.8V ±5%|0.75|0.88|1.01|| ## Table 10. LVPECL DC Electrical Characteristics VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. |**Symbol**|**Parameter**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**| |---|---|---|---|---|---|---| |VOH|Output High Voltage|VDD= 3.3V ±5%.|2.28|2.49|2.72|V| |||VDD= 2.5V ±5%.|1.52|1.69|1.87|| |||VDD= 1.8V ±5%.|0.83|0.96|1.11|| |VOL|Output Low Voltage|VDD= 3.3V ±5%.|1.68|1.84|2.01|| |||VDD= 2.5V ±5%.|0.92|1.04|1.17|| |||VDD= 1.8V ±5%.|0.19|0.30|0.42|| ## Table 11. HCSL DC Electrical Characteristics VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. |**Symbol**|**Parameter**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**| |---|---|---|---|---|---|---| |VOH|Output High Voltage|VDD= 3.3V ±5%.|0.78|0.92|1.07|V| |||VDD= 2.5V ±5%.|0.74|0.88|1.03|| |||VDD= 1.8V ±5%.|0.67|0.81|0.95|| |VOL|Output Low Voltage|—|-0.06|0.07|0.20|| ©2019 Integrated Device Technology, Inc. July 22, 2019 5 XF Datasheet ## Table 12. CML DC Electrical Characteristics VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. |**Symbol**|**Parameter**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**| |---|---|---|---|---|---|---| |VOH|Output High Voltage|VDD= 3.3V ±5%.|3.09|3.26|3.43|V| |||VDD= 2.5V ±5%.|2.33|2.46|2.59|| |||VDD= 1.8V ±5%.|1.66|1.76|1.85|| |VOL|Output Low Voltage|VDD= 3.3V ±5%.|2.70|2.85|3.00|V| |||VDD= 2.5V ±5%.|1.95|2.06|2.17|| |||VDD= 1.8V ±5%.|1.30|1.37|1.45|| ## Table 13. DC Electrical Characteristics – Leakage Current VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz. |**Symbol**|**Parameter**|**Input**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**| |---|---|---|---|---|---|---|---| |IIH|Input Leakage High|OE|VDD= 3.3V ±5%.|-5|0.81|5|µA| |||SCLK||-5|1.36|5|| |||SDATA||-5|1.44|5|| |IIL|Input Leakage Low|OE|VDD= 3.3V ±5%.|-20|-17.44|-14|µA| |||SCLK||-37|-33.49|-30|| |||SDATA||-20|-17.02|-14|| ## AC Electrical Characteristics Notes for all AC Electrical Characteristics tables: 1. A pull-up resistor from VDD to OE enables output when pin 5 is left open. 2. Installation should include a 0.01μF bypass capacitor placed between VDD and GND to minimize power supply line noise. ## Table 14. 3.3V AC Electrical Characteristics VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C. |**Symbol**|**Parameter**|**Test Condition**|**Minimum**|**Typical**|**Maximum**|**Units**| |---|---|---|---|---|---|---| |F|Output Frequency Range|LVDS, LVPECL, CML.|15|—|2100|MHz| |||HCSL.|15|—|725|| ||Frequency Stability|Temperature = -40°C to +85°C.|—|—|±25|ppm| |||Temperature = -40°C to +105°C.|—|—|±50|ppm| ||Frequency Tolerance (25°C)|Temperature = 25°C.|-15|±10|-15|ppm| ||Aging (1st year)|TA= 25°C.|—|—|±3|ppm| ||Aging (10 years)|TA= 25°C.|—|—|±10|ppm| ©2019 Integrated Device Technology, Inc. 6 July 22, 2019 XF Datasheet ## Table 14. 3.3V AC Electrical Characteristics (Cont.) VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C. |**Symbol**|**Parameter**|**Test Condition**|**Test Condition**|**Minimum**|**Typical**|**Maximum**|**Units**| |---|---|---|---|---|---|---|---| ||Output Load|LVDS.|Differential.|—|100|—|Ω| |||LVPECL.|VDD- 2.0V.|—|50|—|| |||HCSL.|To GND.|—|50|—|| |TST|Start-up Time|Output valid time after VDDmeets minimum<br>specified level.||—|5|—|ms| |tR|Output Rise Time|LVDS.|20% – 80%,<br>156.25MHz|—|299|400|ps| |||LVPECL.||—|287|400|| |||HCSL.||—|306|400|| |||CML||—|301|400|| |tF|Output Fall Time|LVDS.|80% – 20%,<br>156.25MHz|—|279|400|ps| |||LVPECL.||—|274|400|| |||HCSL.||—|284|400|| |||CML||—|279|400|| |ODC|Output Clock Duty Cycle|LVDS.|156.25MHz|45|—|55|%| |||LVPECL.|156.25MHz|45|—|55|| |||HCSL.|156.25MHz|45|—|55|| |||CML|156.25MHz|45|—|55|| |TOE|Output Enable/Disable Time|—|—|—|1|—|ms| ©2019 Integrated Device Technology, Inc. July 22, 2019 7 XF Datasheet ## Table 15. 2.5V AC Electrical Characteristics VDD = 2.5V ±5%, TA = -40°C to +85°C, -40°C to +105°C. |**Symbol**|**Parameter**|**Test Condition**|**Test Condition**|**Minimum**|**Typical**|**Maximum**|**Units**| |---|---|---|---|---|---|---|---| |F|Output Frequency Range|LVDS, LVPECL, CML.||15|—|2100|MHz| |||HCSL.||15|—|725|| ||Frequency Stability|Temperature = -40°C to +85°C.||—|—|±25|ppm| |||Temperature = -40°C to +105°C.||—|—|±50|ppm| ||Frequency Tolerance (25°C)|Temperature = 25°C.||-15|±10|+15|ppm| ||Aging (1st year)|TA= 25°C.||—|—|±3|| ||Aging (10 years)|TA= 25°C.||—|—|±10|| ||Output Load|LVDS.|Differential.|—|100|—|Ω| |||LVPECL.|VDD- 2.0V.|—|50|—|| |||HCSL.|To GND.|—|50|—|| |TST|Start-up Time|Output valid time after VDDmeets minimum<br>specified level.||—|5|—|ms| |tR|Output Rise Time|LVDS.|20% – 80%,<br>156.25MHz|—|303|400|ps| |||LVPECL.||—|292|400|| |||HCSL.||—|310|400|| |||CML||—|304|400|| |tF|Output Fall Time|LVDS.|80% – 20%,<br>156.25MHz|—|282|400|ps| |||LVPECL.||—|278|400|| |||HCSL.||—|288|400|| |||CML||—|281|400|| |ODC|Output Clock Duty Cycle|LVDS.|156.25MHz|45|—|55|%| |||LVPECL.|156.25MHz|45|—|55|| |||HCSL.|156.25MHz|45|—|55|| |||CML|156.25MHz|45|—|55|| |TOE|Output Enable/Disable Time|—|—|—|1|—|ms| ©2019 Integrated Device Technology, Inc. 8 July 22, 2019 XF Datasheet ## Table 16. 1.8V AC Electrical Characteristics VDD = 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C. |**Symbol**|**Parameter**|**Test Condition**|**Test Condition**|**Minimum**|**Typical**|**Maximum**|**Units**| |---|---|---|---|---|---|---|---| |F|Output Frequency Range|LVDS, LVPECL, CML.||15|—|2100|MHz| |||HCSL.||15|—|725|| ||Frequency Stability|Temperature = -40°C to +85°C.||—|—|±25|ppm| |||Temperature = -40°C to +105°C.||—|—|±50|ppm| ||Frequency Tolerance (25°C)|Temperature = 25°C.||-15|±10|+15|ppm| ||Aging (1st year)|TA= 25°C.||—|—|±3|| ||Aging (10 years)|TA= 25°C.||—|—|±10|| ||Output Load|LVDS.|Differential.|—|100|—|Ω| |||LVPECL, HCSL.|To GND.|—|50|—|| |TST|Start-up Time|Output valid time after VDDmeets minimum<br>specified level.||—|5|—|ms| |tR|Output Rise Time|LVDS.|20% – 80%,<br>156.25MHz|—|311|450|ps| |||LVPECL.||—|312|450|| |||HCSL.||—|316|450|| |||CML||—|313|450|| |tF|Output Fall Time|LVDS.|80% – 20%,<br>156.25MHz|—|290|450|ps| |||LVPECL.||—|297|450|| |||HCSL.||—|294|450|| |||CML||—|289|450|| |ODC|Output Clock Duty Cycle|LVDS.|156.25MHz|45|—|55|%| |||LVPECL.|156.25MHz|45|—|55|| |||HCSL.|156.25MHz|45|—|55|| |||CML|156.25MHz|45|—|55|| |TOE|Output Enable/Disable Time|—|—|—|1|—|ms| ## Table 17. Phase Jitter Characteristics VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C. |**Symbol**|**Parameter**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**| |---|---|---|---|---|---|---| |fJITTER|Phase Jitter (12kHz – 20MHz)|250.00MHz|—|115|—|fsec| |||312.50MHz|—|125|—|fsec| |||625.00MHz|—|123|—|fsec| |||644.53MHz|—|120|—|fsec| ©2019 Integrated Device Technology, Inc. 9 July 22, 2019 XF Datasheet ## Output Waveforms Figure 1. LVDS Output Waveforms **==> picture [188 x 10] intentionally omitted <==** **----- Start of picture text -----**<br> Output Levels /Rise Time/Fall Time Measurements<br>**----- End of picture text -----**<br> **==> picture [388 x 270] intentionally omitted <==** **----- Start of picture text -----**<br> TR TF<br>OUT0b<br>20% to 80% VOS VOD<br>OUT0<br>Oscillator Symmetry<br>OUT0b VOH<br>OUT0 VOL<br>½ Period<br>Period<br>**----- End of picture text -----**<br> Figure 2. LVPECL Output Waveforms **==> picture [135 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> Rise Time/Fall Time Measurements<br>**----- End of picture text -----**<br> **==> picture [349 x 259] intentionally omitted <==** **----- Start of picture text -----**<br> TR TF<br>OUT0b VOH<br>20% to 80%<br>OUT0 VOL<br>Oscillator Symmetry<br>OUT0b VOH<br>OUT0 VOL<br>½ Period<br>Period<br>**----- End of picture text -----**<br> ©2019 Integrated Device Technology, Inc. 10 July 22, 2019 XF Datasheet ## Figure 3. HCSL Output Waveforms **==> picture [369 x 278] intentionally omitted <==** **----- Start of picture text -----**<br> Rise Time/Fall Time Measurements<br>TR TF<br>OUT0b VOH<br>20% to 80%<br>OUT0 VOL<br>Oscillator Symmetry<br>OUT0b VOH<br>OUT0 VOL<br>½ Period<br>Period<br>**----- End of picture text -----**<br> Figure 4. CML Output Waveforms ## **Rise Time/Fall Time Measurements** **==> picture [349 x 252] intentionally omitted <==** **----- Start of picture text -----**<br> TR TF<br>OUT0b VOH<br>20% to 80%<br>OUT0 VOL<br>Oscillator Symmetry<br>OUT0b VOH<br>OUT0 VOL<br>½ Period<br>Period<br>**----- End of picture text -----**<br> ©2019 Integrated Device Technology, Inc. 11 July 22, 2019 XF Datasheet ## Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential output is a low impedance follower output that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figure 5 and Figure 6 show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. ## Figure 5. 3.3V LVPECL Output Termination Figure 6. 3.3V LVPECL Output Termination **==> picture [219 x 122] intentionally omitted <==** **----- Start of picture text -----**<br> 3.3V<br>R3 R4<br>125Ω 125Ω<br>3.3V<br>3.3V<br>Zo = 50Ω<br>+<br>_<br>Zo = 50Ω Input<br>R1 R2<br>84Ω 84Ω<br>**----- End of picture text -----**<br> ©2019 Integrated Device Technology, Inc. 12 July 22, 2019 XF Datasheet ## Termination for 2.5V LVPECL Outputs Figure 7 and Figure 8 show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground level. The R3 in Figure 8 can be eliminated and the termination is shown in Figure 9 _._ ## Figure 7. 2.5V LVPECL Driver Termination Example **==> picture [237 x 128] intentionally omitted <==** **----- Start of picture text -----**<br> 2.5V<br>2.5V<br>VCCO = 2.5V<br>R1 R3<br>250 250<br>50Ω<br>+<br>50Ω<br>–<br>2.5V LVPECL Driver<br>R2 R4<br>62.5 62.5<br>**----- End of picture text -----**<br> ## Figure 8. 2.5V LVPECL Driver Termination Example **==> picture [236 x 121] intentionally omitted <==** **----- Start of picture text -----**<br> 2.5V<br>VCCO = 2.5V<br>50Ω<br>+<br>50Ω<br>–<br>2.5V LVPECL Driver<br>R1 R2<br>50 50<br>**----- End of picture text -----**<br> ## Figure 9. 2.5V LVPECL Driver Termination Example **==> picture [236 x 142] intentionally omitted <==** **----- Start of picture text -----**<br> 2.5V<br>VCCO = 2.5V<br>50Ω<br>+<br>50Ω<br>–<br>2.5V LVPECL Driver<br>R1 R2<br>50 50<br>R3<br>18<br>**----- End of picture text -----**<br> ©2019 Integrated Device Technology, Inc. 13 July 22, 2019 XF Datasheet ## LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90Ω and 132Ω. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100Ω parallel resistor at the receiver and a 100Ω differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 10 can be used with either type of output structure. Figure 11, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. Figure 10. Standard LVDS Termination Figure 11. Optional LVDS Termination ©2019 Integrated Device Technology, Inc. 14 July 22, 2019 XF Datasheet ## Recommended Termination for HCSL Outputs Figure 12 is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This termination is the standard for PCI Express™ and HCSL output types. All traces should be 50Ω impedance single-ended or 100Ω differential. Figure 13 is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional resistor can range from 0Ω to 33Ω. All traces should be 50 Ω impedance single-ended or 100Ω differential. Figure 12. Recommended Source Termination (where the driver and receiver will be on separate PCBs) **==> picture [500 x 179] intentionally omitted <==** **----- Start of picture text -----**<br> Rs<br>0.5" Max 0-0.2" 1-14" 0.5 - 3.5"<br>22 to 33 +/-5%<br>L1 L2 L4 L5<br>L1 L2 L4 L5<br>PCI Express<br>PCI Express<br>Connector<br>Driver PCI Express<br>0-0.2" L3 L3<br>Add-in Card<br>Rt 49.9 +/- 5%<br>**----- End of picture text -----**<br> Figure 13. Recommended Termination (where a point-to-point connection can be used) **==> picture [420 x 139] intentionally omitted <==** **----- Start of picture text -----**<br> Rs<br>0.5" Max 0-18" 0-0.2"<br>0 to 33<br>L1 L2 L3<br>0 to 33<br>L1 L2 L3<br>PCI Express<br>Driver Rt 49.9 +/- 5%<br>**----- End of picture text -----**<br> ## CML Termination Figure 14 shows an example of the termination for a CML driver. In this example, the transmission line characteristic impedance is 50Ω. The R1 and R2 50Ω matched load terminations are pulled up to VDDO. The matched loads are located close to the receiver. Figure 14. CML Termination Example **==> picture [257 x 131] intentionally omitted <==** **----- Start of picture text -----**<br> VDDO<br>VDDO<br>R1 R2<br>50 50<br>Zo = 50<br>Zo = 50<br>CML Driv er<br>**----- End of picture text -----**<br> ©2019 Integrated Device Technology, Inc. 15 July 22, 2019 XF Datasheet ## Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.idt.com/document/psc/njg12-package-outline-drawing-200-x-250-x-100-mm-body-epad-080-x-190-mm-040mm-pitch-dfn ## Marking Diagram ▪ Lines 1 indicates the following: ABC-YW $PF** - “ABC” denotes the truncated first three digits of the frequency code (e.g., 156). - “-YW” denotes the last digit of the year and week when the part was assembled. - Line 2 indicates the following: - “$” denotes the mark location code. - “PF” denotes the package and frequency codes, where “P” = package code and “F” = frequency code. - “**” denotes the sequential lot number. ## Ordering Information **==> picture [556 x 295] intentionally omitted <==** **----- Start of picture text -----**<br> XF L 2 3 5 125.000000 I<br>Family and ASIC Output Type Package Voltage Precision Frequency Temperature Range<br>I: Industrial range – 40 to +85 °C<br>1: 1.8 VDC ±5% K: Extended industrial range – 40 to +105 °C<br>2: 2.5 VDC ±5%<br>3: 3.3 VDC ±5%<br>2: 2.5 x 2.0 mm<br>C: CML<br>L: LVDS 125.000000 Listed in MHz to 6 digits<br>015.000000MHz to 999.999999MHz<br>P: LVPECL<br>N: HCSL F00.000000 to F99.999999 1500MHz to 1599.999MHz<br>G00.000000 to G99.999999 1600MHz to 1699.999MHz<br>H00.000000 to H99.999999 1700MHz to 1799.999MHz<br>XF: 150fs jitter I00.000000 to I99.999999 1800MHz to 1899.999MHz<br>J00.000000 to J99.999999 1900MHz to 1999.999MHz<br>K00.000000 to K99.999999 2000MHz to 2099.999MHz<br>**----- End of picture text -----**<br> **5:** ±50 ppm (K only) **6:** ±25 ppm (I only) ©2019 Integrated Device Technology, Inc. 16 July 22, 2019 XF Datasheet ## Revision History |**Revision Date**|**Description of Change**| |---|---| |July 22, 2019|Updated LVDS Differential Output Voltage minimum value from 0.28V to 0.30V.| |May 22, 2019|Changed 3.3V, 2.5V, and 1.8V LVPECL current consumption conditions value from 670MHz to 2.1GHz.| |April 3, 2019|Initial release| Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road 1-800-345-7015 or 408-284-8200 www.IDT.com/go/support San Jose, CA 95138 USA Fax: 408-284-2775 www.IDT.com www.IDT.com/go/sales DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved. ©2019 Integrated Device Technology, Inc. 17 July 22, 2019
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