# Power MOSFET, N Channel, 55 V, 7 A, 0.035 ohm, TO-220, Through Hole

![Product image](https://novapart.co/image/farnell:1739424/)

**URL**: https://novapart.co/products/VNP14NV04-E/power-mosfet-n-channel-55-v-7-a-0035-ohm-to-220
**SKU**: VNP14NV04-E
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.5680
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Power Dissipation | 70W |
| Transistor Mounting | Through Hole |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 70W |
| Rds(On) Test Voltage | 5V |
| On Resistance Rds(On) | 0.035ohm |
| Transistor Case Style | TO-220 |
| Drain Source Voltage Vds | 55V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 7A |
| Drain Source On State Resistance | 0.035ohm |
| Gate Source Threshold Voltage Max | 2.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1739424/)

**VNB14NV04, VND14NV04 VND14NV04-1** "OMNIFET II" full auto rotected Power MOSFET y p 

## **Features** 

**TYPE RDS(on) Ilim Vclamp** VNB14NV04 VND14NV04 35 mΩ 12 A 40 V VND14NV04-1 ~~nr~~ I Linear current limitation 

- I Thermal shutdown 

- I Short circuit protection 

- I Integrated clamp 

- I Low current drawn from input pin 

- I Diagnostic feedback through input pin 

- I ESD protection 

- I Direct access to the gate of the Power MOSFET (analog driving) 

- I Compatible with standard Power MOSFET 

## **Description** 

The VNB14NV04, VND14NV04, VND14NV04-1 are monolithic devices made using STMicroeletronics VIPower M0 Technology, intended for replacement of standard power MOSFETS in DC to 50 KHz applications. Built-in thermal shutdown, linear current limitation and overvoltage clamp protect the chip in harsh enviroments. 

Fault feedback can be detected by monitoring the voltage at the input pin. 

## **Table 1. Device summary** 

|**Package**|**Tube**|**Tube (Lead free)**|**Tape and reel**|**Tape and reel (Lead free)**|
|---|---|---|---|---|
|D2PAK|VNB14NV04|VNB14NV04-E|VNB14NV0413TR|VNB14NV04TR-E|
|TO-252 (DPAK)|VND14NV04|VND14NV04-E|VND14NV0413TR|VND14NV04TR-E|
|TO-251 (IPAK)|VND14NV04-1|VND14NV04-1-E|-|-|



April 2009 

Rev 1 

1/25 

_www.st.com_ 

**Contents** 

**VNB14NV04, VND14NV04, VND14NV04-1** 

## **Contents** 

|**1**|**Block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|---|---|
|**2**|**Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
||2.2<br>Thermal data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
||2.3<br>Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
|**3**|**Protection features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7**|
|**4**|**Package thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16**|
||4.1<br>DPAK thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
||4.2<br>D2PAK thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|**5**|**Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21**|
|**6**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24**|



2/25 

**VNB14NV04, VND14NV04, VND14NV04-1** 

**Block diagram** 

## **1 Block diagram** 

## **Figure 1. Block diagram** 

3/25 

**Electrical specification** 

**VNB14NV04, VND14NV04, VND14NV04-1** 

## **2 Electrical specification** 

## **Figure 2. Current and voltage conventions** 

## **2.1 Absolute maximum rating** 

## **Table 2. Absolute maximum rating** 

|**Symbol**|**Parameter**|**Value**|**Value**|**Value**|**Unit**|
|---|---|---|---|---|---|
|||**DPAK**|**IPAK**|**D2PAK**||
|VDS<br>~~es~~<br>~~es~~|Drain-source voltage (VIN=0 V)|Internally Clamped|||V|
|VIN<br>~~es~~<br>~~es~~|Input voltage|Internally Clamped|||V|
|IIN<br>~~es~~<br>~~a~~<br>~~ee~~|Input current|+/-20|||mA|
|RIN MIN<br>~~ee~~<br>~~ee~~|Minimum input series impedance|10|||Ω|
|ID<br>~~ee~~<br>~~ee~~<br>~~ee~~|Drain current|Internally Limited|||A|
|IR<br>~~ee~~<br>~~ee~~|Reverse DC output current|-15|||A|
|VESD1<br>~~ee~~|Electrostatic discharge (R=1.5 KΩ, C=100 pF)|4000|||V|
|VESD2<br>~~a~~|Electrostatic discharge on output pin only (R=330Ω,<br>C=150 pF)<br>|16500<br>|||V<br>|
|Ptot<br>|Total dissipation at Tc=25 °C<br>|74<br>|74<br>|74<br>|W<br>|
|EMAX<br>~~ee~~<br>~~ee~~|Maximum switching energy (L=0.4 mH; RL=0Ω;<br>Vbat=13.5 V; Tjstart=150 °C; IL=18 A)<br>~~ee~~|93<br>~~ee~~|~~ee~~|93<br>~~ee~~|mJ<br>~~ee~~|
|Tj<br>~~ee~~<br>~~es~~|Operating junction temperature|Internally limited|||°C|
|Tc<br>~~ee~~<br>~~es~~|Case operating temperature|Internally limited|||°C|
|Tstg<br>~~es~~<br>~~a~~|Storage temperature|-55 to 150|||°C|



4/25 

**VNB14NV04, VND14NV04, VND14NV04-1** 

**Electrical specification** 

## **2.2 Thermal data** 

## **Table 3. Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Value**|**Value**|**Unit**|
|---|---|---|---|---|---|
|||**DPAK**|**IPAK**|**D2PAK**||
|Rthj-case|Thermal resistance junction-case max|1.7|1.7|1.7|°C/W|
|Rthj-lead|Thermal resistance junction-lead max||||°C/W|
|Rthj-amb|Thermal resistance junction-ambient max|65(1)|102|52(1)|°C/W|



1. When mounted on a standard single-sided FR4 board with 0.5cm[2] of Cu (at least 35 µm thick) connected to all DRAIN pins. Horizontal mounting and no artificial air flow. 

## **2.3 Electrical characteristics** 

-40 < Tj < 150 °C unless otherwise specified. 

## **Table 4. Electrical characteristics** 

|**Table 4.**|**Electrical characteristics**||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|**Off**|||||||
|VCLAMP|Drain-source clamp voltage|VIN=0 V; ID=7 A|40|45|55|V|
|VCLTH|Drain-source clamp threshold<br>voltage|VIN=0 V; ID=2 mA|36|||V|
|VINTH|Input threshold voltage|VDS=VIN; ID=1 mA|0.5||2.5|V|
|IISS|Supply current from input pin|VDS=0 V; VIN=5 V||100|150|µA|
|VINCL|Input-source clamp voltage|IIN=1 mA<br>IIN=-1 mA|6<br>-1.0|6.8|8<br>-0.3|V|
|IDSS|Zero input voltage drain current<br>(VIN=0 V)|VDS=13 V; VIN=0 V; Tj=25 °C<br>VDS=25 V; VIN=0 V|||30<br>75|µA|
|**On**|||||||
|RDS(on)|Static drain-source on resistance|Vin= 5 V ID= 7 A Tj= 25 °C<br>Vin= 5 V ID= 7 A|||35<br>70|mΩ|
|**Dynamic (Tj=25°C, unless otherwise specified)**|||||||
|gfs (1)|Forward transconductance|VDD= 13 V ID= 7 A||18||S|
|Coss|Output capacitance|VDS= 13 V f = 1 MHz VIN= 0 V||400||pF|
|**Switching**|||||||
|td(on)|Turn-on delay time|VDD= 15 V ID= 7 A<br>Vgen= 5 V Rgen= RIN MIN=10Ω<br>(see_Figure 3_)||80|250|ns|
|tr|Rise time|||350|1000|ns|
|td(off)|Turn-off delay time|||450|1350|ns|
|tf|Fall time|||150|500|ns|



5/25 

**Electrical specification** 

**VNB14NV04, VND14NV04, VND14NV04-1** 

## **Table 4. Electrical characteristics (continued)** 

|**Symbol**|**Parameter**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 15 V Id= 7 A<br>Vgen= 5 V Rgen= 2.2 KΩ<br>(see_Figure 3_)||1.5|4.5|µs|
|tr|Rise time|||9.7|30.0|µs|
|td(off)|Turn-off delay time||||25.0|µs|
|tf|Fall time|||10.2|30.0|µs|
|(di/dt)on|Turn-on current slope|VDD= 15 V ID= 7 A<br>Vgen= 5 V Rgen= RIN MIN=10Ω||16||A/µs|
|Qi|Total input charge|VDD= 12 V ID= 7 A Vin= 5 V;<br>Igen= 2.13 mA (see_Figure 7_)||36.8||nC|
|**Source drain diode**|||||||
|VSD<br>(1)|Forward on voltage|ISD= 7 A Vin= 0 V||0.8||V|
|trr|Reverse recovery time|ISD= 7 A; di/dt = 40 A/µs<br>VDD= 30 V L = 200 µH<br>(see test circuit,_Figure 4_)||300||ns|
|Qrr|Reverse recovery charge|||0.8||µC|
|IRRM|Reverse recovery current|||5||A|
|**Protection**|||||||
|Ilim|Drain current limit|VIN= 5 V; VDS= 13 V|12|18|24|A|
|tdlim|Step response current limit|VIN= 5 V; VDS= 13 V||45||µs|
|Tjsh|Over temperature shutdown||150|175|200|°C|
|Tjrs|Over temperature reset||135|||°C|
|Igf|Fault sink current|VIN= 5 V; VDS= 13 V; Tj= Tjsh|10|15|20|mA|
|Eas|Single pulse avalanche energy|starting Tj= 25 °C; VDD= 24 V<br>VIN= 5 V; Rgen= RIN MIN= 10Ω;<br>L = 24 mH (see_Figure 5_and<br>_Figure 6_)|400|||mJ|



1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 

6/25 

**VNB14NV04, VND14NV04, VND14NV04-1** 

**Protection features** 

## **3 Protection features** 

During normal operation, the input pin is electrically connected to the gate of the internal power MOSFET through a low impedance path. 

The device then behaves like a standard power MOSFET and can be used as a switch from DC up to 50 KHz. The only difference from the user’s standpoint is that a small DC current IISS (typ. 100 µA) flows into the input pin in order to supply the internal circuitry. 

The device integrates: 

- G Overvoltage clamp protection: internally set at 45 V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. 

- G Linear current limiter circuit: limits the drain current ID to Ilim whatever the input pin voltages. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the over temperature threshold Tjsh. 

- G Over temperature and short circuit protection: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Over temperature cutout occurs in the range 150 to 190 °C, a typical value being 170 °C. The device is automatica lly restarted when the chip temperature falls of about 15 °C below shutdown temp erature. 

- G Status feedback: in the case of an over temperature fault condition (Tj > Tjsh), the device tries to sink a diagnostic current Igf through the input pin in order to indicate fault condition. If driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. If the drive impedance is high enough so that the input pin driver is not able to supply the current Igf, the input pin will fall to 0 V. This will not however affect the device operation: no requirement is put on the current capability of the input pin driver except to be able to supply the normal operation drive current IISS. 

Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit. 

7/25 

**Protection features** 

**VNB14NV04, VND14NV04, VND14NV04-1** 

## **Figure 3. Switching time test circuit for resistive load** 

## **Figure 4. Test circuit for diode recovery times** 

8/25 

**VNB14NV04, VND14NV04, VND14NV04-1** 

**Protection features** 

## **Figure 5. Unclamped inductive load test Figure 6. Unclamped inductive waveforms circuits** 

## **Figure 7. Input charge test circuit** 

9/25 

**Protection features** 

**VNB14NV04, VND14NV04, VND14NV04-1** 

## **Figure 8. Source-drain diode forward characteristics** 

## **Figure 9. Static drain source on resistance** 

## **Figure 10. Derating curve** 

## **Figure 11. Static drain-source on resistance vs. input voltage (part 1/2)** 

**Figure 12. Static drain-source on resistance Figure 13. Transconductance vs. input voltage (part 2/2)** 

10/25 

**VNB14NV04, VND14NV04, VND14NV04-1** 

**Protection features** 

## **Figure 14. Static drain-source on resistance Figure 15. Transfer characteristics vs. id** 

## **Figure 16. Turn-on current slope (part 1/2)** 

## **Figure 17. Turn-on current slope (part 2/2)** 

**Figure 18. Input voltage vs. input charge** 

**Figure 19. Turn-off drain source voltage slope (part 1/2)** 

11/25 

**Protection features** 

**VNB14NV04, VND14NV04, VND14NV04-1** 

## **Figure 20. Turn-off drain source voltage slope Figure 21. Capacitance variations (part 2/2)** 

**Figure 22. Switching time resistive load (part Figure 23. Switching time resistive load (part 1/2) 2/2)** 

**Figure 24. Output characteristics** 

## **Figure 25. Normalized on resistance vs. temperature** 

12/25 

**VNB14NV04, VND14NV04, VND14NV04-1** 

**Protection features** 

**Figure 26. Normalized input threshold voltage Figure 27. Current limit vs. junction vs. temperature temperatures** 

## **Figure 28. Step response current limit** 

13/25 

**Protection features** 

**VNB14NV04, VND14NV04, VND14NV04-1** 

## **Figure 29. DPAK Maximum turn-off current versus load inductance** 

Legend: 

A= Single pulse at TJstart=150ºC 

B= Repetitive pulse at TJstart=100ºC 

C= Repetitive pulse at TJstart=125ºC 

Conditions: 

VCC=13.5 V 

Values are generated with RL=0Ω 

In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. 

## **Figure 30. Demagnetization** 

14/25 

**VNB14NV04, VND14NV04, VND14NV04-1** 

**Protection features** 

## **Figure 31. D[2] PAK Maximum turn-off current versus load inductance** 

**==> picture [30 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Legend:<br>**----- End of picture text -----**<br>


A= Single pulse at TJstart=150ºC 

B= Repetitive pulse at TJstart=100ºC 

C= Repetitive pulse at TJstart=125ºC 

Conditions: 

VCC=13.5 V 

Values are generated with RL=0Ω 

In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. 

**Figure 32. Demagnetization** 

15/25 

**Package thermal data** 

**VNB14NV04, VND14NV04, VND14NV04-1** 

## **4 Package thermal data** 

## **4.1 DPAK thermal data** 

## **Figure 33. DPAK PC board** 

**Figure 34. Rthj-amb vs PCB copper area in open box free air condition** 

16/25 

**VNB14NV04, VND14NV04, VND14NV04-1** 

**Package thermal data** 

**Figure 35. DPAK thermal impedance junction ambient single pulse** 

## **Figure 36. Thermal fitting model of an OMNIFET II in DPAK** 

## **Pulse calculation formula** 

## Z = R ⋅ δ + Z (1 – δ) THδ TH THtp where δ = t ⁄ T p 

|**Area/island(cm2)**|**Footprint**|**6**|
|---|---|---|
|R1 (°C/W)|0.1||
|R2 (°C/W)|0.35||
|R3 ( °C/W)|1.20||
|R4 (°C/W)|2||
|R5 (°C/W)|15||
|R6 (°C/W)|61|24|
|C1 (W.s/°C)|0.0006||
|C2 (W.s/°C)|0.0021||
|C3 (W.s/°C)|0.05||



17/25 

**Package thermal data** 

**VNB14NV04, VND14NV04, VND14NV04-1** 

## **Table 5. Thermal parameter (continued)** 

|**Area/island(cm2)**|**Footprint**|**6**|
|---|---|---|
|C4 (W.s/°C)|0.3||
|C5 (W.s/°C)|0.45||
|C6 (W.s/°C)|0.8|5|



## **4.2 D[2] PAK thermal data** 

## **Figure 37. D[2] PAK PC board** 

## **Figure 38. Rthj-amb vs PCB copper area in open box free air condition** 

18/25 

**VNB14NV04, VND14NV04, VND14NV04-1** 

**Package thermal data** 

## **Figure 39. D[2] PAK thermal impedance junction ambient single pulse** 

## **Figure 40. Thermal fitting model of an OMNIFET II in D[2] PAK** 

## **Pulse calculation formula** 

## Z = R ⋅ δ + Z (1 – δ) THδ TH THtp where δ = t ⁄ T p 

|**Area/island(cm2)**|**Footprint**|**6**|
|---|---|---|
|R1 (°C/W)|0.1||
|R2 (°C/W)|0.35||
|R3 ( °C/W)|0.3||
|R4 (°C/W)|4||
|R5 (°C/W)|9||
|R6 (°C/W)|37|22|
|C1 (W.s/°C)|0.0006||
|C2 (W.s/°C)|2.10E-03||
|C3 (W.s/°C)|8.00E-02||



19/25 

**Package thermal data** 

**VNB14NV04, VND14NV04, VND14NV04-1** 

|**Table 6.**<br>**Thermalparameter(continued)**|**Table 6.**<br>**Thermalparameter(continued)**|**Table 6.**<br>**Thermalparameter(continued)**|
|---|---|---|
|**Area/island(cm2)**|**Footprint**|**6**|
|C4 (W.s/°C)|0.45||
|C5 (W.s/°C)|2||
|C6 (W.s/°C)|3|5|



20/25 

**VNB14NV04, VND14NV04, VND14NV04-1** 

**Package information** 

## **5 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[® ] specifications, grade definitions and product status are available at: _www.st.com_ . ECOPACK[®] is an ST trademark. 

**Figure 41. TO-251 (IPAK) mechanical data** 

21/25 

**Package information** 

**VNB14NV04, VND14NV04, VND14NV04-1** 

**Figure 42. D[2] PAK mechanical data** 

22/25 

**VNB14NV04, VND14NV04, VND14NV04-1** 

**Package information** 

**==> picture [209 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 43. TO-252 (DPAK) mechanical data<br>**----- End of picture text -----**<br>


23/25 

**Revision history** 

**VNB14NV04, VND14NV04, VND14NV04-1** 

## **6 Revision history** 

**Table 7. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|21-Jun-2004|6|Initial release.|
|03-Apr-2009|7|Document reformatted.<br>Added_Table 1: Device summary on page 1_.<br>Updated_Section 5: Package information on page 21_|



24/25 

**VNB14NV04, VND14NV04, VND14NV04-1** 

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25/25 



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