# Power MOSFET, N Channel, 42 V, 7 A, 0.14 ohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2849695/)

**URL**: https://novapart.co/products/VND7N04-E/power-mosfet-n-channel-42-v-7-a-014-ohm-to-252
**SKU**: VND7N04-E
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.3720
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | OMNIFET |
| Power Dissipation | 60W |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 60W |
| Rds(On) Test Voltage | 10V |
| On Resistance Rds(On) | 0.14ohm |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 42V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 7A |
| Drain Source On State Resistance | 0.14ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2849695/)

## **VND7N04, VND7N04-1 VNK7N04FM** "OMNIFET": Full auto rotected ower MOSFET y p p 

## **Features** 

|**Features**||||
|---|---|---|---|
|**Type**|**Vclamp**|**RDS(on)**|**Ilim**|
|VND7N04<br>VND7N04-1<br>VNK7N04FM|42 V<br>42 V<br>42 V|0.14Ω<br>0.14Ω<br>0.14Ω|7 A<br>7 A<br>7 A|



- I Linear current limitation 

- I Thermal shut down 

- I Short circuit protection 

- I Integrated clamp 

- I Low current drawn from input pin 

- I Diagnostic feedback through input pin 

- I ESD protection 

- I Direct access to the gate of the power MOSFET (analog driving) 

- I Compatible with standard power MOSFET 

## **Description** 

The VND7N04, VND7N04-1 and VNK7N04FM are monolithic devices made using STMicroeletronics VIPower M0 Technology, intended for replacement of standard power MOSFETS in DC to 50 KHz applications. Built-in thermal shut-down, linear current limitation and overvoltage clamp protect the chip in harsh enviroments. 

Fault feedback can be detected by monitoring the voltage at the input pin. 

**Table 1. Device summary** 

|**Part number**|**Order code**|
|---|---|
|VND7N04|VND7N04, VND7N04-1-E,<br>VND7N04-E, VND7N0413TR,<br>VND7N04TR-E|
|VND7N04-1|VND7N04-1|
|VNK7N04FM|VNK7N04FM|



1/17 

Rev 2 

September 2013 

_www.st.com_ 

|**Contents**|**VND7N04, VND7N04-1, VNK7N04FM**|
|---|---|
|**Contents**||
|**1**|**Block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
||2.2<br>Thermal data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
||2.3<br>Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|**3**|**Protection features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7**|
|**4**|**Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13**|
|**5**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16**|



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**VND7N04, VND7N04-1, VNK7N04FM** 

**Block diagram** 

## **1 Block diagram** 

**==> picture [127 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 1. Block diagram<br>**----- End of picture text -----**<br>


**==> picture [271 x 182] intentionally omitted <==**

3/17 

**Electrical specification** 

**VND7N04, VND7N04-1, VNK7N04FM** 

## **2 Electrical specification** 

## **2.1 Absolute maximum rating** 

## **Table 2. Absolute maximum rating** 

|**Table 2.**|**Absolute maximum rating**||||
|---|---|---|---|---|
|**Symbol**|**Parameter**|**Value**||**Unit**|
|||**DPAK**<br>**IPAK**|**SOT-82FM**||
|VDS|Drain-source voltage (Vin= 0)|Internally clamped||V|
|Vin|Input voltage|18||V|
|ID|Drain current|Internally limited||A|
|IR|Reverse DC output current|-7||A|
|Vesd|Electrostatic discharge (C = 100 pF,<br>R=1.5 KΩ)|2000||V|
|Ptot|Total dissipation at Tc= 25 °C|60|9|W|
|Tj|Operating junction temperature|Internally limited||°C|
|Tc|Case operating temperature|Internally limited||°C|
|Tstg|Storage temperature|-55 to 150||°C|



## **2.2 Thermal data** 

## **Table 3. Thermal data** 

|**Table 3.**|**Thermal data**||||
|---|---|---|---|---|
|||**DPAK/IPAK**|**SOT82-FM**||
|Rthj-case|Thermal resistance junction-case max|3.75|14|°C/W|
|Rthj-amb|Thermal resistance junction-ambient max|100|100|°C/W|



## **2.3 Electrical characteristics** 

## **Table 4. Electrical characteristics: off** 

(-40 < Tj < 125 °C unless otherwise specified) 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VCLAMP<br>|Drain-source clamp voltage|ID= 200 mA Vin= 0|32|42|52|V|
|VCLTH<br>|Drain-source clamp threshold voltage|ID= 2 mA Vin= 0|31|||V|
|VINCL<br>|Input-source reverse clamp voltage|Iin= -1 mA|-1.1||-0.25|V|
|IDSS<br>|Zero input voltage drain current (Vin= 0)|VDS= 13 V Vin= 0<br>VDS= 25 V Vin= 0|||75<br>200|µA<br>µA|
|IISS<br>|Supply current from input pin|VDS= 0 V Vin= 10 V||250|550|µA|



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**VND7N04, VND7N04-1, VNK7N04FM** 

**Electrical specification** 

**Table 5. Electrical characteristics: on** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VIN(th)|Input threshold voltage|VDS= VinID+ Iin= 1 mA|0.8||3|V|
|RDS(on)|Static drain-source on resistance|Vin= 10 V ID= 3.5 A<br>Vin= 5 V ID= 3.5 A<br>-40 < Tj< 25 °C<br>Vin= 10 V ID= 3.5 A<br>Vin= 5 V ID= 3.5 A<br>Tj= 125 °C|||0.14<br>0.28<br>0.28<br>0.56|Ω<br>Ω<br>Ω<br>Ω|



## **Table 6. Electrical characteristics: dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|gfs (1)|Forward<br>transconductance|VDS= 13 V ID= 3.5 A|2|5||S|
|Coss|Output capacitance|VDS= 13 V f = 1 MHz Vin= 0||250|500|pF|



1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 

## **Table 7. Electrical characteristics: switching** 

|**Symbol**|**Parameter**|**Test conditions**|**Test conditions**|**Min.**|**Min.**|**Typ.**|**Typ.**|**Max.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|---|---|---|---|
|td(on)<br>tr<br>td(off)<br>tf|Turn-on delay time<br>Rise time<br>Turn-off delay time<br>Fall time|VDD= 15 V Id= 3.5 A<br>Vgen= 10 V Rgen= 10Ω<br>(see_Figure 26_)||||50<br>60<br>130<br>50||150<br>180<br>300<br>200||ns<br>ns<br>ns<br>ns|
|td(on)<br>tr<br>td(off)<br>tf|Turn-on delay time<br>Rise time<br>Turn-off delay time<br>Fall time|VDD= 15 V Id= 3.5 A<br>Vgen= 10 V Rgen= 1000Ω<br>(see_Figure 26_)||||140<br>0.4<br>2.5<br>1||500<br>1.1<br>7<br>4||ns<br>µs<br>µs<br>µs|
|(di/dt)on|Turn-on current slope|VDD= 15 V ID= 3.5 A<br>Vin= 10 V Rgen= 10Ω||||50||||A/µs|
|Qi|Total input charge|VDD= 12 V ID= 3.5 A Vin= 10 V||||18||||nC|
|**Table 8.**<br>**Electrical characteristics: source drain diode**|||||||||||
|**Symbol**|**Parameter**||**Test conditions**||**Min.**||**Typ.**||**Max.**|**Unit**|
|VSD (1)|Forward on voltage||ISD= 3.5 A Vin= 0||||||1.7|V|
|trr (2)<br>Qrr (2)<br>IRRM<br>(2)|Reverse recovery time<br>Reverse recovery charge<br>Reverse recovery current||ISD= 3.5 A di/dt = 100 A/µs<br>VDD= 30 V Tj= 25 °C<br>(see test circuit,_Figure 28_)||||40<br>0.2<br>3.6|||ns<br>µC<br>A|



|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VSD (1)|Forward on voltage|ISD= 3.5 A Vin= 0|||1.7|V|
|trr (2)|Reverse recovery time|ISD= 3.5 A di/dt = 100 A/µs||40||ns|
|Qrr (2)|Reverse recovery charge|VDD= 30 V Tj= 25 °C||0.2||µC|
|IRRM<br>(2)|Reverse recovery current|(see test circuit,_Figure 28_)||3.6||A|



1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 

2. Parameters guaranteed by design/characterization 

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**Electrical specification** 

**VND7N04, VND7N04-1, VNK7N04FM** 

## **Table 9. Electrical characteristics: protection** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ilim|Drain current limit|Vin= 10 V VDS= 13 V<br>Vin= 5 V VDS= 13 V|4<br>4|7<br>7|11<br>11|A<br>A|
|tdlim<br>(1)|Step response<br>Current limit|Vin= 10 V<br>Vin= 5 V||13<br>15|20<br>25|µs<br>µs|
|Tjsh<br>(1)|Overtemperature<br>shutdown||150|||°C|
|Tjrs<br>(1)|Overtemperature reset||135|||°C|
|Igf<br>(1)|Fault sink current|Vin= 10 V VDS= 13 V<br>Vin= 5 V VDS= 13 V||50<br>20||mA<br>mA|
|Eas (1)|Single pulse avalanche<br>energy|starting Tj= 25°C VDD= 20 V<br>Vin= 10 V Rgen= 1 KΩL = 30 mH|0.4|||J|



1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 

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**VND7N04, VND7N04-1, VNK7N04FM** 

**Protection features** 

## **3 Protection features** 

During normal operation, the Input pin is electrically connected to the gate of the internal power MOSFET. The device then behaves like a standard power MOSFET and can be used as a switch from DC to 50 KHz. The only difference from the user’s standpoint is that a small DC current (Iiss) flows into the Input pin in order to supply the internal circuitry. 

The device integrates: 

- G Overvoltage clamp protection: internally set at 42 V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. 

- G Linear current limiter circuit: limits the drain current Id to Ilim whatever the Input pin voltage. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold Tjsh. 

- G Overtemperature and short circuit protection: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs at minimum 150 °C. The device is automatically restarted when the chip temperature falls below 135 °C. 

- G Status feedback: in the case of an overtemperature fault condition, a Status Feedback is provided through the Input pin. The internal protection circuit disconnects the input from the gate and connects it instead to ground via an equivalent resistance of 100 Ω. The failure can be detected by monitoring the voltage at the Input pin, which will be close to ground potential. 

Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit (with a small increase in RDS(on)). 

7/17 

**Protection features** 

**VND7N04, VND7N04-1, VNK7N04FM** 

## **Figure 2. Thermal impedance for DPAK / IPAK** 

**==> picture [156 x 158] intentionally omitted <==**

## **Figure 4. Output characteristics** 

**==> picture [155 x 149] intentionally omitted <==**

**Figure 6. Static drain-source on resistance vs input voltage** 

**==> picture [171 x 158] intentionally omitted <==**

## **Figure 3. Derating curve** 

**==> picture [163 x 159] intentionally omitted <==**

**Figure 5. Transconductance** 

**==> picture [155 x 146] intentionally omitted <==**

**Figure 7. Static drain-source on resistance (part 1/2)** 

**==> picture [171 x 158] intentionally omitted <==**

8/17 

**VND7N04, VND7N04-1, VNK7N04FM** 

**Protection features** 

**Figure 8. Static drain-source on resistance (part 2/2)** 

**==> picture [169 x 158] intentionally omitted <==**

**Figure 10. Capacitance variations** 

**==> picture [163 x 151] intentionally omitted <==**

**Figure 12. Normalized on resistance vs temperature (part 1/2)** 

**==> picture [172 x 157] intentionally omitted <==**

**Figure 9. Input charge vs input voltage** 

**==> picture [176 x 158] intentionally omitted <==**

**Figure 11. Normalized input threshold voltage vs temperature** 

**==> picture [163 x 149] intentionally omitted <==**

**Figure 13. Normalized on resistance vs temperature (part 2/2)** 

**==> picture [172 x 158] intentionally omitted <==**

9/17 

**Protection features** 

**VND7N04, VND7N04-1, VNK7N04FM** 

## **Figure 14. Turn-on current slope(part 1/2)** 

**==> picture [176 x 157] intentionally omitted <==**

## **Figure 15. Turn-on current slope(part 2/2)** 

**==> picture [171 x 153] intentionally omitted <==**

**Figure 16. Turn-off drain-source voltage slope Figure 17. Turn-off drain-source voltage slope (part 1/2) (part 2/2)** 

**==> picture [163 x 148] intentionally omitted <==**

**Figure 18. Switching time resistive load (part 1/3)** 

**==> picture [163 x 147] intentionally omitted <==**

**Figure 19. Switching time resistive load (part 2/3)** 

**==> picture [163 x 156] intentionally omitted <==**

**==> picture [163 x 154] intentionally omitted <==**

10/17 

**VND7N04, VND7N04-1, VNK7N04FM** 

**Protection features** 

**Figure 20. Switching time resistive load (part Figure 21. Current limit vs junction 3/3) temperature** 

**==> picture [163 x 155] intentionally omitted <==**

**Figure 22. Step response current limit** 

**==> picture [163 x 153] intentionally omitted <==**

**Figure 23. Source drain diode forward characteristics** 

**==> picture [160 x 148] intentionally omitted <==**

**==> picture [159 x 149] intentionally omitted <==**

11/17 

**Protection features** 

**VND7N04, VND7N04-1, VNK7N04FM** 

**Figure 24. Unclamped inductive load test Figure 25. Unclamped inductive waveforms circuits** 

**==> picture [217 x 149] intentionally omitted <==**

**==> picture [193 x 159] intentionally omitted <==**

**Figure 26. Switching times test circuits for Figure 27. Input charge test circuit resistive load** 

**==> picture [451 x 131] intentionally omitted <==**

**Figure 28. Test circuit for inductive load Figure 29. Waveforms switching and diode recovery times** 

**==> picture [209 x 113] intentionally omitted <==**

**==> picture [208 x 103] intentionally omitted <==**

12/17 

**VND7N04, VND7N04-1, VNK7N04FM** 

**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _www.st.com_ . ECOPACK[®] is an ST trademark. 

**Figure 30. TO-252 (DPAK) mechanical data** 

13/17 

**Package information** 

**VND7N04, VND7N04-1, VNK7N04FM** 

**Figure 31. TO-251 (IPAK) mechanical data** 

14/17 

**VND7N04, VND7N04-1, VNK7N04FM** 

**Package information** 

**Figure 32. SOT-82FM mechanical data** 

15/17 

**Revision history** 

**VND7N04, VND7N04-1, VNK7N04FM** 

## **5 Revision history** 

**Table 10. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|21-Jun-2004|0.1|Initial release.|
|18-Mar-2009|1|Document reformatted.<br>Added_Table 1: Device summary on page 1_.<br>Updated_Section 4: Package information on page 13_|



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**VND7N04, VND7N04-1, VNK7N04FM** 

**Revision history** 

## **5 Revision history** 

**Table 10. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|21-Jun-2004|1|Initial release.|
|25-Sep-2013|2|Updated Disclaimer|



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**VND7N04, VND7N04-1, VNK7N04FM** 

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## Links

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