# DMOSFET, N-CH, 0.23A, 120V, TO-92
**URL**: https://novapart.co/products/VN1206L-G/dmosfet-n-ch-023a-120v-to-92
**SKU**: VN1206L-G
**Manufacturer**: MICROCHIP
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.4200
**Stock**: 500+
**Lead Time**: 72 days (indicative)
## Description
Channel Type:N Channel; Drain Source Voltage Vds:120V; Continuous Drain Current Id:230mA; Transistor Mounting:Through Hole; Rds(on) Test Voltage:10V; Gate Source Thr 53Y4318
## Specifications
| Parameter | Value |
|---|---|
| Svhc | No SVHC (04-Feb-2026) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 1W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-92 |
| Drain Source Voltage Vds | 120V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 230mA |
| Drain Source On State Resistance | 6ohm |
| Gate Source Threshold Voltage Max | 2V |
## Datasheet
📄 [Download PDF](https://novapart.co/datasheet/farnell:3579964/)
- _**Supertex inc.**_ **VN1206 N-Channel Enhancement-Mode**
- ~~—~~ **Vertical DMOS FET Features General Description** ► Free from secondary breakdown This enhancement-mode (normally-off) transistor utilizes
This enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown.
- Low power drive requirement
- Ease of paralleling
- Low CISS and fast switching speeds
- Excellent thermal stability
- Integral source-drain diode
- High input impedance and high gain
## **Applications**
- Motor controls
Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.
- Converters
- Amplifiers
- Switches
- Power supply circuits
► Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) **Ordering Information Product Summary Part Number Package Option Packing BV /BV RDS(ON) IDSS DSS DGS** VN1206L-G TO-92 1000/Bag **(max) (min)** VN1206L-G P002 120V 6.0Ω 1.0A VN1206L-G P003 VN1206L-G P005 TO-92 2000/Reel **Pin Configuration** VN1206L-G P013 VN1206L-G P014 _-G denotes a lead (Pb)-free / RoHS compliant package._ ~~=~~ _Contact factory for Wafer / Die availablity._ ~~Tl.~~ **DRAIN** _Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant._ **SOURCE Absolute Maximum Ratings Parameter Value GATE** Drain-to-source voltage BVDSS **TO-92** Drain-to-gate voltage BVDGS Gate-to-source voltage ±30V **Product Marking** Operating and storage temperature -55[O] C to +150[O] C **Si VN** _Absolute Maximum Ratings are those values beyond which damage to the device may_ YY = Year Sealed _occur. Functional operation under these conditions is not implied. Continuous operation_ **1 2 0 6 L** WW = Week Sealed _of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground._ ~~——=-~~ **YYWW** = “Green” Packaging _Package may or may not include the following marks: Si or_ **Typical Thermal Resistance TO-92 Package** _**θja**_ TO-92 132[O] C/W ~~—~~ _Doc.# DSFP-VN1206 B081913_ ~~i~~ _**Supertex inc.www.supertex.com**_
**VN1206**
## **Thermal Characteristics**
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Package (continuous)ID [†] (pulsed)ID Power Dissipation@TC = 25 [O] C IDR † IDRM
TO-92 230mA 2.0A 1.0W 230mA 2.0A
**----- End of picture text -----**
_**Notes:**_
_† ID (continuous) is limited by max rated Tj ._
## **Electrical Characteristics** _(TA = 25[O] C unless otherwise specified)_
**==> picture [542 x 335] intentionally omitted <==**
**----- Start of picture text -----**
Sym Parameter Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage 120 - - V VGS = 0V, ID = 100µA
VGS(th) Gate threshold voltage 0.8 - 2.0 V VGS = VDS, ID = 1.0mA
IGSS Gate body leakage - - 100 nA VGS = ±15V, VDS = 0V
- - 10 VGS = 0V, VDS = Max Rating
IDSS Zero gate voltage drain current - - 500 µA VDS = 0.8Max Rating,
VGS = 0V, TA = 125°C
ID(ON) On-state drain current 1.0 - - A VGS = 10V, VDS = 10V
R Static drain-to-source on-state resistance - - 10 Ω VGS = 2.5V, ID = 100mA
DS(ON) - - 6.0 VGS = 10V, ID = 500mA
GFS Forward transductance 300 - - mmho VDS = 10V, ID = 500mA
CISS Input capacitance - - 125 VGS = 0V,
COSS Common source output capacitance - - 50 pF VDS = 25V,
CRSS Reverse transfer capacitance - - 20 f = 1.0MHz
t Rise time - - 8.0
r
td(ON) Turn-on delay time - - 8.0 VDD = 60V,
ns ID = 400mA,
tf Fall time - - 12 RGEN = 25Ω
td(OFF) Turn-off delay time - - 18
VSD Diode forward voltage drop - 1.2 - V VGS = 0V, ISD = 250mA
**----- End of picture text -----**
_**Notes:**_
_1. All D.C. parameters 100% tested at 25[O] C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)_
_2. All A.C. parameters sample tested._
## **Switching Waveforms and Test Circuit**
**==> picture [490 x 127] intentionally omitted <==**
**----- Start of picture text -----**
10V 90% VDD
INPUT Pulse R
10% Generator L
0V OUTPUT
t t
(ON) (OFF) R
GEN
td(ON) tr td(OFF) tf
VDD INPUT D.U.T.
10% 10%
OUTPUT
0V 90% 90%
**----- End of picture text -----**
_**Supertex inc.**_
_Doc.# DSFP-VN1206 B081913_
2
_**www.supertex.com**_
**VN1206**
## **3-Lead TO-92 Package Outline (L)**
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D
A
Seating
Plane 1 2 3
L
b c
e1
e
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Front View
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**----- Start of picture text -----**
Side View
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**----- Start of picture text -----**
E
E1
1 3
2
Bottom View
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Symbol A b c D E E1 e e1 L
MIN .170 .014 [†] .014 [†] .175 .125 .080 .095 .045 .500
Dimensions
NOM - - - - - - - - -
(inches)
MAX .210 .022 [†] .022 [†] .205 .165 .105 .105 .055 .610*
**----- End of picture text -----**
- _JEDEC Registration TO-92. * This dimension is not specified in the JEDEC drawing._
_† This dimension differs from the JEDEC drawing._
_**Drawings not to scale.**_
_**Supertex Doc.#:** DSPD-3TO92N3, Version E041009._
_(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)_
_**Supertex inc.**_ does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” _**Supertex inc.**_ does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the _**Supertex inc.**_ (website: http//www.supertex.com)
> ©2013 _**Supertex inc.**_ All rights reserved. Unauthorized use or reproduction is prohibited.
_**Supertex inc.**_ 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 _**www.supertex.com**_
_Doc.# DSFP-VN1206 B081913_
3
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