# EMI Filter, 2-Channel, USB Upstream Terminator, ESD Protection, SOT-323-6

![Product image](https://novapart.co/image/farnell:2341659/)

**URL**: https://novapart.co/products/USBUF02W6/emi-filter-2-channel-usb-upstream-terminator-esd
**SKU**: USBUF02W6
**Manufacturer**: STMICROELECTRONICS
**Category**: Passive Components || Filters || Integrated Passive Filters
**Price**: €0.1440
**Stock**: 10+
**Lead Time**: 127 days (indicative)

## Description

EMI Filter Type:USB Upstream and Terminator EMI Filter with ESD; No. of Data Lines:2 Data Lines; Filter Circuit:RC Pi Filter; Filter Case Style:SOT323; No. of Pins:6Pins; Product Range:

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 6Pins |
| Product Range | - |
| Filter Circuit | RC Pi Filter |
| Emi Filter Type | USB Upstream and Terminator EMI Filter with ESD |
| No. Of Data Lines | 2 Data Lines |
| Filter Case / Package | SOT323 |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2341659/)

## **USBUF** 

## EMI filter and line termination for USB upstream ports 

**Datasheet** - **production data** 

- Complies with the following standards IEC 61000-4-2, level 4 

   - ± 15 kV (air discharge) 

   - ± 8 kV (contact discharge) 

   - MIL STD 883E, Method 3015-7 

**==> picture [53 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOT323-6L<br>**----- End of picture text -----**<br>


- Class 3 C = 100 pF; R = 1500 Ω 

- 3 positive strikes and 3 negative strikes (F = 1 Hz) 

**Figure 1. Functional diagram** 

**==> picture [166 x 131] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.3 V<br>Rt Rp<br>D1 D4<br>Ct<br>cheb<br>Grd 3.3 V<br>Rt<br>D2 1 ¢ D3<br>he<br>Ct<br>**----- End of picture text -----**<br>


## **Features** 

- Monolithic device with recommended line termination for USB upstream ports 

- Integrated Rt series termination and Ct bypassing capacitors. 

- Integrated ESD protection 

- Small package size 

- Benefits 

   - EMI / RFI noise suppression 

   - Required line termination for USB upstream ports 

   - ESD protection exceeding IEC 61000-4-2 level 4 

   - High flexibility in the design of high density boards 

## **Application** 

EMI Filter and line termination for USB upstream ports on: 

- USB Hubs 

- PC peripherals 

## **Description** 

The USB specification requires upstream ports to be terminated with pull-up resistors from the D+ and D- lines to Vbus. On the implementation of USB systems, the radiated and conducted EMI should be kept within the required levels as stated by the FCC regulations. In addition to the requirements of termination and EMC compatibility, the computing devices are required to be tested for ESD susceptibility. 

The USBUF provides the recommended line termination while implementing a low pass filter to limit EMI levels and providing ESD protection which exceeds IEC 61000-4-2 level 4 standard. The device is packaged in a SOT323-6L which is the smallest available lead frame package (50% smaller than the standard SOT23). 

**Table 1. Device summary** 

|**Order codes**|**Marking**|
|---|---|
|USBUF01W6|UU1|
|USBUF02W6|UU2|



- Tailored to meet USB 1.1 standard 

August 2015 

DocID7041 Rev 8 

1/13 

This is information on a product in full production. 

_www.st.com_ 

**Characteristics** 

**USBUF** 

## **1 Characteristics** 

**Table 2. Absolute ratings (Tamb = 25° C)** 

||**Table 2. Absolute ratings (Tamb = 25°**|**C)**||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|VPP|ESD discharge IEC 61000-4-2, air discharge<br>ESD discharge IEC 61000-4-2, contact discharge<br>ESD discharge - MIL STD 883E - Method 3015-7|± 16<br>± 9<br>± 25|kV|
|Tj|Maximum junction temperature|150|°C|
|Tstg|Storage temperature range|- 55 to + 150|°C|
|TL|Lead solder temperature (10 second duration)|260|°C|
|Top|Operating temperature range|-40 to 125|°C|
|P|Power rating per resistor|100|mW|



**Table 3. Functional diagram** 

||**Rt**|**Rp**|**Ct**|
|---|---|---|---|
|CODE 01|33 W|1.5 kΩ|47 pF|
|CODE 02|22 W|1.5 kΩ|47 pF|
|Tolerance|± 10%|± 10%|± 20%|



2/13 

DocID7041 Rev 8 

**USBUF** 

**Technical information** 

## **2 Technical information** 

## **Figure 2. USB standard requirements** 

**==> picture [397 x 234] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.3V<br>1.5k<br>Rt D+ D+ Rt<br>Full-speed or<br>Ct Ct Full-speed USB<br>Low-speed USBTransceiver Rt Twisted pair shielded Rt Transceiver<br>D- Zo = 90ohms D-<br>Ct 15k 15k 5m max Ct<br>Host or Hub 0 or<br>Hub port Full-speed function<br>FULL SPEED CONNECTION<br>3.3V<br>1.5k<br>Rt D+ D+ Rt<br>Full-speed or<br>Ct Ct Low-speed USB<br>Low-speed USBTransceiver Rt Untwisted unshielded Rt Transceiver<br>D- 3m max D-<br>Host or Ct 15k 15k Ct Hub 0 or<br>Hub port Low-speed function<br>LOW SPEED CONNECTION<br>**----- End of picture text -----**<br>


DocID7041 Rev 8 

3/13 

**USBUF** 

**Technical information** 

## **2.1 Application example** 

## **Figure 3. Implementation of ST solutions for USB ports** 

**==> picture [398 x 310] intentionally omitted <==**

**----- Start of picture text -----**<br>
USBUF01W6<br>Downstream port USBDF01W5 Upstream port<br>D2 Gnd D1 D+<br>D+ Rt<br>CABLE<br>D+ in Ct Rd D+ out D+ D+<br>Gnd Ct Ct<br>Rt Rt<br>Gnd 3.3 V<br>Ct Rd D- D- Rp<br>D-<br>D- in Rt D- out D3 3.3V D4 D-<br>FULL SPEED CONNECTION<br>USBUF01W6<br>Downstream port USBDF01W5 Upstream port<br>D+<br>D2 Gnd D1<br>D+ Rt<br>CABLE<br>D+ in Ct Rd D+ out D+ D+<br>Gnd Ct Ct<br>Rt Rt<br>Gnd 3.3 V<br>Ct Rd D- D- Rp<br>D-<br>D- in Rt D- out D3 3.3V D4 D-<br>LOW SPEED CONNECTION<br>Peripheral  transceiver<br>Host/Hub USB por transceivert<br>Peripheral  transceiver<br>Host/Hub USB por transceivert<br>**----- End of picture text -----**<br>


## **2.2 EMI filtering** 

Current FCC regulations requires that class B computing devices meet specified maximum levels for both radiated and conducted EMI. 

- Radiated EMI covers the frequency range from 30 MHz to 1 GHz. 

- Conducted EMI covers the 450 kHz to 30 MHz range. 

For the types of devices utilizing the USB, the most difficult test to pass is usually the radiated EMI test. For this reason the USBUF device is aiming to minimize radiated EMI. 

The differential signal (D+ and D-) of the USB does not contribute significantly to radiated or conducted EMI because the magnetic field of both conductors cancels each other. 

The inside of the PC environment is very noisy and designers must minimize noise coupling from the different sources. D+ and D-must not be routed near high speed lines (clocks spikes). 

Induced common mode noise can be minimized by running pairs of USB signals parallel to each other and running grounded guard trace on each side of the signal pair from the USB controller to the USBUF device. If possible, locate the USBUF device physically near the 

4/13 

DocID7041 Rev 8 

**USBUF** 

**Technical information** 

USB connectors. Distance between the USB controller and the USB connector must be minimized. 

The 47 pF (Ct) capacitors are used to bypass high frequency energy to ground and for edge control, and are placed between the driver chip and the series termination resistors (Rt). Both Ct and Rt should be placed as close to the driver chip as is practicable. 

The USBUF ensures a filtering protection against Electromagnetic and Radio-frequency Interferences thanks to its low-pass filter structure. This filter is characterized by the following parameters: 

- cut-off frequency 

- Insertion loss 

- high frequency rejection. 

**==> picture [404 x 158] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 4. USBUF typical attenuation Figure 5. Measurement configuration<br>S21 (dB)<br>0<br>-10 50 Ω TEST BOARD<br>-20 Vg 50 Ω<br>-30<br>1 10 100 1,000<br>Frequency (MHz)<br>UUx<br>**----- End of picture text -----**<br>


## **2.3 ESD protection** 

In addition to the requirements of termination and EMC compatibility, computing devices are required to be tested for ESD susceptibility. This test is described in the IEC 61000-4-2 and is already in place in Europe. This test requires that a device tolerates ESD events and remains operational without user intervention. 

The USBUF is particularly optimized to perform ESD protection. ESD protection is based on the use of device which clamps at: 

Vcl = VBR + Rd . IPP 

This protection function is spitted in 2 stages. As shown in _Figure 6_ , the ESD strikes are clamped by the first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor Rt. Such a configuration makes the output voltage very low at the output. 

DocID7041 Rev 8 

5/13 

**USBUF** 

**Technical information** 

## **Figure 6. USBUF ESD clamping behavior** 

**==> picture [314 x 84] intentionally omitted <==**

**----- Start of picture text -----**<br>
Rg S1 Rt S2<br>Rd Rd<br>Vinput Rload<br>VPP VBR Voutput VBR<br>Device<br>to be<br>ESD Surge USBUF01W6 protected<br>**----- End of picture text -----**<br>


## **Figure 7. Measurement board** 

**==> picture [163 x 109] intentionally omitted <==**

**----- Start of picture text -----**<br>
ESD<br>TEST BOARD<br>SURGE<br>16kV<br>Air<br>Discharge Vin Vout<br>UUx<br>**----- End of picture text -----**<br>


To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical dynamical resistance value Rd. By taking into account these following hypothesis: Rt > Rd, Rg > Rd and Rload > Rd, it gives these formulas: 

**==> picture [114 x 25] intentionally omitted <==**

**==> picture [129 x 23] intentionally omitted <==**

The results of the calculation done for Vg = 8 kV, Rg = 330 Ω (IEC 61000-4-2 standard), VBR = 7 V (typ.) and Rd = 1 Ω (typ.) give: 

Vinput = 31.2 V 

Voutput = 7.95 V 

This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the Vinput side. This parasitic effect is not present at the Voutput side due the low current involved after the resistance Rt. 

The measurements done hereafter show very clearly (figure 8) the high efficiency of the ESD protection: 

- no influence of the parasitic inductances on Voutput stage 

- Voutput clamping voltage very close to VBR (breakdown voltage) in the positive way and - VF (forward voltage) in the negative way 

6/13 

DocID7041 Rev 8 

**USBUF** 

**Technical information** 

**Figure 8. Remaining voltage at both stages S1 (Vinput) and S2 (Voutput) during ESD surge** 

**==> picture [285 x 107] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vin<br>PPP) ee e<br>Vin<br>CE E) feE E<br>HEPEEPEPER,’ 2 Cece Vout<br>Vout<br>TTA SURREseeen:<br>ee eos a<br>CPT EET TT SeGeesnnee<br>Positive surge Negative surge<br>**----- End of picture text -----**<br>


Please note that the USBUF is not only acting for positive ESD surges but also for negative ones. For these kinds of disturbances it clamps close to ground voltage as shown in _Figure 8._ (negative surge. 

## **2.4 Latch-up phenomenon** 

The early aging and destruction of IC’s is often due to latch-up phenomenon which is mainly induced by dV/dt. Thanks to its structure, the USBUF provides a high immunity to latch-up phenomenon by smoothing very fast edges. 

## **2.5 Crosstalk behavior** 

**==> picture [312 x 135] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 9. Crosstalk phenomenon<br>RG1<br>Line 1<br>VG1 RL1 α 1 VG1 + β 1  2VG2<br>RG2 Line 2<br>VG2 RL2 α 2 VG2 + β 2  1VG1<br>DRIVERS RECEIVERS<br>**----- End of picture text -----**<br>


The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor ( β 12 or β 21) increases when the gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load RL2 is α 2VG2, in fact the real voltage at this point has got an extra value β 21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few k Ω ). 

DocID7041 Rev 8 7/13 ~~CS7~~ 

DocID7041 Rev 8 7/13 

**USBUF** 

**Technical information** 

**==> picture [384 x 154] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 10. Analog crosstalk  Figure 11. Typical analog crosstalk<br>measurements results<br>Analog crosstalk (dB)<br>0<br>TEST BOARD -20<br>50 Ω<br>UUx -40<br>Vg 50 Ω -60<br>-80<br>7 a7 -100 pee<br>1 10 100 1,000<br>Frequency (MHz)<br>**----- End of picture text -----**<br>


_Figure 10._ gives the measurement circuit for the analog crosstalk application. In _Figure 11._ , the curve shows the effect of the D+ cell on the D-cell. In usual frequency range of analog signals (up to 100 MHz) the effect on disturbed line is less than -37 db. 

**Figure 12. Digital crosstalk measurements configuration** 

**==> picture [225 x 96] intentionally omitted <==**

**----- Start of picture text -----**<br>
+5V +5V<br>74HC04 74HC04<br>J 3.3 V L<br>D+ Rt Rp<br>D1 Ct D4<br>Square VG1 Soh pe<br>Pulse +5V Gnd 3.3 V<br>Generator D- Rt<br>D2 Ct D3<br>OTE<br>v β 21 VG1 ca Vv<br>**----- End of picture text -----**<br>


_Figure 12_ shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. 

**Figure 13. Digital crosstalk results** 

**==> picture [28 x 45] intentionally omitted <==**

**----- Start of picture text -----**<br>
VG1<br>β 21VG1<br>**----- End of picture text -----**<br>


_Figure 13_ shows, with a signal from 0 to 5 V and rise time of few ns, the impact on the disturbed line is less than 250 mV peak to peak. No data disturbance was noted on the other line.The measurements performed with falling edges gives an impact within the same range. 

8/13 

DocID7041 Rev 8 

**USBUF** 

**Technical information** 

## **2.6 Transition times** 

This low pass filter has been designed in order to meet the USB 1.1 standard requirements that implies the signal edges are maintained within the 4 -20 ns stipulated USB specification limits. To verify this point, we have measured the rise time of VD+ voltage with and without the USBUF device. 

**==> picture [385 x 123] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 14. Typical rise and fall times:  Figure 15. Typical rise times with and<br>measurement configuration without protection device<br>+5V +5V without<br>74HC04 ; ; 74HC04 TT<br>D+<br>USBDF D e n —<br>+5V 01W6<br>Square n f  | feeGALLE<br>Pulse D-<br>Generator SECT<br>: ; Ce with ET ere<br>**----- End of picture text -----**<br>


_Figure 14._ shows the circuit used to perform measurements of the transition times. In _Figure 15._ , we see the results of such measurements: 

trise = 3.8 ns driver alone 

trise = 7.8 ns with protection device 

The adding of the protection device causes the rise time increase of roughly 4ns. 

_Note: Rise time has been measured between 10% and 90% of the signal (resp. 90% and 10%)_ 

DocID7041 Rev 8 9/13 ~~CS7~~ 

**USBUF** 

**Packaging information** 

## **3 Packaging information** 

**Table 4. SOT323-6L Package mechanical data** 

**==> picture [405 x 251] intentionally omitted <==**

**----- Start of picture text -----**<br>
DIMENSIONS<br>REF.<br>Millimeters Inches<br>A<br>E Min. Max. Min. Max.<br>A 0.8 1.1 0.031 0.043<br>e A1 0 0.1 0 0.004<br>b D A2 0.8 1 0.031 0.039<br>e<br>b 0.15 0.3 0.006 0.012<br>A1 c 0.1 0.18 0.004 0.007<br>A2 D 1.8 2.2 0.071 0.086<br>Q1 E 1.15 1.35 0.045 0.053<br>e 0.65 Typ. 0.025 Typ.<br>c<br>L HE 1.8 2.4 0.071 0.094<br>HE<br>L 0.1 0.4 0.004 0.016<br>Q1 0.1 0.4 0.004 0.016<br>**----- End of picture text -----**<br>


## **Figure 16. Recommended footprint (dimensions in mm)** 

**==> picture [118 x 130] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.65<br>1.05<br>0.80 2.9<br>1.05<br>0.40<br>**----- End of picture text -----**<br>


10/13 

DocID7041 Rev 8 

**USBUF** 

**Packaging information** 

**Table 5. Mechanical specifications** 

|**Lead**|**Description**|
|---|---|
|Lead plating|Tin-lead|
|Lead plating thickness|5 m min<br>25 m max|
|Lead material|Sn / Pb<br>(70% to 90%Sn)|
|Lead coplanarity|10 m max|
|Body material|Molded epoxy|
|Flammability|UL94V-0|



DocID7041 Rev 8 

11/13 

**Ordering information** 

**USBUF** 

## **4 Ordering information** 

**Table 6. Order code** 

|**Order code**|**Marking**|**Package**|**Weight**|**Base qty**|**Delivery mode**|
|---|---|---|---|---|---|
|USBUF01W6|UU1|SOT323-6L|5.4 mg|3000|Tape and reel|
|USBUF02W6|UU2|SOT323-6L|5.4 mg|3000|Tape and reel|



## **5 Revision history** 

**Table 7. Document revision history** 

|**Date**|**Revision**|**Description of Changes**|
|---|---|---|
|Mar-2002|3A|Last update.|
|Feb-2005|4|Layout update. No content change.|
|28-Feb-2006|5|Operating temperature range updated to -40 to 70° C.<br>Layout updated to current standard.|
|27-May-2009|6|Reformatted to the current standard.|
|14-Jan-2014|7|Updated_Section 3: Packaging information_|
|24-Aug-2015|8|Updated Topparameter in_Table 2_.<br>Minor text changes.|



12/13 

DocID7041 Rev 8 

**USBUF** 

## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2015 STMicroelectronics – All rights reserved 

DocID7041 Rev 8 

13/13 



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- [Supplier page](https://es.farnell.com/stmicroelectronics/usbuf02w6/filter-low-pass-1ghz-sot-323-6/dp/2341659)
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