# EMI Filter, 2-Channel, USB Downstream Terminator, ESD Protection, SOT-323-5

![Product image](https://novapart.co/image/farnell:2341665/)

**URL**: https://novapart.co/products/USBDF01W5/emi-filter-2-channel-usb-downstream-terminator-esd
**SKU**: USBDF01W5
**Manufacturer**: STMICROELECTRONICS
**Category**: Passive Components || Filters || Integrated Passive Filters
**Price**: €0.1410
**Stock**: 100+
**Lead Time**: 127 days (indicative)

## Description

EMI Filter Type:USB Downstream and Terminator EMI Filter with ESD; No. of Data Lines:2 Data Lines; Filter Circuit:C-R-C Pi Filter; Filter Case Style:SOT323; No. of Pins:5Pins; Product R

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 5Pins |
| Product Range | - |
| Filter Circuit | C-R-C Pi Filter |
| Emi Filter Type | USB Downstream and Terminator EMI Filter with ESD |
| No. Of Data Lines | 2 Data Lines |
| Filter Case / Package | SOT323 |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2341665/)

**USBDFxxW5** 

EMI filter and line termination for USB downstream ports 

**==> picture [61 x 39] intentionally omitted <==**

## **Applications** 

EMI Filter and line termination for USB downstream ports on: 

- Desktop computer 

- Notebooks 

- Workstations 

- USB Hubs 

## **Features** 

- Monolithic device with recommended line termination for USB downstream ports 

- Integrated Rt series termination and Ct bypassing capacitors. 

- Integrated ESD protection 

- Small package size 

## **Description** 

The USB specification requires USB downstream ports to be terminated with pull-down resistors from the D+ and D- lines to ground. On the implementation of USB systems, the radiated and conducted EMI should be kept within the required levels as stated by the FCC regulations. In addition to the requirements of termination and EMC compatibility, the computing devices are required to be tested for ESD susceptibility. 

The USBDFxxW5 provides the recommended line termination while implementing a low pass filter to limit EMI levels and providing ESD protection which exceeds IEC 61000-4-2 level 4 standard. The device is packaged in a SOT323-5L, which is a very small (50% smaller than the standard SOT23). 

## **Complies with the following standards** 

IEC 61000-4-2, level 4 ±15 kV (air discharge) 

±8 kV   (contact discharge) 

MIL STD 883C, Method 3015-6 Class 3   C = 100 pF   R = 1500 W 3 positive strikes and 3 negative strikes (F = 1 Hz) 

**==> picture [58 x 44] intentionally omitted <==**

**==> picture [53 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOT323-5L<br>**----- End of picture text -----**<br>


## **Functional diagram** 

|D+ In<br>D- In<br>Gnd|D+ In<br>D- In<br>Gnd|D+ Out<br>D- Out<br>Rt<br>Rd<br>Ct<br>Rt<br>Ct<br>Rd|D+ Out<br>D- Out<br>Rt<br>Rd<br>Ct<br>Rt<br>Ct<br>Rd|D+ Out<br>D- Out<br>Rt<br>Rd<br>Ct<br>Rt<br>Ct<br>Rd|
|---|---|---|---|---|
|||Rt|Rd|Ct|
|USBDF01W5||33Ω|15 kΩ|47 pF|
|USBDF02W5||15Ω|15 kΩ|47 pF|
|Tolerance||±10%|±10%|±20%|



## **Order codes** 

|**Order codes**||
|---|---|
|**Part number**|**Marking**|
|USBDF01W5|UD1|
|USBDF02W5|UD2|



## **Benefits** 

- EMI / RFI noise suppression 

- Required line termination for USB downstream ports 

- ESD protection exceeding IEC61000-4-2 level 4 

- IPAD™ technology provides high flexibility in the design of high density boards 

- Tailored to meet USB 1.1 standard 

TM: IPAD is a trademark of STMicroelectronics 

September 2006 

1/11 

Rev 3 

_www.st.com_ 

**Characteristics** 

**USBDFxxW5** 

## **1 Characteristics** 

## **Table 1. Absolute maximum ratings (Tamb = 25° C)** 

|**Table 1.**|**Absolute maximum ratings (Tamb = 25° C)**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|VPP|ESD discharge IEC 61000-4-2, contact discharge<br>ESD discharge - MIL STD 883 - Method 3015-6|±15<br>±25|kV|
|Tj|Operating junction temperature range|-40 to 150|°C|
|Tstg|Storage temperature range|- 55 to +150|°C|
|TL|Lead solder temperature (10 second duration)|260|°C|
|Pr|Power rating per resistor|100|mW|



|**Table 2.**<br>**Electrical characteristics(Tamb = 25° C)**|**Table 2.**<br>**Electrical characteristics(Tamb = 25° C)**|**Table 2.**<br>**Electrical characteristics(Tamb = 25° C)**|**Table 2.**<br>**Electrical characteristics(Tamb = 25° C)**|**Table 2.**<br>**Electrical characteristics(Tamb = 25° C)**|**Table 2.**<br>**Electrical characteristics(Tamb = 25° C)**|**Table 2.**<br>**Electrical characteristics(Tamb = 25° C)**|
|---|---|---|---|---|---|---|
|**Symbol**|**Parameters**|**Test conditions**|**Min**|**Typ**|**Max**|**Unit**|
|VBR|Diode breakdown voltage|IR= 1 mA|6|||V|
|VF|Diode forward voltage drop|IF= 50 mA||0.9||V|



## **2 Application information** 

## **Figure 1. USB Standard requirements** 

**==> picture [383 x 226] intentionally omitted <==**

**----- Start of picture text -----**<br>
+Vbus<br>1.5k<br>Rt D+ D+ Rt<br>Full-speed or<br>Low-speed USBTransceiver Ct Rt Twisted pair shielded Rt Ct Full-speed USBTransceiver<br>D- Zo = 90ohms D-<br>Ct 15k 15k 5m max Ct<br>Host or Hub 0 or<br>Hub port Full-speed function<br>FULL SPEED CONNECTION<br>+Vbus<br>1.5k<br>Rt D+ D+ Rt<br>Full-speed or<br>Ct Ct Low-speed USB<br>Low-speed USBTransceiver Rt Untwisted unshielded Rt Transceiver<br>D- 3m max D-<br>Host or Ct 15k 15k Ct Hub 0 or<br>Hub port Low-speed function<br>LOW SPEED CONNECTION<br>**----- End of picture text -----**<br>


2/11 

**USBDFxxW5** 

**Application information** 

## **Figure 2. Application example** 

**==> picture [308 x 147] intentionally omitted <==**

**----- Start of picture text -----**<br>
Downstream port Upstream port<br>D+ (1)<br>D+ CABLE D-  (2)<br>+Vbus<br>USBDF USBUF<br>xxW5 xxW6<br>D- D-  (1)<br>D+ (2)<br>Host/Hub USB Peripheral<br>port transceiver transceiver<br>(1) for a low-speed port<br>(2) for a full-speed port<br>**----- End of picture text -----**<br>


## **2.1 EMI filtering** 

Current FCC regulations requires that class B computing devices meet specified maximum levels for both radiated and conducted EMI. 

- Radiated EMI covers the frequency range from 30 MHz to 1 GHz. 

- Conducted EMI covers the 450 kHz to 30 MHz range. 

For the types of devices utilizing the USB the most difficult test to pass is usually the radiated EMI test. For this reason the USBDF device aims to minimize radiated EMI. 

The differential signal (D+ and D-) of the USB does not contribute significantly to radiated or conducted EMI because the magnetic field of the two conductors exactly cancels each other. 

The inside of the PC environment is very noisy and designers must minimise noise coupling from the different sources. D+ and D- must not be routed near high speed lines (clocks...). 

Induced common mode noise can be minimised by running pairs of USB signals parallel to each other and running grounded guard trace on each side of the signal pair from the USB controller to the USBDF device. 

If possible, locate the USBDF device physically near the USB connectors. Distance between the USB controller and the USB connector must be minimized. 

The 47 pF (Ct) capacitors are used to divert high frequency energy to ground and for edge control, and must be placed between the USB Controller and the series termination resistors (Rt). Both Ct and Rt should be placed as close to the mSB Controller as practicable. 

The USBDFxxW5 ensure a filtering protection against electroMagnetic and radio-frequency Interference thanks to its low-pass filter structure. This filter is characterized by the following parameters : 

- cut-off frequency 

- Insertion loss 

- high frequency rejection 

_Figure 4._ shows the attenuation curve for frequencies up to 3 GHz. 

3/11 

**USBDFxxW5** 

**Application information** 

**Figure 3. Measurement configuration Figure 4. USBDFxxW5 attenuation curve** 

**==> picture [406 x 146] intentionally omitted <==**

**----- Start of picture text -----**<br>
Insertion loss (dB)<br>0<br>TEST BOARD<br>50  Ω TG OUT RF IN<br>-10<br>Vg 50  Ω<br>-20<br>-30<br>1 10 100 1000 3000<br>F (MHz)<br>UD1<br>**----- End of picture text -----**<br>


## **2.2 ESD protection** 

In addition to the requirements of termination and EMC compatibility, computing devices are required to be tested for ESD susceptibility. This test is described in the IEC 61000-4-2 and is already in place in Europe. This test requires that a device tolerates ESD events and remain operational without user intervention. 

The USBDFxxW5 is particularly optimized to perform ESD protection. ESD protection is based on the use of device which clamps at : 

VINPUT = VBR + Rd.Ipp 

This protection function is split in 2 stages. As shown in _Figure 5._ , the ESD strikes are clamped by the first stage S1 and then the remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output voltage very low at the Vout level. 

## **Figure 5. USBDFxxW5 ESD clamping behavior** 

**==> picture [395 x 105] intentionally omitted <==**

**----- Start of picture text -----**<br>
Rg S1 R S2<br>Rd Rd<br>Vinput Rload<br>VPP<br>VBR Voutput VBR<br>Device<br>to be<br>ESD Surge USBDFxxW5 protected<br>**----- End of picture text -----**<br>


4/11 

**USBDFxxW5** 

**Application information** 

To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical dynamical resistance value Rd. Taking into account the following hypothesis: Rt > Rd, Rg > R and Rload > Rd, gives these formulas:: 

**==> picture [124 x 59] intentionally omitted <==**

The results of the calculation done for VPP = 8 kV, Rg = 330 W (IEC61000-4-2 standard), VBR = 7 V (typ.) and Rd = 1 Ω (typ.) give: 

V = 31.2 V input 

- V = 7.95 V output 

This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the resistance R. 

The measurements results shown below show very clearly ( _Figure 7._ ) the high efficiency of the ESD protection : 

- no influence of the parasitic inductances on Vout stage 

- output clamping voltage very close to VBR (positive strike) and -VF (negative strike) 

## **Figure 6. Measurement board** 

**==> picture [203 x 136] intentionally omitted <==**

**----- Start of picture text -----**<br>
ESD<br>TEST BOARD<br>SURGE<br>15 kV<br>Air<br>Vin Vout<br>Discharge<br>UD1<br>**----- End of picture text -----**<br>


5/11 

**USBDFxxW5** 

**Application information** 

**Figure 7. Remaining voltage at both stages S1 (Vinput) and S2 (Voutput) during ESD surge** 

A. Positive surge B. Negative surge 

Note that the USBDFxxW5 is not only acting for positive ESD surges but also for negative ones. Negative disturbances are clamped close to ground voltage as shown in _Figure 7.b_ . 

## **2.3 Latch-up phenomena** 

The early ageing and destruction of IC’s is often due to latch-up phenomena which is mainly induced by dV/dt. Thanks to its structure, the USBDFxxW5 provides a high immunity to latch-up phenomena by smoothing very fast edges. 

## **2.4 Crosstalk behaviour** 

## **Figure 8. Crosstalk phenomena** 

**==> picture [346 x 130] intentionally omitted <==**

**----- Start of picture text -----**<br>
RG1<br>Line 1<br>VG1 RL1 α1 VG1 + β1  2VG2<br>RG2 Line 2<br>VG2 RL2 α2 VG2 + β2  1VG1<br>DRIVERS RECEIVERS<br>**----- End of picture text -----**<br>


The crosstalk phenomena is due to the coupling between 2 lines. The coupling factor ( β12 or β21 ) increases when the gap across lines decreases, this is the reason why we provide crosstalk measurements for a monolithic device to guarantee negligeable crosstalk between the lines. In the example above, the expected signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ). 

6/11 

**USBDFxxW5** 

**Application information** 

**==> picture [456 x 201] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 9. Analog crosstalk measurements Figure 10. Typical analog crosstalk results<br>Analog crosstalk (dB)<br>0<br>-20<br>TEST BOARD<br>50  Ω TG OUT RF IN<br>-40<br>Vg 50  Ω -60<br>-80<br>-100<br>1 10 100 1,000<br>frequency (MHz)<br>==n LL<br>Figure 8.  gives the measurement circuit for the analog crosstalk application. In  Figure 10. ,<br>the curve shows the effect of the D+ cell on the D- cell. In usual frequency range of analog<br>signals (up to 100 MHz) the effect on disturbed line is less than -46 dB.<br>UD1<br>**----- End of picture text -----**<br>


## **Figure 11. Digital crosstalk measurements Figure 12. Digital crosstalk results configuration** 

**==> picture [206 x 89] intentionally omitted <==**

**----- Start of picture text -----**<br>
+5V +5V<br>74HC04 74HC04<br>Line 1<br>Square an +5V VG1 USBDFxxW5 ><br>Pulse th<br>Generator Line 2<br>5KHz b 21 VG1<br>3 —|<br>**----- End of picture text -----**<br>


_Figure 11._ shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. 

_Figure 12._ shows that in such a condition signal, from 0 to 5 V and rise time of few ns, the impact on the other line is less than 100 mV peak to peak (below the logic high voltage threshold). The measurements performed with falling edges give the same results. 

7/11 

**USBDFxxW5** 

**Application information** 

## **2.5 Transition times** 

This low pass filter has been designed in order to meet the USB 1.1 standard requirements that implies the signal edges are maintained within the 4 ns-20 ns stipulated USB specification limits. 

## **Figure 13. Typical rise and fall times: measurements configuration** 

**==> picture [283 x 329] intentionally omitted <==**

**----- Start of picture text -----**<br>
+5V +5V<br>J L<br>74HC04 74HC04<br>D+<br>USBDF<br>JUL +5V xxW5<br>Square LL<br>Pulse D-<br>Generator<br>zt<br>Typical rise and fall timesypical rise and fall timesical rise and fall times<br>Seen ee | PANE TP et<br>PAP | Pee<br>ff Pe |<br>| PB<br>A |i tel | PT INE<br>E<br>pice([} “7.1 ns<br>Pall) 16.7 ns<br>A. Rise time B. Fall time<br>**----- End of picture text -----**<br>


**Figure 14. Typical rise and fall timesypical rise and fall timesical rise and fall times** 

8/11 ~~S77~~ 

**USBDFxxW5** 

**Package information** 

## **3 Package information** 

|**Table 3.**|**Table 3.**|**SOT323-5L dimensions**|**SOT323-5L dimensions**|**SOT323-5L dimensions**|**SOT323-5L dimensions**|**SOT323-5L dimensions**|**SOT323-5L dimensions**|**SOT323-5L dimensions**||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**c**<br>**Q1**<br>**b**||||||**A2**<br>**A**<br>**D**|||**Ref.**|**Dimensions**||||
|||||||||||**Millimeters**||**Inches**||
|||**E**||||||||||||
|||||||||||||||
|||||||||||**Min.**|**Max.**|**Min.**|**Max.**|
|||||||||||||||
||||||||||A|0.8|1.1|0.031|0.043|
||||||**e**|||||||||
||||||||||A1|0|0.1|0|0.004|
||||||**e**||||A2<br>|0.8<br>|1<br>|0.031<br>|0.039<br>|
||||||||||b|0.15|0.3|0.006|0.012|
|||||||||||||||
||||||||||c|0.1|0.18|0.004|0.007|
||||||||||D|1.8|2.2|0.071|0.086|
||||||||||E|1.15|1.35|0.045|0.053|
|||||||||||||||
||||||||||e|0.65 Typ.||0.025 Typ.||
||||||||||H|1.8<br>2.4||0.071<br>0.094||
||||||||||Q1|0.1|0.4|0.004|0.016|



**Figure 15. Recommended footprint (dimensions in mm)** 

**==> picture [98 x 142] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.3<br>1.0<br>2.9<br>1.0<br>0.35<br>**----- End of picture text -----**<br>


In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 

9/11 

**Ordering information** 

**USBDFxxW5** 

## **4** 

## **Ordering information** 

|**Type**|**Order Code**|**Weight**|**Marking**|**Package**|**Base Qty**|
|---|---|---|---|---|---|
|USBDF01W5|USBDF01W5|5.4 mg|UD1|SOT323-5L|3000|
|USBDF02W5|USBDF02W5||UD2|||



## **5 Revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|May-2000|1C|Initial release.|
|7-Sep-2006|2|Reformatted to current standard. Modified Operating junction<br>temperature range in Table 1.|
|15-Sep-2006|3|Corrected units of Rdto kΩinstead ofΩ. on page 1|



10/11 

**USBDFxxW5** 

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11/11 



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- [Supplier page](https://es.farnell.com/stmicroelectronics/usbdf01w5/filter-low-pass-1ghz-sot-323-5/dp/2341665)
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