# Power MOSFET, N Channel, 600 V, 18 A, 0.13 ohm, DFN, Surface Mount

![Product image](https://novapart.co/image/farnell:4816463/)

**URL**: https://novapart.co/products/TK130V60Z1,LQ(S/power-mosfet-n-channel-600-v-18-a-013-ohm-dfn
**SKU**: TK130V60Z1,LQ(S
**Manufacturer**: TOSHIBA
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.2400
**Stock**: 10+
**Lead Time**: 162 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 4Pins |
| Channel Type | N Channel |
| Product Range | DTMOSVI Series |
| Qualification | - |
| Power Dissipation | 150W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | DFN |
| Drain Source Voltage Vds | 600V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 18A |
| Drain Source On State Resistance | 0.13ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:4816463/)

TK130V60Z1 

MOSFETs Silicon N-Channel MOS (DTMOS VI ) 

## TK130V60Z1 

## 1. Applications 

- Switching Power Supplies 

## 2. Features 

- (1) Low drain-source on-resistance: RDS(ON) = 0.108 Ω (typ.) 

- (2) High-speed switching properties with the lower capacitance. 

- (3) Enhancement mode: Vth = 3 to 4 V (VDS = 10 V, ID = 0.73 mA) 

## 3. Packaging and Internal Circuit 

1: Gate 2: Source 1 3, 4: Source 2 5: Drain (heatsink) 

Notice: Only use source 1 pin for gate input signal return. Please make sure that the main current flows into the source 2 pin. 

DFN8x8 

## 4. Absolute Maximum Ratings (Note) (Ta = 25 

unless otherwise specified) 

Characteristics Symbol Rating Unit ~~es~~ Drain-source voltage VDSS 600 V ~~ooa~~ Gate-source voltage VGSS ±30 Drain current (DC) (Note 1) ID 18 A ~~a$f~~ Drain current (pulsed) (Note 1) IDP 72 ~~©~~ Power dissipation (Tc = 25 ) PD 150 W ~~a~~ Single-pulse avalanche energy (Note 2) EAS 242 mJ ~~a~~ Single-pulse avalanche current IAS 4.2 A ~~a~~ Reverse drain current (DC) (Note 1) IDR 18 ~~a~~ Reverse drain current (pulsed) (Note 1) IDRP 72 Channel temperature Tch 150 ~~a———————E~~ Storage temperature Tstg -55 to 150 

Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. 

Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). 

Start of commercial production 2024-07 

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TK130V60Z1 

5. Thermal Characteristics 

Characteristics Symbol Max Unit ~~ee CG~~ Channel-to-case thermal resistance Rth(ch-c) 0.833 /W Note 1: Ensure that the channel temperature does not exceed 150 c . Note 2: VDD = 90 V, Tch = 25 °C (initial), L = 24.3 mH, IAS = 4.2 A 

Note: This transistor is sensitive to electrostatic discharge and should be handled with care. 

## 6. Electrical Characteristics 

## 6.1. Static Characteristics (Ta = 25 

## unless otherwise specified) 

Characteristics Symbol Test Condition Min Typ. Max Unit ~~eeee es~~ Gate leakage current IGSS VGS = ±30 V, VDS = 0 V ±1 µA ~~eea~~ Drain cut-off current IDSS VDS = 600 V, VGS = 0 V ~~ee el~~ 2 Drain-source breakdown voltage V(BR)DSS ID = 10 mA, VGS = 0 V 600 V ~~eG~~ Gate threshold voltage Vth ~~Ge~~ VDS = 10 V, ID = 0.73 mA 3 4 ~~es ee ee el~~ Drain-source on-resistance RDS(ON) VGS = 10 V, ID = 6 A 0.108 0.13 Ω ~~PO =~~ 

## 6.2. Dynamic Characteristics (Ta = 25 

## unless otherwise specified) 

|Characteristics<br>~~ee~~<br>~~ee~~|Symbol<br>~~ee~~<br>~~es~~|Test Condition<br>~~ee~~<br>~~es~~<br>~~|-~~|Min<br>~~ee~~<br>~~|- |~~|Typ.<br>~~ee~~<br>~~||~~|Max<br>~~ee~~<br>~~-|~~|Unit<br>~~ee~~|
|---|---|---|---|---|---|---|
|Input capacitance<br>~~ee~~<br>~~ee~~|Ciss<br>~~es~~<br>~~ee~~|VDS= 300 V, VGS= 0 V, f = 100 kHz<br> ~~es~~<br>~~|-~~<br>~~|}~~<br>~~oe~~|~~|- |~~<br>~~|}-|~~|1620<br>~~||~~<br>~~|~~|~~-|~~<br>|pF|
|Reverse transfer capacitance<br>~~ee~~<br>~~ee~~|Crss<br>~~es ~~<br>~~ee~~||~~|- |~~<br>~~|}-|~~|2.3<br>~~| | ~~<br>~~||[-|~~|~~-|~~<br>~~|[-|~~||
|Output capacitance<br>~~ee~~|Coss<br>~~ee~~||~~|} - |~~|40<br>~~|~~|||
|Effective output capacitance<br>(energyrelated)<br>(Note 3)|Co(er)|VDS= 0 to 400 V, VGS= 0 V<br>~~oe~~||70|||
|Effective output capacitance<br>(time related)<br>(Note 4)|Co(tr)|||480|||
|Gate resistance<br>~~GO~~<br>~~ee~~|rg<br>~~GO~~|VDS= OPEN , f = 1 MHz<br>~~oe~~<br>~~GO~~<br>~~|-~~|~~GO~~<br>~~|-|~~|3.2<br>~~GO~~<br>~~|~~<br>~~|~~|~~GO~~<br>~~-|~~|Ω<br>~~GO~~|
|Switching time (rise time)<br>~~ee~~<br>~~ee~~|tr|See Figure 6.2.1<br>~~|-~~<br>~~|}-~~<br>~~|}~~<br>~~|-~~|~~|-|~~<br>~~|}-|~~|16<br>~~|~~<br>~~|~~<br>~~|~~|~~-|~~<br>|ns|
|Switching time (turn-on time)<br>~~ee~~<br>~~ee~~<br>~~ee~~|ton<br>~~ee~~||~~|- |~~<br>~~|}-|~~<br>~~|}-|~~|38<br>~~|~~<br>~~| ~~<br>~~||[-|~~<br>~~|~~|~~-|~~<br>~~|[-|~~<br>||
|Switching time (fall time)<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~DR~~|tf<br>~~ee~~||~~|}- |~~<br>~~|}-|~~<br>~~|-|~~|5<br>~~||[-|~~<br>~~||[-|~~<br>~~|~~<br>~~|~~|~~|[-|~~<br>~~|[-|~~<br>~~-|~~||
|Switching time (turn-off time)<br>~~ee~~<br>~~ee~~<br>~~DR~~|toff<br>~~ee~~||~~|} - |~~<br>~~|-|~~|75<br>~~|[-|~~<br>~~||[-|~~<br>~~|~~<br>~~|~~<br>~~ee~~|~~|[-|~~<br>~~|[-|~~<br>~~-|~~<br>~~ee~~||
|MOSFET dv/dt ruggedness<br>~~ee~~<br>~~DR~~|dv/dt<br>~~GG~~|VDS ≤VDSS, ID ≤9 A<br><br>~~|-~~<br>~~GG~~|70<br><br>~~|-|~~<br>~~GG~~|~~|[-|~~<br>~~|~~<br>~~|~~<br>~~GG~~<br>~~ee~~|~~|[-|~~<br>~~-|~~<br>~~GG~~<br>~~ee~~|V/ns<br>~~GG~~|



Note 3: CO(er) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0V to 400V. Note 4: CO(tr) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0V to 400V. 

VDD ≈ 400 V VGS = 10 V/0 V ID = 9 A RL = 44 Ω RG = 10 Ω Duty ≤ 1 %, tw = 10 µs 

Fig. 6.2.1 Switching Time Test Circuit 

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TK130V60Z1 

## 6.3. Gate Charge Characteristics (Ta = 25 °C unless otherwise specified) 

|Characteristics|Symbol|Test Condition|Min|Typ.|Max|Unit|
|---|---|---|---|---|---|---|
|Total gate charge (gate-source plus<br>gate-drain)|Qg|VDD≈400 V, VGS= 10 V, ID= 18 A||28||nC|
|Gate-source charge 1|Qgs1|||9|||
|Gate-drain charge|Qgd|||8|||



## 6.4. Source-Drain Characteristics (Ta = 25 °C unless otherwise specified) 

|Characteristics|Symbol|Test Condition|Min|Typ.|Max|Unit|
|---|---|---|---|---|---|---|
|Diode forward voltage|VDSF|IDR= 18 A, VGS= 0 V|||-1.7|V|
|Reverse recovery time|trr|VDD= 400 V,<br>IDR= 9 A, VGS= 0 V<br>-dIDR/dt = 100 A/µs||280||ns|
|Reverse recovery charge|Qrr|VDD= 400 V,<br>IDR= 9 A, VGS= 0 V<br>-dIDR/dt = 100 A/µs||2.9||µC|
|Peak reverse recovery current|Irr|||21||A|
|Diode dv/dt ruggedness|dv/dt|VDD ≤400 V, IDR ≤9 A, VGS= 0 V|40|||V/ns|



## 7. Marking 

Fig. 7.1 Marking 

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TK130V60Z1 

## 8. Characteristics Curves (Note) 

Fig. 8.1 ID - VDS 

Fig. 8.3 ID - VGS 

Fig. 8.5 VDSS - Ta 

Fig. 8.2 ID - VDS 

Fig. 8.4 VDS - VGS 

Fig. 8.6 RDS(ON) - ID 

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TK130V60Z1 

Fig. 8.7 RDS(ON) - Ta 

**==> picture [82 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig. 8.9 C - VDS<br>**----- End of picture text -----**<br>


Fig. 8.11 Dynamic Input/Output Characteristics 

**==> picture [88 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig. 8.8 IDR - VDS<br>**----- End of picture text -----**<br>


**==> picture [86 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig. 8.10 Vth - Ta<br>**----- End of picture text -----**<br>


**==> picture [104 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig. 8.12 EOSS - VDS<br>**----- End of picture text -----**<br>


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Fig. 8.13 rth - tw (Guaranteed Maximum) 

Fig. 8.14 EAS - Tch (Guaranteed Maximum) 

Fig. 8.16 Test Circuit/Waveform 

**==> picture [110 x 24] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig. 8.15 PD - Tc<br>(Guaranteed Maximum)<br>**----- End of picture text -----**<br>


Fig. 8.17 ID - Tc (Guaranteed Maximum) 

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Fig. 8.18 Safe Operating Area (Guaranteed Maximum) 

Note: The above characteristics curves are presented for reference only and not guaranteed by production test, unless otherwise noted. 

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TK130V60Z1 

## Package Dimensions 

Unit: mm 

Weight: 0.175 g (typ.) 

Package Name(s) TOSHIBA: 2-8T1A Nickname: DFN8x8 

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TK130V60Z1 

## RESTRICTIONS ON PRODUCT USE 

Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as "TOSHIBA". Hardware, software and systems described in this document are collectively referred to as "Product". 

- TOSHIBA reserves the right to make changes to the information in this document and related Product without notice. 

- This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. 

- Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS. 

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https://toshiba.semicon-storage.com/ 

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