# Bipolar (BJT) Single Transistor, PNP, 100 V, 2 A, 50 W, TO-220, Through Hole

![Product image](https://novapart.co/image/farnell:2535658/)

**URL**: https://novapart.co/products/TIP117G/bipolar-bjt-single-transistor-pnp-100-v-2-a-50-w
**SKU**: TIP117G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || Transistors || Bipolar Transistors || Single Bipolar Junction Transistors - BJT
**Price**: €0.4080
**Stock**: 50+
**Lead Time**: 2 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 3Pins |
| Qualification | AEC-Q101 |
| Power Dissipation | 50W |
| Dc Current Gain Hfe | 500hFE |
| Transistor Mounting | Through Hole |
| Transistor Polarity | PNP |
| Transistor Case Style | TO-220 |
| Dc Current Gain Hfe Min | 500hFE |
| Operating Temperature Max | 150°C |
| Continuous Collector Current | 2A |
| Collector Emitter Voltage Max | 100V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2535658/)

## TIP110, TIP111, TIP112 (NPN); TIP115, TIP116, TIP117 (PNP) 

## Plastic Medium-Power Complementary Silicon Transistors 

Designed for general−purpose amplifier and low−speed switching applications. 

## **Features** 

- High DC Current Gain − hFE = 2500 (Typ) @ IC = 1.0 Adc 

- Collector−Emitter Sustaining Voltage − @ 30 mAdc VCEO(sus) = 60 Vdc (Min) − TIP110, TIP115 

   - = 80 Vdc (Min) − TIP111, TIP116 

   - = 100 Vdc (Min) − TIP112, TIP117 

- Low Collector−Emitter Saturation Voltage − VCE(sat) = 2.5 Vdc (Max) @ IC = 2.0 Adc 

- Monolithic Construction with Built−in Base−Emitter Shunt Resistors 

- Pb−Free Packages are Available* 

**www.onsemi.com** 

**DARLINGTON 2 AMPERE COMPLEMENTARY SILICON POWER TRANSISTORS 60−80−100 VOLTS, 50 WATTS** 

**==> picture [170 x 195] intentionally omitted <==**

**----- Start of picture text -----**<br>
MARKING<br>DIAGRAM<br>4<br>TO−220AB<br>CASE 221A TIP11xG<br>STYLE 1 AYWW<br>STYLE 1:<br>1 } 2 PIN 1.2. BASECOLLECTOR<br>3 3. EMITTER<br>4. COLLECTOR<br>TIP11x = Device Code<br>x = 0, 1, 2, 5, 6, or 7<br>A = Assembly Location<br>Y = Year<br>WW = Work Week<br>G = Pb−Free Package<br>**----- End of picture text -----**<br>


## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 3 of this data sheet. 

> *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

Publication Order Number: **TIP110/D** 

**1** 

© Semiconductor Components Industries, LLC, 2014 **November, 2014 − Rev. 8** 

**TIP110, TIP111, TIP112 (NPN); TIP115, TIP116, TIP117 (PNP)** 

## **MAXIMUM RATINGS** 

|**MAXIMUM RATINGS**||||||
|---|---|---|---|---|---|
|**Rating**|**Symbol**|**TIP110,**<br>**TIP115**|**TIP111,**<br>**TIP116**|**TIP112,**<br>**TIP117**|**Unit**|
|Collector−Emitter Voltage|VCEO|60|80|100|Vdc|
|Collector−Base Voltage|VCB|60|80|100|Vdc|
|Emitter−Base Voltage|VEB|5.0|||Vdc|
|Collector Current −Continuous<br>−Peak|IC|2.0<br>4.0|||Adc|
|Base Current|IB|50|||mAdc|
|Total Power Dissipation @ TC= 25°C<br>Derate above 25°C|PD|50<br>0.4|||W<br>W/°C|
|Total Power Dissipation @ TA= 25°C<br>Derate above 25°C|PD|2.0<br>0.016|||W<br>W/°C|
|Unclamped Inductive Load Energy − Figure 13|E|25|||mJ|
|Operating and Storage Junction|TJ, Tstg|–65 to +150|||°C|
|**THERMAL CHARACTERISTICS**||||||
|**Characteristics**|**Symbol**|**Max**|||**Unit**|
|Thermal Resistance, Junction−to−Case|R�JC|2.5|||°C/W|
|Thermal Resistance, Junction−to−Ambient|R�JA|62.5|||°C/W|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **ELECTRICAL CHARACTERISTICS** (TC = 25 ° C unless otherwise noted) 

|**ELECTRICAL CHARACTERISTICS**(TC= 25°C unless otherwise noted)|||||
|---|---|---|---|---|
|**Characteristic**|**Symbol**|**Min**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**|||||
|Collector−Emitter Sustaining Voltage (Note 1)<br>(IC= 30 mAdc, IB= 0)<br>TIP110, TIP115<br>TIP111, TIP116<br>TIP112, TIP117|VCEO(sus)|60<br>80<br>100|−<br>−<br>−|Vdc|
|Collector Cutoff Current<br>(VCE= 30 Vdc, IB= 0)<br>TIP110, TIP115<br>(VCE= 40 Vdc, IB= 0)<br>TIP111, TIP116<br>(VCE= 50 Vdc, IB= 0)<br>TIP112 ,TIP117|ICEO|−<br>−<br>−|2.0<br>2.0<br>2.0|mAdc|
|Collector Cutoff Current<br>(VCB= 60 Vdc, IE= 0)<br>TIP110, TIP115<br>(VCB= 80 Vdc, IE= 0)<br>TIP111, TIP116<br>(VCB= 100 Vdc, IE= 0)<br>TIP112, TIP117|ICBO|−<br>−<br>−|1.0<br>1.0<br>1.0|mAdc|
|Emitter Cutoff Current<br>(VBE= 5.0 Vdc, IC= 0)|IEBO|−|2.0|mAdc|
|**ON CHARACTERISTICS**(Note 1)|||||
|DC Current Gain<br>(IC= 1.0 Adc, VCE= 4.0 Vdc)<br>(IC= 2.0 Adc, VCE= 4.0 Vdc)|hFE|1000<br>500|−<br>−|−|
|Collector−Emitter Saturation Voltage (IC= 2.0 Adc, IB= 8.0 mAdc)|VCE(sat)|−|2.5|Vdc|
|Base−Emitter On Voltage (IC= 2.0 Adc, VCE= 4.0 Vdc)|VBE(on)|−|2.8|Vdc|
|**DYNAMIC CHARACTERISTICS**|||||
|Small−Signal Current Gain (IC= 0.75 Adc, VCE= 10 Vdc, f = 1.0 MHz)|hfe|25|−|−|
|Output Capacitance<br>(VCB= 10 Vdc, IE= 0, f = 0.1 MHz)<br>TIP115, TIP116, TIP117<br>TIP110, TIP111, TIP112|Cob|−<br>−|200<br>100|pF|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Pulse Test: Pulse Width � 300 � s, Duty Cycle � 2%. 

**www.onsemi.com** 

**2** 

**TIP110, TIP111, TIP112 (NPN); TIP115, TIP116, TIP117 (PNP)** 

**==> picture [274 x 122] intentionally omitted <==**

**----- Start of picture text -----**<br>
COLLECTOR COLLECTOR<br>BASE BASE<br>≈ 8.0 k ≈ 120 ≈ 8.0 k ≈ 120<br>EMITTER EMITTER<br>**----- End of picture text -----**<br>


**Figure 1. Darlington Circuit Schematic** 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**|||
|---|---|---|
|**Device**|**Package**|**Shipping**|
|TIP110|TO−220|50 Units / Rail|
|TIP110G|TO−220<br>(Pb−Free)|50 Units / Rail|
|TIP111|TO−220|50 Units / Rail|
|TIP111G|TO−220<br>(Pb−Free)|50 Units / Rail|
|TIP112|TO−220|50 Units / Rail|
|TIP112G|TO−220<br>(Pb−Free)|50 Units / Rail|
|TIP115|TO−220|50 Units / Rail|
|TIP115G|TO−220<br>(Pb−Free)|50 Units / Rail|
|TIP116|TO−220|50 Units / Rail|
|TIP116G|TO−220<br>(Pb−Free)|50 Units / Rail|
|TIP117|TO−220|50 Units / Rail|
|TIP117G|TO−220<br>(Pb−Free)|50 Units / Rail|



**==> picture [251 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
TA TC<br>3.0 60<br>2.0 40<br>TC<br>1.0 20<br>TA<br>0 0<br>0 20 40 60 80 100 120 140 160<br>T, TEMPERATURE (°C)<br>PD, POWER DISSIPATION (WATTS)<br>**----- End of picture text -----**<br>


**Figure 2. Power Derating** 

**www.onsemi.com** 

**3** 

**TIP110, TIP111, TIP112 (NPN); TIP115, TIP116, TIP117 (PNP)** 

**==> picture [486 x 384] intentionally omitted <==**

**----- Start of picture text -----**<br>
4.0<br>RDB1, MUST BE FAST RECOVERY TYPE, eg: & RC VARIED TO OBTAIN DESIRED CURRENT LEVELS -�30 VVCC ts IVCCC/IB = 30 V = 250 ITB1J = 25 = IB2°C<br>�1N5825 USED ABOVE IB ≈ 100 mA RC 2.0<br>�MSD6100 USED BELOW IB ≈ 100 mA SCOPE<br>TUT<br>V2 RB tf<br>approx 1.0<br>+�8.0 V 0.8<br>51 D1 ≈ 8.0 k ≈ 60 tr<br>0 0.6<br>approxV1 +�4.0 V 0.4<br>-12 V 25 �s for td and tr, D1 is disconnected td @ VBE(off) = 0<br>tr, tf ≤ 10 ns to obtain desired test currents.and V2 = 0, RB and RC are varied PNPNPN<br>DUTY CYCLE = 1.0% 0.2<br>For NPN test circuit, reverse diode, 0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0<br>polarities and input pulses.<br>IC, COLLECTOR CURRENT (AMP)<br>Figure 3. Switching Times Test Circuit Figure 4. Switching Times<br>1.0<br>0.7<br>D = 0.5<br>0.5<br>0.3<br>0.2<br>0.2<br>0.1<br>0.1 Z�JC(t) = r(t) R�JC P(pk)<br>0.07 0.05 R �JC  = 2.5 ° C/W MAX<br>0.05 D CURVES APPLY FOR POWER<br>0.02 PULSE TRAIN SHOWN<br>0.03 t1<br>0.02 READ TIME AT t1 t2<br>0.01 SINGLE PULSE TJ(pk) - TC = P(pk) Z�JC(t) DUTY CYCLE, D = t1/t2<br>0.01<br>0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1.0 k<br>t, TIME (ms)<br>μ<br>t, TIME (��s)<br>(NORMALIZED)<br>r(t), TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


**Figure 5. Thermal Response** 

**www.onsemi.com** 

**4** 

**TIP110, TIP111, TIP112 (NPN); TIP115, TIP116, TIP117 (PNP)** 

## **ACTIVE−REGION SAFE−OPERATING AREA** 

**==> picture [487 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 10<br>4.0 4.0<br>1�ms<br>2.0 5�ms 2.0<br>TJ = 150°C dc TJ = 150°C dc<br>1.0 BONDING WIRE LIMITED 1.0 BONDING WIRE LIMITED<br>THERMALLY LIMITED THERMALLY LIMITED<br>@ TC = 25°C (SINGLE PULSE) @ TC = 25°C (SINGLE PULSE)<br>SECONDARY BREAKDOWN LIMITED SECONDARY BREAKDOWN LIMITED<br>CURVES APPLY BELOW TIP115 CURVES APPLY BELOW TIP110<br>RATED VCEO TIP116TIP117 RATED VCEO TIP111TIP112<br>0.1 0.1<br>1.0 10 40 60 80 100 1.0 10 60 80 100<br>VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)<br>IC, COLLECTOR CURRENT (AMPS) IC, COLLECTOR CURRENT (AMPS)<br>**----- End of picture text -----**<br>


**Figure 6. TIP115, 116, 117** 

**Figure 7. TIP110, 111, 112** 

There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC − VCE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. 

The data of Figures 6 and 7 is based on TJ(pk) = 150°C; TC is variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to 10% provided TJ(pk) < 150°C.  TJ(pk) may be calculated from the data in Figure 5. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. 

**==> picture [234 x 170] intentionally omitted <==**

**----- Start of picture text -----**<br>
200<br>TC = 25°C<br>100<br>70<br>50<br>Cob<br>30<br>Cib<br>20<br>PNP<br>NPN<br>10<br>0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0 6.0 10 20 40<br>VR, REVERSE VOLTAGE (VOLTS)<br>C, CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


**Figure 8. Capacitance** 

**www.onsemi.com** 

**5** 

**TIP110, TIP111, TIP112 (NPN); TIP115, TIP116, TIP117 (PNP)** 

**==> picture [489 x 643] intentionally omitted <==**

**----- Start of picture text -----**<br>
NPN PNP<br>TIP110, 111, 112 TIP115, 116, 117<br>6.0 k 6.0 k<br>4.0 k TJ = 125°C VCE = 3.0 V 4.0 k TJ = 125°C VCE = 3.0 V<br>3.0 k 3.0 k<br>25°C<br>2.0 k 25°C 2.0 k<br>-�55°C<br>-�55°C<br>1.0 k 1.0 k<br>800 800<br>600 600<br>400 400<br>300 300<br>0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0 0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0<br>IC, COLLECTOR CURRENT (AMP) IC, COLLECTOR CURRENT (AMP)<br>Figure 9. DC Current Gain<br>3.4 3.4<br>3.0 IC = TJ = 25°C 3.0 TJ = 25°C<br>0.5 A<br>1.0 A 2.0 A 4.0 A IC =<br>2.6 2.6 0.5 A 1.0 A 2.0 A 4.0 A<br>2.2 2.2<br>1.8 1.8<br>1.4 1.4<br>1.0 1.0<br>0.6 0.6<br>0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100<br>IB, BASE CURRENT (mA) IB, BASE CURRENT (mA)<br>Figure 10. Collector Saturation Region<br>2.2 2.2<br>TJ = 25°C TJ = 25°C<br>1.8 1.8<br>VBE(sat) @ IC/IB = 250<br>1.4 VBE(sat) @ IC/IB = 250 VBE @ VCE = 3.0 V 1.4 VBE @ VCE = 3.0 V<br>1.0 1.0<br>VCE(sat) @ IC/IB = 250 VCE(sat) @ IC/IB = 250<br>0.6 0.6<br>0.2 0.2<br>0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0 0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0<br>IC, COLLECTOR CURRENT (AMP) IC, COLLECTOR CURRENT (AMP)<br>hFE, DC CURRENT GAIN hFE, DC CURRENT GAIN<br>VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)<br>V, VOLTAGE (VOLTS) V, VOLTAGE (VOLTS)<br>**----- End of picture text -----**<br>


**Figure 11. “On” Voltages** 

**www.onsemi.com** 

**6** 

**TIP110, TIP111, TIP112 (NPN); TIP115, TIP116, TIP117 (PNP)** 

**==> picture [490 x 197] intentionally omitted <==**

**----- Start of picture text -----**<br>
NPN PNP<br>TIP110, 111, 112 TIP115, 116, 117<br>+�0.8 +�0.8<br>*APPLIES FOR IC/IB ≤ hFE/3 *APPLIES FOR IC/IB ≤ hFE/3<br>0 0<br>-�0.8 -�0.8 25°C to 150°C<br>-�1.6 25°C to 150°C -�1.6 *��VC for VCE(sat)<br>-�2.4 *��VC for VCE(sat) -�2.4 -�55°C to 25°C<br>-�55°C to 25°C<br>-�3.2 25°C to 150°C -�3.2 25°C to 150°C<br>-�4.0 �VC for VBE -�55°C to 25°C -�4.0 �VC for VBE -�55°C to 25°C<br>-�4.8 -�4.8<br>0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0 0.04 0.06 0.1 0.2 0.4 0.6 1.0 2.0 4.0<br>IC, COLLECTOR CURRENT (AMP) IC, COLLECTOR CURRENT (AMP)<br>C)° C)°<br>V, TEMPERATURE COEFFICIENTS (mV/ V, TEMPERATURE COEFFICIENTS (mV/<br>θ θ<br>**----- End of picture text -----**<br>


**Figure 12. Temperature Coefficients** 

**==> picture [489 x 174] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 [5] 10 [5]<br>REVERSE FORWARD REVERSE FORWARD<br>10 [4] 10 [4]<br>10 [3] VCE = 30 V 10 [3] VCE = 30 V<br>10 [2] 10 [2]<br>T J  = 150°C T J  = 150°C<br>10 [1] 10 [1]<br>100°C<br>10 [0] 100°C 10 [0]<br>25°C 25°C<br>10 [-1] 10 [-1]<br>-�0.6 -�0.4 -�0.2 0 +�0.2 +�0.4 +�0.6 +�0.8 +�1.0 +�1.2 +�1.4 -�0.6 -�0.4 -�0.2 0 +�0.2 +�0.4 +�0.6 +�0.8 +�1.0 +�1.2 +�1.4<br>VBE, BASE‐EMITTER VOLTAGE (VOLTS) VBE, BASE‐EMITTER VOLTAGE (VOLTS)<br>μ μ<br>, COLLECTOR CURRENT (��A) , COLLECTOR CURRENT (��A)<br>IC IC<br>**----- End of picture text -----**<br>


**Figure 13. Collector Cut-Off Region** 

**TEST CIRCUIT VOLTAGE AND CURRENT WAVEFORMS** 

**==> picture [473 x 153] intentionally omitted <==**

**----- Start of picture text -----**<br>
tw ≈ 3.5 ms (SEE NOTE A)<br>VCE MONITOR<br>0 V<br>INPUT<br>VOLTAGE<br>INPUT MJE254 RBB1 TUT 100 mH -�5 V 100 ms<br>2�k� +<br>50 � - VCC = 20 V COLLECTOR 0.71 A<br>50 � RBB2 IC CURRENT<br>100 � MONITOR 0 V<br>VBB1 = 10 V + RS = VCER<br>- VBB2 = 0 0.1 � COLLECTOR<br>VOLTAGE<br>20 V<br>VCE(sat)<br>**----- End of picture text -----**<br>


Note A: Input pulse width is increased until ICM = 0.71 A, NPN test shown; for PNP test reverse all polarity and use MJE224 driver. 

**Figure 14. Inductive Load Switching** 

**www.onsemi.com** 

**7** 

**TIP110, TIP111, TIP112 (NPN); TIP115, TIP116, TIP117 (PNP)** 

## **PACKAGE DIMENSIONS** 

**TO−220** CASE 221A−09 ISSUE AH 

NOTES: 

**==> picture [232 x 185] intentionally omitted <==**

**----- Start of picture text -----**<br>
SEATING<br>−T− PLANE<br>B F C<br>T S<br>4<br>Q te A a<br>1 2 3 U<br>H<br>K<br>Z<br>L R<br>V J<br>G<br>D<br>N<br>**----- End of picture text -----**<br>


|1.|DIMENSIONING AND TOLERANCING PER ANSI|DIMENSIONING AND TOLERANCING PER ANSI|DIMENSIONING AND TOLERANCING PER ANSI|DIMENSIONING AND TOLERANCING PER ANSI|DIMENSIONING AND TOLERANCING PER ANSI|
|---|---|---|---|---|---|
|2. <br>3.|Y14.5M, 1982.<br> CONTROLLING DIMENSION: INCH.<br> DIMENSION Z DEFINES A ZONE WHERE ALL<br>BODY AND LEAD IRREGULARITIES ARE<br>ALLOWED.<br>**DIM**<br>**MIN**<br>**MAX**<br>**MIN**<br>**MAX**<br>**MILLIMETERS**<br>**INCHES**<br>**A**<br>0.570<br>0.620<br>14.48<br>15.75<br>**B**<br>0.380<br>0.415<br>9.66<br>10.53<br>~~eee~~|||||
||**C**<br>0.160|0.190|4.07|4.83||
||**D**<br>0.025|0.038|0.64|0.96||
||**F**<br>0.142|0.161|3.61|4.09||
||**G**<br>0.095|0.105|2.42|2.66||
||**H**<br>0.110|0.161|2.80|4.10||
||**J**<br>0.014|0.024|0.36|0.61||
||**K**<br>0.500|0.562|12.70|14.27||
||**L**<br>0.045|0.060|1.15|1.52||
||**N**<br>0.190|0.210|4.83|5.33||
||**Q**<br>0.100|0.120|2.54|3.04||
||**R**<br>0.080|0.110|2.04|2.79||
||**S**<br>0.045|0.055|1.15|1.39||
||**T**<br>0.235|0.255|5.97|6.47||
||**U**<br>0.000|0.050|0.00|1.27||
||**V**<br>0.045|---|1.15|---||
||**Z**<br>---|0.080|---|2.04||
||STYLE 1:|||||
||PIN 1.<br>BASE|||||
||2.<br>COLLECTOR|||||
||3.<br>EMITTER|||||
||4.<br>COLLECTOR|||||



ON Semiconductor and the         are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf.  SCILLC reserves the right to make changes without further notice to any products herein.  SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC does not convey any license under its patent rights nor the rights of others.  SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.  Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.  SCILLC is an Equal Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **PUBLICATION ORDERING INFORMATION** 

## **LITERATURE FULFILLMENT** : 

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**TIP110/D** 

**8** 



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