# Power MOSFET, N Channel, 650 V, 138 A, 0.012 ohm, MAX-247, Through Hole

![Product image](https://novapart.co/image/farnell:2807335/)

**URL**: https://novapart.co/products/STY145N65M5/power-mosfet-n-channel-650-v-138-a-0012-ohm-max
**SKU**: STY145N65M5
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €24.0900
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:138A; Drain Source Voltage Vds:650V; On Resistance Rds(on):0.012ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; P

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh M5 |
| Qualification | - |
| Power Dissipation | 625W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | MAX-247 |
| Drain Source Voltage Vds | 650V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 138A |
| Drain Source On State Resistance | 0.012ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2807335/)

## **STY145N65M5** 

## N-channel 650 V, 0.012 Ω typ., 138 A MDmesh™ M5 Power MOSFET in a Max247 package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS @ TJmax**|**RDS(on) max.**|**ID**|
|---|---|---|---|
|STY145N65M5|710 V|0.015 Ω|138 A|



- Extremely low RDS(on) 

- Low gate charge and input capacitance 

- • Excellent switching performance 

**==> picture [93 x 37] intentionally omitted <==**

**----- Start of picture text -----**<br>
3<br>2<br>1<br>Max247<br>**----- End of picture text -----**<br>


- 100% avalanche tested 

## **Applications** 

- Switching applications 

**Figure 1: Internal schematic diagram** 

## **Description** 

This device is an N-channel Power MOSFET based on the MDmesh™ M5 innovative vertical process technology combined with the wellknown PowerMESH™ horizontal layout. The resulting product offers extremely low onresistance, making it particularly suitable for applications requiring high power and superior efficiency. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packaging**|
|---|---|---|---|
|STY145N65M5|145N65M5|Max247|Tube|



This is information on a product in full production. 

_www.st.com_ 

November 2015 

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|**Contents**<br>**STY145N65M5**|**Contents**<br>**STY145N65M5**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>Max247 package information ............................................................ 9|
|**5**|**Revision history ............................................................................ 11**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|± 25|V|
|ID|Drain current (continuous) at TC= 25 °C|138|A|
|ID|Drain current (continuous) at TC= 100 °C|87|A|
|IDM<br>_(1)_|Drain current (pulsed)|552|A|
|PTOT|Total dissipation at TC= 25 °C|625|W|
|IAR|Avalanche current, repetitive or not repetitive (pulse width<br>limited byTjmax)|12|A|
|EAS|Single pulse avalanche energy (starting Tj= 25 °C, ID= IAR,<br>VDD= 50 V)|2420|mJ|
|dv/dt_(2)_|Peak diode recoveryvoltage slope|15|V/ns|
|Tstg|Storage temperature|- 55 to 150|°C|
|Tj|Max. operating junction temperature|150||



## **Notes:** 

(1) Pulse width limited by safe operating area. 

(2) ISD ≤ 138 A, di/dt ≤ 400 A/µs; VDS(peak) < V(BR)DSS, VDD = 400 V. 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case max|0.2|°C/W|
|Rthj-amb|Thermal resistance junction-ambient max|30|°C/W|



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**Electrical characteristics** 

## **2 Electrical characteristics** 

TC = 25 °C unless otherwise specified 

**Table 4: On/off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 1 mA|650|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= 650 V|||10|µA|
|||VGS= 0 V, VDS= 650 V,<br>TC= 125 °C|||100|µA|
|IGSS|Gate-body leakage current|VDS= 0 V, VGS= ±25 V|||±100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|3|4|5|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID= 69 A||0.012|0.015|Ω|



**Table 5: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0 V|-|18500|-|pF|
|Coss|Output capacitance||-|413|-|pF|
|Crss|Reverse transfer<br>capacitance||-|11|-|pF|
|Co(er)<br>_(1)_|Equivalent output<br>capacitance energy<br>related|VGS= 0, VDS= 0 to 520 V|-|415|-|pF|
|Co(tr)<br>_(2)_|Equivalent output<br>capacitance time related||-|1950|-|pF|
|RG|Intrinsicgate resistance|f = 1 MHz, open drain|-|0.7|-|Ω|
|Qg|Totalgate charge|VDD= 520 V, ID= 69 A,<br>VGS= 10 V (see_Figure 15:_<br>_"Test circuit for gate charge_<br>_behavior"_)|-|414|-|nC|
|Qgs|Gate-source charge||-|114|-|nC|
|Qgd|Gate-drain charge||-|164|-|nC|



## **Notes:** 

(1)Co(er) is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 

(2)Co(tr) is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

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**Electrical characteristics** 

**Table 6: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(V)|Voltage delaytime|VDD= 400 V, ID= 85 A<br>RG= 4.7 Ω, VGS= 10 V<br>(see_Figure 16: "Test circuit_<br>_for inductive load switching_<br>_and diode recovery times"_<br>and_Figure 19: "Switching_<br>_time waveform"_)|-|255|-|ns|
|tr(V)|Voltage rise time||-|11|-|ns|
|tf(i)|Current fall time||-|82|-|ns|
|tC(off)|Crossing time||-|88|-|ns|



**Table 7: Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||138|A|
|ISDM,_(1)_|Source-drain current (pulsed)||-||552|A|
|VSD<br>_(2)_|Forward on voltage|VGS= 0 V, ISD= 138 A|-||1.5|V|
|trr|Reverse recoverytime|ISD= 138 A,<br>di/dt = 100 A/µs,<br>VDD= 100 V (see_Figure_<br>_16: "Test circuit for_<br>_inductive load switching_<br>_and diode recovery times"_)|-|568||ns|
|Qrr|Reverse recoverycharge||-|14.5||µC|
|IRRM|Reverse recovery current||-|51||A|
|trr|Reverse recoverytime|ISD= 138 A,<br>di/dt = 100 A/µs,<br>VDD= 100 V, Tj= 150 °C<br>(see_Figure 16: "Test circuit_<br>_for inductive load switching_<br>_and diode recovery times"_)|-|728||ns|
|Qrr|Reverse recoverycharge||-|24.5||µC|
|IRRM|Reverse recovery current||-|67||A|



## **Notes:** 

(1) Pulse width is limited by safe operating area 

(2) Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

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**Electrical characteristics** 

## **2.2 Electrical characteristics (curves)** 

**==> picture [416 x 362] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>AM09125v1<br>K<br>δ =0.5<br>0.2<br>0.1<br>0.05<br>10 -1<br>0.02<br>0.01 Zth=k Rthj-c<br>Single pulse d=tp/t<br>tp<br>t<br>1010-2 -4 10 -3 10 -2 10 -1 tp [(s)]<br>Figure 4: Output characteristics  Figure 5: Transfer characteristics<br>AM17901v1 AM17902v1<br>ID (A) ID<br>VGS=10V 9V (A) VDS=30V<br>300 300<br>8V<br>250 250<br>200 200<br>150 150<br>7V<br>100 100<br>50 50<br>6V<br>0 0<br>0 5 10 15 20 25 VDS(V) 0 1 2 3 4 5 6 7 8 VGS(V)<br>**----- End of picture text -----**<br>


**Figure 6: Gate charge vs gate-source voltage** 

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**Figure 7: Static drain-source on-resistance** 

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**Electrical characteristics** 

**==> picture [394 x 177] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 8: Capacitance variations  Figure 9: Normalized gate threshold voltage<br>vs temperature<br>C AM15553v1 VGS(th) AM08899v1<br>(pF) (norm)<br>1.10<br>100000 ID= 250µA<br>V DS = V GS<br>Ciss<br>10000 1.00<br>1000<br>0.90<br>Coss<br>100 f=1 MHz<br>0.80<br>10 Crss<br>1 0.70<br>0.1 1 10 100 VDS(V) -50 -25 0 25 50 75 100 TJ(°C)<br>**----- End of picture text -----**<br>


**Figure 10: Normalized on-resistance vs Figure 11: Normalized V(BR)DSS vs temperature temperature** 

**==> picture [383 x 145] intentionally omitted <==**

**----- Start of picture text -----**<br>
RDS(on) AM08900v1 V(BR)DSS AM10399v1<br>(norm) (norm)<br>2.1 1.08<br>ID = 69A ID = 1mA<br>1.06<br>VGS= 10V<br>1.7 1.04<br>1.02<br>1.3 1.00<br>0.98<br>0.9<br>0.96<br>0.94<br>0.5 0.92<br>-50 -25 0 25 50 75 100 TJ(°C) -50 -25 0 25 50 75 100 TJ(°C)<br>**----- End of picture text -----**<br>


**Figure 12: Output capacitance stored energy** 

**==> picture [166 x 147] intentionally omitted <==**

**Figure 13: Switching losses vs gate resistance** 

**==> picture [167 x 145] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM15555v1<br>E (µJ)<br>9000 VDD=400 V Eon<br>VGS=10 V<br>8000 ID=85 A<br>7000<br>6000<br>5000<br>4000 Eoff<br>3000<br>2000<br>1000<br>0<br>0 10 20 30 40 RG(W)<br>**----- End of picture text -----**<br>


The previous figure Eon includes reverse recovery of a SiC diode. 

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**Test circuits** 

## **3 Test circuits** 

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**----- Start of picture text -----**<br>
Figure 14: Test circuit for resistive load  Figure 15: Test circuit for gate charge<br>switching times  behavior<br>Figure 16: Test circuit for inductive load  Figure 17: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>**----- End of picture text -----**<br>


**==> picture [403 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 18: Unclamped inductive waveform  Figure 19: Switching time waveform<br>Concept waveform for Indu ctive Load Turn-off<br>Id<br>90%Vds 90%Id<br>Tdelay -off<br>Vgs<br>90%Vgs on<br>Vgs(I(t ))<br>10%Vds 10%Id<br>Vds<br>Trise Tfall<br>Tcross - over AM05540v2_for_M5<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 Max247 package information** 

**Figure 20: Max247 package outline** 

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**----- Start of picture text -----**<br>
0094330_Rev_D<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 8: Max247 package mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.70|-|5.30|
|A1|2.20|-|2.60|
|b|1.00|-|1.40|
|b1|2.00|-|2.40|
|b2|3.00|-|3.40|
|c|0.40|-|0.80|
|D|19.70|-|20.30|
|e|5.35|-|5.55|
|E|15.30|-|15.90|
|L|14.20|-|15.20|
|L1|3.70|-|4.30|



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**Revision history** 

## **5 Revision history** 

**Table 9: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|25-Sep-2012|1|First release.|
|17-Jan-2013|2|Modified: IARand EASvalues<br>Modified: typical values on Table 5, 6 and 7|
|13-Nov-2015|3|Updated title, features and description on cover page.<br>Document status promoted from preliminary to production data.<br>Modified:_Table 2: "Absolute maximum ratings"_and_Table 3: "Thermal_<br>_data"_<br>Updated:_Figure 4: "Output characteristics"_and_Figure 5: "Transfer_<br>_characteristics"_<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2015 STMicroelectronics – All rights reserved 

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