# Power MOSFET, N Channel, 900 V, 7 A, 0.72 ohm, TO-247, Through Hole

![Product image](https://novapart.co/image/farnell:2729688/)

**URL**: https://novapart.co/products/STW7N90K5/power-mosfet-n-channel-900-v-7-a-072-ohm-to-247
**SKU**: STW7N90K5
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.7570
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh |
| Power Dissipation | 110W |
| Transistor Mounting | Through Hole |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 110W |
| Rds(On) Test Voltage | 10V |
| On Resistance Rds(On) | 0.72ohm |
| Transistor Case Style | TO-247 |
| Drain Source Voltage Vds | 900V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 7A |
| Drain Source On State Resistance | 0.72ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2729688/)

## **STW7N90K5** 

N-channel 900 V, 0.72 Ω typ., 7 A MDmesh™ K5 Power MOSFET in a TO-247 package 

Datasheet - production data 

## **Features** 

**Order code VDS RDS(on) max. ID** STW7N90K5 900 V 0.81 Ω 7 A ~~Sea~~ 

- Industry’s lowest RDS(on) x area 

- Industry’s best FoM (figure of merit) 

**==> picture [62 x 54] intentionally omitted <==**

**----- Start of picture text -----**<br>
3<br>2<br>1<br>TO-247<br>**----- End of picture text -----**<br>


- Ultra-low gate charge 

- 100% avalanche tested 

- Zener-protected 

## **Applications** 

- Switching applications 

**Figure 1: Internal schematic diagram** 

## **Description** 

This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STW7N90K5|7N90K5|TO-247|Tube|



_www.st.com_ 

October 2016 

DocID029863 Rev 1 

1/12 

This is information on a product in full production. 

|**Contents**<br>**STW7N90K5**|**Contents**<br>**STW7N90K5**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>TO-247 package information ............................................................. 9|
|**5**|**Revision history ............................................................................ 11**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|± 30|V|
|ID|Drain current (continuous) at TC= 25 °C|7|A|
|ID|Drain current (continuous) at TC= 100 °C|4.4|A|
|ID_(1)_|Drain current (pulsed)|28|A|
|PTOT|Total dissipation at TC= 25 °C|110|W|
|dv/dt_(2)_|Peak diode recoveryvoltage slope|4.5|V/ns|
|dv/dt_(3)_|MOSFET dv/dt ruggedness|50||
|Tj|Operating junction temperature range|- 55 to 150|°C|
|Tstg|Storage temperature range|||



## **Notes:** 

(1)Pulse width limited by safe operating area 

(2)ISD ≤ 7 A, di/dt ≤ 100 A/μs; VDS peak < V(BR)DSS, VDD = 450 V 

(3)VDS ≤ 720 V 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|1.14|°C/W|
|Rthj-amb|Thermal resistance junction-ambient|50|°C/W|



## **Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR|Avalanche current, repetitive or not repetitive (pulse width<br>limited by Tjmax)|2.4|A|
|EAS|Single pulse avalanche energy (starting Tj= 25 °C,<br>ID= IAR, VDD= 50 V)|230|mJ|



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**Electrical characteristics** 

## **2 Electrical characteristics** 

TC = 25 °C unless otherwise specified 

**Table 5: On/off-state** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown voltage|VGS= 0 V, ID= 1 mA|900|||V|
|IDSS|Zero gate voltage drain current|VGS= 0 V, VDS= 900 V|||1|µA|
|||VGS= 0 V, VDS= 900 V<br>TC= 125 °C_(1)_|||50|µA|
|IGSS|Gate bodyleakage current|VDS= 0 V, VGS= ±20 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDD= VGS, ID= 100µA|3|4|5|V|
|RDS(on)|Static drain-source on-resistance|VGS= 10 V, ID= 3.5 A||0.72|0.81|Ω|



## **Notes:** 

(1)Defined by design, not subject to production test. 

**Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0 V|-|425|-|pF|
|Coss|Output capacitance||-|41|-|pF|
|Crss|Reverse transfer capacitance||-|1.2|-|pF|
|Co(tr)_(1)_|Equivalent capacitance time<br>related|VGS= 0,<br>VDS= 0 to 720 V|-|64|-|pF|
|Co(er)_(2)_|Equivalent capacitance energy<br>related|||24||pF|
|Rg|Intrinsic gate resistance|f = 1 MHz , ID= 0 A|-|6.7|-|Ω|
|Qg|Totalgate charge|VDD= 720 V, ID= 7 A<br>VGS= 10 V<br>(see_Figure 15: "Test_<br>_circuit for gate charge_<br>_behavior"_)|-|17.7|-|nC|
|Qgs|Gate-source charge||-|3.1|-|nC|
|Qgd|Gate-drain charge||-|13|-|nC|



## **Notes:** 

(1)Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 

(2)Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. 

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**Electrical characteristics** 

**Table 7: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 450 V, ID= 3.5 A, RG= 4.7 Ω<br>VGS= 10 V<br>(see_Figure 14: "Test circuit for_<br>_resistive load switching times"_and<br>_Figure 19: "Switching time_<br>_waveform"_)|-|13.2|-|ns|
|tr|Rise time||-|14.2|-|ns|
|td(off)|Turn-off delaytime||-|31.6|-|ns|
|tf|Fall time||-|14.7|-|ns|



**Table 8: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain<br>current||-||7|A|
|ISDM_(1)_|Source-drain<br>current (pulsed)||-||28|A|
|VSD_(2)_|Forward on<br>voltage|ISD= 7 A, VGS= 0 V|-||1.5|V|
|trr|Reverse recovery<br>time|ISD= 7 A, di/dt = 100 A/µs,<br>VDD= 60 V<br>(see_Figure 16: "Test circuit for_<br>_inductive load switching and diode_<br>_recovery times"_)|-|352||ns|
|Qrr|Reverse recovery<br>charge||-|3.63||µC|
|IRRM|Reverse recovery<br>current||-|20.6||A|
|trr|Reverse recovery<br>time|ISD= 7 A, di/dt = 100 A/µs VDD= 60<br>V, Tj= 150 °C<br>(see_Figure 16: "Test circuit for_<br>_inductive load switching and diode_<br>_recovery times"_)|-|525||ns|
|Qrr|Reverse recovery<br>charge||-|4.94||µC|
|IRRM|Reverse recovery<br>current||-|18.8||A|



## **Notes:** 

(1)Pulse width limited by safe operating area 

(2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

**Table 9: Gate-source Zener diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)GSO|Gate-source<br>breakdown<br>voltage|IGS= ± 1mA, ID= 0 A|±30|-|-|V|



The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. 

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## **Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**==> picture [178 x 163] intentionally omitted <==**

**==> picture [167 x 178] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 3: Thermal impedance<br>CG20930<br>K<br>δ = 0.5<br>δ = 0.2<br>δ = 0.1<br>10 [-1]<br>Zδ = tZ δ = tthth  = k R = k Rpp / /  Ƭ  Ƭ ththjj-C�-C�<br>δ = 0.05<br>δ = 0.02<br>SINGLE PULSEδ = 0.01 tt pp ƬƬ<br>10 [-2]<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] tp(s)<br>**----- End of picture text -----**<br>


**Figure 4: Output characteristics** 

**==> picture [178 x 164] intentionally omitted <==**

**Figure 5: Transfer characteristics** 

**==> picture [178 x 164] intentionally omitted <==**

**Figure 6: Gate charge vs gate-source voltage** 

**==> picture [183 x 163] intentionally omitted <==**

**Figure 7: Static drain-source on-resistance** 

**==> picture [186 x 163] intentionally omitted <==**

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**Electrical characteristics** 

**Figure 8: Capacitance variations** 

**==> picture [183 x 164] intentionally omitted <==**

**Figure 10: Normalized on-resistance vs temperature** 

**==> picture [197 x 168] intentionally omitted <==**

**Figure 12: Maximum avalanche energy vs starting TJ** 

**==> picture [180 x 162] intentionally omitted <==**

**Figure 9: Normalized gate threshold voltage vs temperature** 

**==> picture [189 x 163] intentionally omitted <==**

**Figure 11: Normalized V(BR)DSS vs temperature** 

**==> picture [189 x 157] intentionally omitted <==**

**Figure 13: Source-drain diode forward characteristics** 

**==> picture [181 x 165] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 589] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 14: Test circuit for resistive load<br>Figure 15: Test circuit for gate charge<br>switching times<br>behavior<br>VDD<br>RL<br>VGS IG= CONST 100 Ω D.U.T.<br>pulse width + 2.7 kΩ<br>2200 VG<br>μF<br>47 kΩ<br>1 kΩ<br>AM01469v10<br>Figure 16: Test circuit for inductive load<br>switching and diode recovery times  Figure 17: Unclamped inductive load test<br>circuit<br>Figure 19: Switching time waveform<br>Figure 18: Unclamped inductive waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 TO-247 package information** 

**Figure 20: TO-247 package outline** 

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**Package information** 

**Table 10: TO-247 package mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.85||5.15|
|A1|2.20||2.60|
|b|1.0||1.40|
|b1|2.0||2.40|
|b2|3.0||3.40|
|c|0.40||0.80|
|D|19.85||20.15|
|E|15.45||15.75|
|e|5.30|5.45|5.60|
|L|14.20||14.80|
|L1|3.70||4.30|
|L2||18.50||
|ØP|3.55||3.65|
|ØR|4.50||5.50|
|S|5.30|5.50|5.70|



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**Revision history** 

## **5 Revision history** 

**Table 11: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|17-Oct-2016|1|First release.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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## Links

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- [Supplier page](https://es.farnell.com/en-ES/stmicroelectronics/stw7n90k5/mosfet-n-ch-900v-7a-to-247-3/dp/2729688)
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