# Power MOSFET, N Channel, 800 V, 46 A, 0.07 ohm, TO-247, Through Hole

![Product image](https://novapart.co/image/farnell:3367088/)

**URL**: https://novapart.co/products/STW65N80K5/power-mosfet-n-channel-800-v-46-a-007-ohm-to-247
**SKU**: STW65N80K5
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €8.5700
**Stock**: 500+
**Lead Time**: 127 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh K5 |
| Qualification | - |
| Power Dissipation | 446W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-247 |
| Drain Source Voltage Vds | 800V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 46A |
| Drain Source On State Resistance | 0.07ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3367088/)

## **STW65N80K5** 

## N-channel 800 V, 0.07 Ω typ., 46 A MDmesh™ K5 Power MOSFET in a TO-247 package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS**|**RDS(on) max.**|**ID**|**PTOT**|
|---|---|---|---|---|
|STW65N80K5|800 V|0.08 Ω|46 A|446 W|



- Industry’s lowest RDS(on) x area 

- Industry’s best figure of merit (FoM) 

**==> picture [62 x 53] intentionally omitted <==**

**----- Start of picture text -----**<br>
3<br>2<br>1<br>TO-247<br>**----- End of picture text -----**<br>


- Ultra low gate charge 

- 100% avalanche tested 

- Zener-protected 

## **Applications** 

- Switching applications 

**Figure 1: Internal schematic diagram** 

## **Description** 

This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STW65N80K5|65N80K5|TO-247|Tube|



This is information on a product in full production. 

_www.st.com_ 

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|**Contents**<br>**STW65N80K5**|**Contents**<br>**STW65N80K5**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>TO-247 package information ............................................................. 9|
|**5**|**Revision history ............................................................................ 11**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|±30|V|
|ID|Drain current (continuous) at Tcase= 25 °C|46|A|
||Drain current (continuous) at Tcase= 100 °C|30||
|IDM_(1)_|Drain current (pulsed)|184|A|
|PTOT|Total dissipation at Tcase= 25 °C|446|W|
|dv/dt_(2)_|Peak diode recoveryvoltage slope|4.5|V/ns|
|dv/dt_(3)_|MOSFET dv/dt ruggedness|50||
|Tstg|Storage temperature|-55 to 150|°C|
|Tj|Operating junction temperature|||



## **Notes:** 

(1) Pulse width is limited by safe operating area. 

(2) ISD ≤ 46 A, di/dt=100 A/μs; VDS peak < V(BR)DSS, VDD = 80% V(BR)DSS. 

(3) VDS ≤ 640 V 

## **Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|0.28|°C/W|
|Rthj-amb|Thermal resistancejunction-ambient|50||



## **Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR_(1)_|Avalanche current, repetitive or not repetitive|16|A|
|EAS_(2)_|Singlepulse avalanche energy|700|mJ|



## **Notes:** 

> (1) Pulse width limited by Tjmax. 

> (2) starting Tj = 25 °C, ID = IAR, VDD = 50 V. 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(Tcase = 25 °C unless otherwise specified) 

**Table 5: Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 1 mA|800|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= 800 V|||1|µA|
|||VGS= 0 V, VDS= 800 V,<br>Tcase= 125 °C|||50||
|IGSS|Gate-bodyleakage current|VDS= 0 V, VGS= ±20 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 100µA|3|4|5|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 23 A||0.07|0.08|Ω|



**Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0 V|-|3230|-|pF|
|Coss|Output capacitance||-|310|-||
|Crss|Reverse transfer<br>capacitance||-|3|-||
|Coss(eq)_(1)_|Equivalent output<br>capacitance|VDS= 0 to 640 V, VGS= 0 V|-|734|-|pF|
|RG|Intrinsicgate resistance|f = 1 MHz, ID= 0 A|-|1.9|-|Ω|
|Qg|Totalgate charge|VDD= 640 V, ID= 46 A,<br>VGS= 10 V (see_Figure 14:_<br>_"Test circuit for gate charge_<br>_behavior"_)|-|92|-|nC|
|Qgs|Gate-source charge||-|18|-||
|Qgd|Gate-drain charge||-|65|-||



## **Notes:** 

(1) Coss(eq) is defined as a constant equivalent capacitance giving the same charging time as COSS when VDS increases from 0 to 80% VDSS. 

**Table 7: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 400 V, ID= 23 A<br>RG= 4.7 Ω, VGS= 10 V (see<br>_Figure 13: "Test circuit for_<br>_resistive load switching times"_<br>and_Figure 18: "Switching time_<br>_waveform"_)|-|34|-|ns|
|tr|Rise time||-|30|-||
|td(off)|Turn-off delay time||-|90|-||
|tf|Fall time||-|10|-||



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**Electrical characteristics** 

**Table 8: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||46|A|
|ISDM_(1)_|Source-drain current<br>(pulsed)||-||184|A|
|VSD_(2)_|Forward on voltage|VGS= 0 V, ISD= 46 A|-||1.5|V|
|trr|Reverse recoverytime|ISD= 46 A, di/dt = 100 A/µs,<br>VDD= 60 V (see_Figure 15:_<br>_"Test circuit for inductive load_<br>_switching and diode recovery_<br>_times"_)|-|650||ns|
|Qrr|Reverse recoverycharge||-|20||µC|
|IRRM|Reverse recovery current||-|60||A|
|trr|Reverse recoverytime|ISD= 46 A, di/dt = 100 A/µs,<br>VDD= 60 V, Tj= 150 °C (see<br>_Figure 15: "Test circuit for_<br>_inductive load switching and_<br>_diode recovery times"_)|-|845||ns|
|Qrr|Reverse recoverycharge||-|28||µC|
|IRRM|Reverse recovery current||-|66||A|



## **Notes:** 

- (1) Pulse width is limited by safe operating area. 

- (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. 

**Table 9: Gate-source Zener diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)GSO|Gate-source breakdown voltage|IGS= ±1 mA, ID= 0 A|±30|-|-|V|



The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**==> picture [159 x 143] intentionally omitted <==**

**Figure 3: Thermal impedance** 

**==> picture [141 x 144] intentionally omitted <==**

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**----- Start of picture text -----**<br>
Figure 4: Output characteristics  Figure 5: Transfer characteristics<br>**----- End of picture text -----**<br>


**==> picture [409 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 6: Gate charge vs gate-source voltage  Figure 7: Static drain-source on-resistance<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

**==> picture [385 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 9: Normalized gate threshold voltage<br>Figure 8: Capacitance variations<br>vs temperature<br>**----- End of picture text -----**<br>


**==> picture [398 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 10: Normalized on-resistance vs  Figure 11: Normalized V(BR)DSS vs<br>temperature  temperature<br>**----- End of picture text -----**<br>


**Figure 12: Maximum avalanche energy vs temperature** 

**==> picture [158 x 142] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 375] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Test circuit for resistive load  Figure 14: Test circuit for gate charge<br>switching times  behavior<br>Figure 15: Test circuit for inductive load  Figure 16: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>**----- End of picture text -----**<br>


**==> picture [403 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 17: Unclamped inductive waveform  Figure 18: Switching time waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 TO-247 package information** 

**Figure 19: TO-247 package outline** 

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**Package information** 

**Table 10: TO-247 package mechanical data** 

|**Dim.**||**mm.**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.85||5.15|
|A1|2.20||2.60|
|b|1.0||1.40|
|b1|2.0||2.40|
|b2|3.0||3.40|
|c|0.40||0.80|
|D|19.85||20.15|
|E|15.45||15.75|
|e|5.30|5.45|5.60|
|L|14.20||14.80|
|L1|3.70||4.30|
|L2||18.50||
|ØP|3.55||3.65|
|ØR|4.50||5.50|
|S|5.30|5.50|5.70|



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**Revision history** 

## **5 Revision history** 

**Table 11: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|21-May-2015|1|First release.|
|02-Oct-2015|2|Text and formatting changes throughout document.<br>Datasheet status promoted from preliminary to production data.<br>On cover page:<br>- updated title description and Features table.<br>Updated sections - Electrical ratings and Electrical characteristics.<br>Added section - Electrical characteristics (curves).|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2015 STMicroelectronics – All rights reserved 

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- [Supplier page](https://es.farnell.com/stmicroelectronics/stw65n80k5/mosfet-n-ch-800v-46a-150deg-c/dp/3367088)
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