# Power MOSFET, N Channel, 950 V, 38 A, 0.11 ohm, TO-247, Through Hole

![Product image](https://novapart.co/image/farnell:2849687/)

**URL**: https://novapart.co/products/STW40N95K5/power-mosfet-n-channel-950-v-38-a-011-ohm-to-247
**SKU**: STW40N95K5
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €8.1200
**Stock**: 200+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:38A; Drain Source Voltage Vds:950V; On Resistance Rds(on):0.11ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; Power

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh K5 |
| Qualification | - |
| Power Dissipation | 450W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-247 |
| Drain Source Voltage Vds | 950V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 38A |
| Drain Source On State Resistance | 0.11ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2849687/)

## **STW40N95K5** 

## N-channel 950 V, 0.110 Ω typ., 38 A MDmesh™ K5 Power MOSFET in a TO-247 package 

Datasheet - production data 

## **Features** 

**Order code VDS RDS(on) max ID PTOT** STW40N95K5 950 V 0.130 Ω 38 A 450 W ~~——__—___—~~  Industry’s lowest RDS(on) x area 

**==> picture [61 x 49] intentionally omitted <==**

**----- Start of picture text -----**<br>
3<br>2<br>1<br>TO-247<br>**----- End of picture text -----**<br>


- Industry’s best figure of merit (FoM) 

- Ultra low gate charge 

- 100% avalanche tested 

- Zener-protected 

## **Applications** 

**Figure 1: Internal schematic diagram** 

- Switching applications 

## **Description** 

This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. 

||**Table 1: Device summary**|**Table 1: Device summary**||
|---|---|---|---|
|**Order code**|**Marking**|**Package**|**Packaging**|
|STW40N95K5|40N95K5|TO-247|Tube|



This is information on a product in full production. 

_www.st.com_ 

November 2014 DocID026447 Rev 2 

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|**Contents**<br>**STW40N95K5**|**Contents**<br>**STW40N95K5**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 9**|
|**4**|**Package mechanical data ............................................................. 10**|
||4.1<br>TO-247 package information ........................................................... 10|
|**5**|**Revision history ............................................................................ 12**|



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**Electrical ratings** 

## **1 Electrical ratings** 

## **Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate- source voltage|± 30|V|
|ID|Drain current (continuous) at TC= 25 °C|38|A|
|ID|Drain current (continuous) at TC= 100 °C|24|A|
|IDM_(1)_|Drain current (pulsed)|152|A|
|PTOT|Total dissipation at TC= 25 °C|450|W|
|IAR|Max current duringrepetitive or singlepulse avalanche|13|A|
|EAS|Single pulse avalanche energy<br>(starting TJ= 25 °C, ID= 13 A, VDD= 50 V)|700|mJ|
|dv/dt_(2)_|Peak diode recoveryvoltage slope|4.5|V/ns|
|dv/dt_(3)_|MOSFET dv/dt ruggedness|50|V/ns|
|Tj<br>Tstg|Operating junction temperature<br>Storage temperature|-55 to 150|°C|



## **Notes:** 

(1)Pulse width limited by safe operating area. 

(2)ISD ≤ 19 A, di/dt ≤ 100 A/µs, VDS(peak) ≤ V(BR)DSS. 

(3)VDS ≤ 760 V 

||**Table 3: Thermal data**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|Rthj-case|Thermal resistancejunction-case max|0.28|°C/W|
|Rthj-amb|Thermal resistance junction-amb max|50|°C/W|



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**STW40N95K5** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(Tcase =25 °C unless otherwise specified) 

||**Table 4:On /offstates**|**Table 4:On /offstates**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0, ID= 1 mA|950|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0, VDS= 950 V|||1|µA|
|||VGS= 0, VDS= 950 V,<br>TC=125 °C|||50|µA|
|IGSS|Gate-bodyleakage current|VDS=0, VGS= ± 20 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 100µA|3|4|5|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 19 A||0.110|0.130|Ω|



||**Table 5: Dynamic**|**Table 5: Dynamic**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|Ciss|Input capacitance|VGS=0, VDS=100 V, f=1 MHz|-|3300|-|pF|
|Coss|Output capacitance||-|250|-|pF|
|Crss|Reverse transfer<br>capacitance||-|2|-|pF|
|Co(tr)_(1)_|Equivalent capacitance time<br>related|VGS= 0, VDS= 0 to 760 V|-|398|-|pF|
|Co(er)_(2)_|Equivalent capacitance<br>energy related||-|142|-|pF|
|RG|Intrinsicgate resistance|f = 1 MHz, ID=0|-|5|-|Ω|
|Qg|Totalgate charge|VDD= 760 V, ID= 38 A<br>VGS=10 V<br>(see_Figure 16: "Gate charge_<br>_test circuit"_)|-|93|-|nC|
|Qgs|Gate-source charge||-|18.7|-|nC|
|Qgd|Gate-drain charge||-|63.4|-|nC|



## **Notes:** 

(1)Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

(2)energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 

|||**Table 6: Switching times**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|<br>**Max**|**Unit**|
|td(on)|Turn-on delay<br>time|VDD= 475 V, ID= 19 A,<br>RG= 4.7 Ω, VGS= 10 V<br>(see_Figure 15: "Switching times test_<br>_circuit for resistive load"_)|-<br>-<br>-<br>-|33.5|-|ns|
|tr|Rise time|||51|-|ns|
|td(off)|Turn-off-delay<br>time|||91.5|-|ns|
|tf|Fall time|||10|-|ns|



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**Electrical characteristics** 

|||**Table 7:Source draindiode**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max**|**Unit**|
|ISD|Source-drain current||-||38|A|
|ISDM_(1)_|Source-drain current<br>(pulsed)||-||152|A|
|VSD_(2)_|Forward on voltage|ISD= 38 A, VGS= 0|-||1.5|V|
|trr|Reverse recovery<br>time|ISD= 38 A, di/dt = 100 A/µs<br>VDD= 60 V<br>(see_Figure 18: " Unclamped_<br>_inductive load test circuit"_)|-|706||ns|
|Qrr|Reverse recovery<br>charge||-|22||µC|
|IRRM|Reverse recovery<br>current||-|62||A|
|trr|Reverse recovery<br>time|ISD= 38 A, di/dt = 100 A/µs<br>VDD= 60 V TJ= 150 °C<br>(see_Figure 18: " Unclamped_<br>_inductive load test circuit"_)|-|886||ns|
|Qrr|Reverse recovery<br>charge||-|28.2||µC|
|IRRM|Reverse recovery<br>current||-|64||A|



## **Notes:** 

(1)Pulse width limited by safe operating area. 

(2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

||**Table 8: Gate-source Zener diode**|**Table 8: Gate-source Zener diode**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min**|**Typ.**|**Max.**|**Unit**|
|V(BR)GSO|Gate-source breakdown voltage|IGS= ± 1mA, ID=0|30|-|-|V|



The built-in back-to-back Zener diodes have specifically been designed to enhance the device's ESD capability. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. 

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**STW40N95K5** 

**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

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**----- Start of picture text -----**<br>
Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
AM09125v1<br>K<br>δ=0.5<br>0.2<br>0.1<br>0.05<br>10-1<br>0.02<br>0.01 Zth=k R thj-c<br>δ=tp/ t<br>Single pulse<br>tp<br>1010-2 -4 10-3 10-2 10t -1 tp [(s)]<br>**----- End of picture text -----**<br>


**Figure 4: Output characteristics** 

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**Figure 5: Transfer characteristics** 

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**Figure 6: Gate charge vs gate-source voltage** 

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**Figure 7: Static drain-source on-resistance** 

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**Electrical characteristics** 

**Figure 8: Capacitance variations** 

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**Figure 9: Normalized gate threshold voltage vs temperature** 

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**----- Start of picture text -----**<br>
Figure 10: Normalized on-resistance  Figure 11: Normalized V(BR)DSS vs temperature<br>GIPD121120141039FSR GIPD121120141041FSR<br>RDS(on) V(BR)DSS<br>(norm) (norm)<br>2.6 1.12<br>VGS= 10V ID= 1mA<br>2.2 1.08<br>1.8 1.04<br>1.4 1.00<br>1 0.96<br>0.6 0.92<br>0.2 0.88<br>-50 0 50 100 Tj(°C) -50 0 50 100 Tj(°C)<br>**----- End of picture text -----**<br>


**Figure 12: Output capacitance stored energy** 

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**Figure 13: Source-drain diode forward characteristics** 

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**Electrical characteristics** 

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**----- Start of picture text -----**<br>
Figure 14: Maximum avalanche energy vs T J<br>GIPD141120141040FSR<br>EAS<br>(mJ)<br>600<br>400<br>Single pulse<br>ID= 13A<br>200<br>VDD= 50V<br>0<br>-50 0 50 100 Tj(°C)<br>**----- End of picture text -----**<br>


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**Test circuits** 

## **3** 

## **Test circuits** 

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**----- Start of picture text -----**<br>
Figure 15: Switching times test circuit for<br>resistive load<br>Figure 16: Gate charge test circuit<br>; vo<br>12V<br> 1 47kQ 4 tka<br>100nF<br>RL 2200 3.3<br>UF HF Vp IG = CONST<br>Ves Vb Vi=20V=V GMAX2200 1002 ; D.U.T.<br>| * Re D U T . T AF 2.7kQ vvG<br>JL gp4 4 47kQ<br>PW | 1kQ ‘) AM01469v1<br>AMo1468v1<br>Figure 17:  Test circuit for inductive load  Figure 18:  Unclamped inductive load test<br>switching and diode recovery times  circuit<br>**----- End of picture text -----**<br>


**==> picture [381 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 19:  Unclamped inductive waveform  Figure 20:  Switching time waveform<br>**----- End of picture text -----**<br>


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**Package mechanical** data 

## **4 Package mechanical data** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 TO-247 package information** 

**Figure 21: TO-247 drawing** 

~~©~~ 10/13 DocID026447 Rev 2 

**STW40N95K5** 

**Package mechanical** data 

||**Table 9: TO-247 mechanical data**|**Table 9: TO-247 mechanical data**||
|---|---|---|---|
|||**mm.**||
|**Dim.**||||
||**Min.**|**Typ.**|**Max.**|
|||||
|A|4.85||5.15|
|A1|2.20||2.60|
|b|1.0||1.40|
|b1|2.0||2.40|
|b2|3.0||3.40|
|c|0.40||0.80|
|D|19.85||20.15|
|E|15.45||15.75|
|e|5.30|5.45|5.60|
|L|14.20||14.80|
|L1|3.70||4.30|
|L2||18.50||
|ØP|3.55||3.65|
|ØR|4.50||5.50|
|S|5.30|5.50|5.70|



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**Revision history** 

## **5 Revision history** 

||**Table 10: Document revision history**|**Table 10: Document revision history**|
|---|---|---|
|**Date**|**Revision**|**Changes**|
|03-Jun-2014|1|First release.|
|14-Nov-2014|2|Document status promoted from preliminary to production data.<br>Added_Section 2.1: "Electrical characteristics (curves)"_.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2014 STMicroelectronics – All rights reserved 

DocID026447 Rev 2 

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