# Power MOSFET, N Channel, 650 V, 32 A, 0.087 ohm, TO-247, Through Hole

![Product image](https://novapart.co/image/farnell:3129870/)

**URL**: https://novapart.co/products/STW40N65M2/power-mosfet-n-channel-650-v-32-a-0087-ohm-to-247
**SKU**: STW40N65M2
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €2.1600
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:32A; Drain Source Voltage Vds:650V; On Resistance Rds(on):0.087ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3V

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh M2 |
| Qualification | - |
| Power Dissipation | 250W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-247 |
| Drain Source Voltage Vds | 650V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 32A |
| Drain Source On State Resistance | 0.087ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3129870/)

## **STW40N65M2** 

N-channel 650 V, 0.087 Ω typ., 32 A MDmesh™ M2 Power MOSFET in a TO-247 package 

Datasheet - production data 

**Features** 

**Order code VDS RDS(on) max. ID** STW40N65M2 650 V 0.099 Ω 32 A ~~a~~ 

**==> picture [61 x 53] intentionally omitted <==**

**----- Start of picture text -----**<br>
3<br>2<br>1<br>TO-247<br>**----- End of picture text -----**<br>


- Extremely low gate charge 

- • Excellent output capacitance (COSS) profile • 100% avalanche tested 

- Zener-protected 

## **Applications** 

- Switching applications 

**Figure 1: Internal schematic diagram** 

## **Description** 

This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. 

||**Table 1: Device summary**|**Table 1: Device summary**||
|---|---|---|---|
|**Order code**|**Marking**|**Package**|**Packaging**|
|STW40N65M2|40N65M2|TO-247|Tube|



This is information on a product in full production. 

_www.st.com_ 

February 2015 

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|**Contents**<br>**STW40N65M2**|**Contents**<br>**STW40N65M2**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.2<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>TO-247 package information ............................................................. 9|
|**5**|**Revision history ............................................................................ 11**|



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**Electrical ratings** 

## **1 Electrical ratings** 

## **Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|± 25|V|
|ID|Drain current (continuous) at TC= 25 °C|32|A|
|ID|Drain current (continuous) at TC= 100 °C|20|A|
|IDM<br>_(1)_|Drain current (pulsed)|128|A|
|PTOT|Total dissipation at TC= 25 °C|250|W|
|dv/dt_(2)_|Peak diode recoveryvoltage slope|15|V/ns|
|dv/dt_(3)_|MOSFET dv/dt ruggedness|50|V/ns|
|Tstg|Storage temperature|- 55 to 150|°C|
|Tj|Max. operating junction temperature|150||



## **Notes:** 

(1) Pulse width limited by safe operating area. 

(2) ISD ≤ 32 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD = 400 V 

(3) VDS ≤ 520 V 

||**Table 3: Thermal data**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|Rthj-case|Thermal resistance junction-case max|0.5|°C/W|
|Rthj-amb|Thermal resistancejunction-ambient max|50|°C/W|



||**Table 4: Avalanche characteristics**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|IAR|Avalanche current, repetitive or not repetitive (pulse width<br>limited byTjmax)|3|A|
|EAS|Single pulse avalanche energy (starting Tj= 25 °C,<br>ID= IAR, VDD= 50 V)|820|mJ|



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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC= 25 °C unless otherwise specified) 

|||**Table 5: On/offstates**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 1 mA|650|||V|
|IDSS|Zero gate voltage Drain<br>current|VGS= 0 V, VDS= 650 V|||1|µA|
|||VGS= 0 V, VDS= 650 V,<br>TC= 125 °C|||100|µA|
|IGSS|Gate-body leakage current|VDS= 0 V, VGS= ± 25 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|2|3|4|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 16 A||0.087|0.099|Ω|



|||**Table 6: Dynamic**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0 V|-|2355|-|pF|
|Coss|Output capacitance||-|102|-|pF|
|Crss|Reverse transfer<br>capacitance||-|2.7|-|pF|
|Coss eq.<br>_(1)_|Equivalent output<br>capacitance|VDS= 0 V to 520 V, VGS= 0 V|-|380|-|pF|
|RG|Intrinsicgate resistance|f = 1 MHz open drain|-|4.5|-|Ω|
|Qg|Totalgate charge|VDD= 520 V, ID= 32 A,<br>VGS= 10 V (see_Figure 15:_<br>_"Gate charge test circuit"_)|-|56.5|-|nC|
|Qgs|Gate-source charge||-|8|-|nC|
|Qgd|Gate-drain charge||-|24|-|nC|



## **Notes:** 

(1)Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

||**Table 7:Switching times**|**Table 7:Switching times**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|td(on)|Turn-on delay time|VDD= 325 V, ID= 16 A<br>RG= 4.7 Ω, VGS= 10 V (see<br>_Figure 14: "Switching times_<br>_test circuit for resistive load"_<br>and_Figure 19: "Switching time_<br>_waveform"_)|-|15|-|ns|
|tr|Rise time||-|10|-|ns|
|td(off)|Turn-off-delay time||-|96.5|-|ns|
|tf|Fall time||-|12|-|ns|



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**Electrical characteristics** 

|||**Table 8: Source draindiode**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|ISD|Source-drain<br>current||-||32|A|
|ISDM<br>_(1)_|Source-drain<br>current<br>(pulsed)||-||128|A|
|VSD<br>_(2)_|Forward on<br>voltage|VGS= 0 V, ISD= 32 A|-||1.6|V|
|trr|Reverse<br>recovery time|ISD= 32 A, di/dt = 100 A/µs, VDD= 60 V<br>(see_Figure 16: " Test circuit for inductive_<br>_load switching and diode recovery times"_)|-|468||ns|
|Qrr|Reverse<br>recovery<br>charge||-|8.7||µC|
|IRRM|Reverse<br>recovery<br>current||-|37.5||A|
|trr|Reverse<br>recovery time|ISD= 32 A, di/dt = 100 A/µs, VDD= 60 V,<br>Tj= 150 °C (see_Figure 16: " Test circuit_<br>_for inductive load switching and diode_<br>_recovery times"_)|-|610||ns|
|Qrr|Reverse<br>recovery<br>charge||-|11.7||µC|
|IRRM|Reverse<br>recovery<br>current||-|39||A|



## **Notes:** 

(1) Pulse width is limited by safe operating area 

(2) Pulse test: pulse duration = 300 µs, duty cycle 1.5% 

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**Electrical characteristics** 

## **2.2 Electrical characteristics (curves)** 

**==> picture [416 x 344] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>ID GIPD030220151540ALS K GC18460<br>(A) δ=0.5<br>0.2<br>100<br>0.1<br>10µs 10 [-1]<br>0.05<br>10 100µs 0.02<br>1ms<br>10ms 10 [-2] 0.01 Zth= K*Rthj-c<br>1 Tj = 150 °C Single pulse δ= tp/ Ƭ<br>Single pulseTc = 25 °C t p  Ƭ<br>0.1 10 [-3]<br>0.1 1 10 100 VDS(V) 10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] tp (s)<br>Figure 4: Output characteristics  Figure 5: Transfer characteristics<br>ID GIPG300120151500ALS ID GIPG300120151715ALS<br>(A)70 V GS  = 6,7,8,9,10 V (A)70<br>V GS [ = 5 V]<br>60 60<br>50 50 V GS = 20 V<br>40<br>40<br>30<br>30 V GS  = 4 V<br>20<br>20<br>10<br>10<br>0<br>00 4 8 12 16 20 24 VDS (V) 0 2 4 6 8 VGS (V)<br>DS(on)<br>Operation in this area islimited by max R<br>**----- End of picture text -----**<br>


**Figure 6: Normalized gate threshold voltage vs temperature** 

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**Figure 7: Normalized V(BR)DSS vs temperature** 

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**Electrical characteristics** 

**Figure 8: Static drain-source on-resistance** 

**==> picture [159 x 145] intentionally omitted <==**

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**----- Start of picture text -----**<br>
Figure 9: Normalized on-resistance vs.<br>temperature<br>**----- End of picture text -----**<br>


**Figure 10: Gate charge vs. gate-source Figure 11: Capacitance variations voltage** 

**==> picture [155 x 146] intentionally omitted <==**

**==> picture [150 x 147] intentionally omitted <==**

**Figure 12: Output capacitance stored energy** 

**==> picture [152 x 143] intentionally omitted <==**

**Figure 13: Source-drain diode forward characteristics** 

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**Test circuits** 

## **3 Test circuits** 

**Figure 14: Switching times test circuit for resistive Figure 15: Gate charge test circuit load** 

**==> picture [207 x 90] intentionally omitted <==**

**==> picture [216 x 144] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>12 V 47 kΩ<br>1 kΩ<br>100 nF<br>I G = CONST<br>Vi ≤ V GS 100 Ω D.U.T.<br>2.7 k Ω VG<br>2200 μ F<br>47 kΩ<br>1 kΩ<br>PW<br>AM01469v1<br>**----- End of picture text -----**<br>


**Figure 16:  Test circuit for inductive load switching and diode recovery times** 

**==> picture [212 x 126] intentionally omitted <==**

**----- Start of picture text -----**<br>
A A A<br>D<br>FAST L=100 µH<br>G D.U.T. DIODE<br>S B 3.3 1000<br>25 Ω B B D µF µF VDD<br>G D.U.T.<br>RG S<br>AM01470v1<br>**----- End of picture text -----**<br>


**Figure 17:  Unclamped inductive load test circuit** 

**==> picture [207 x 146] intentionally omitted <==**

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**----- Start of picture text -----**<br>
Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform<br>V(BR)DSS t on toff<br>t d(on) t r t d(off) t f<br>VD<br>90% 90%<br>I DM<br>10%<br>I D 0 10% VDS<br>VDD VDD<br>90%<br>VGS<br>AM01472v1 0 10% AM01473v1<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 TO-247 package information** 

**Figure 20: TO-247 drawing** 

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**==> picture [33 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
0075325_H<br>**----- End of picture text -----**<br>


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**Package information** 

|**formation**|||**STW40N65M2**|
|---|---|---|---|
||**Table 9: TO-247 mechanical data**|||
|**Dim.**||**mm.**||
||**Min.**|**Typ.**|**Max.**|
|A|4.85||5.15|
|A1|2.20||2.60|
|b|1.0||1.40|
|b1|2.0||2.40|
|b2|3.0||3.40|
|c|0.40||0.80|
|D|19.85||20.15|
|E|15.45||15.75|
|e|5.30|5.45|5.60|
|L|14.20||14.80|
|L1|3.70||4.30|
|L2||18.50||
|ØP|3.55||3.65|
|ØR|4.50||5.50|
|S|5.30|5.50|5.70|



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**Revision history** 

## **5 Revision history** 

|**Revision history**|**Revision history**|**Revision history**|
|---|---|---|
|**Table 10: Document revision history**|||
|**Date**|**Revision**|**Changes**|
|09-Feb-2014|1|First release.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2015 STMicroelectronics – All rights reserved 

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