# Power MOSFET, N Channel, 800 V, 24 A, 0.15 ohm, TO-247, Through Hole

![Product image](https://novapart.co/image/farnell:3367082/)

**URL**: https://novapart.co/products/STW30N80K5/power-mosfet-n-channel-800-v-24-a-015-ohm-to-247
**SKU**: STW30N80K5
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €3.6300
**Stock**: 200+
**Lead Time**: 127 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh K5 |
| Qualification | - |
| Power Dissipation | 250W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-247 |
| Drain Source Voltage Vds | 800V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 24A |
| Drain Source On State Resistance | 0.15ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3367082/)

## **STW30N80K5** 

N-channel 800 V, 0.15 Ω typ., 24 A, MDmesh™ K5 Power MOSFET in a TO-247 package 

Datasheet - production data 

## **Features table** 

**Order code VDS RDS(on) max. ID** STW30N80K5 800 V 0.18 Ω 24 A ~~Se~~ 

## **Features** 

**==> picture [62 x 53] intentionally omitted <==**

**----- Start of picture text -----**<br>
3<br>2<br>1<br>TO-247<br>**----- End of picture text -----**<br>


- Industry’s lowest RDS(on) x area 

- Industry’s best FoM (figure of merit) 

- Ultra-low gate charge 

- 100% avalanche tested 

- Zener-protected 

**Figure 1: Internal schematic diagram** 

## **Applications** 

- Switching applications 

## **Description** 

This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STW30N80K5|30N80K5|TO-247|Tube|



This is information on a product in full production. 

_www.st.com_ 

March 2016 DocID028638 Rev 2 

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|**Contents**<br>**STW30N80K5**|**Contents**<br>**STW30N80K5**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 9**|
|**4**|**Package information ..................................................................... 10**|
||4.1<br>TO-247 package information ........................................................... 10|
|**5**|**Revision history ............................................................................ 12**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|800|V|
|VGS|Gate-source voltage|± 30|V|
|ID|Drain current (continuous) at TC= 25 °C|24|A|
|ID|Drain current (continuous) at TC= 100 °C|15|A|
|IDM_(1)_|Drain current (pulsed)|96|A|
|PTOT|Total dissipation at TC= 25 °C|250|W|
|dv/dt_(2)_|Peak diode recoveryvoltage slope|4.5|V/ns|
|dv/dt_(3)_|MOSFET dv/dt ruggedness|50||
|Tstg|Storage temperature range|- 55 to 150|°C|
|Tj|Operating junction temperature range|||



## **Notes:** 

(1)Pulse width limited by safe operating area 

(2)ISD< 24 A, di/dt < 100 A/µs, VDSpeak < V (BR)DSS, VDD= 80% V(BR)DSS 

(3)VDS= 640 V 

## **Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|0.5|°C/W|
|Rthj-amb|Thermal resistance junction-ambient|50|°C/W|



**Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR|Avalanche current, repetitive or not repetitive<br>(pulse width limited byTjmax.)|8|A|
|EAS|Single pulse avalanche energy<br>(starting Tj= 25 °C, ID= IAR, VDD= 50 V)|440|mJ|



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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TCASE = 25 °C unless otherwise specified) 

**Table 5: On/off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source<br>breakdown voltage|ID= 1 mA, VGS= 0 V|800|||V|
|IDSS|Zero gate voltage<br>drain current|VGS= 0 V, VDS= 800 V|||1|µA|
|||VGS= 0 V, VDS= 800 V, TC=<br>125 °C_(1)_|||50|µA|
|IGSS|Gate source leakage<br>current|VDS= 0 V, VGS= ± 20 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 100µA|3|4|5|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 12 A||0.15|0.18|Ω|



## **Notes:** 

(1)Defined by design, not subject to production test 

**Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz, VGS= 0 V|-|1530|-|pF|
|Coss|Output capacitance||-|145|-|pF|
|Crss|Reverse transfer<br>capacitance||-|1.2|-|pF|
|Co(er)_(1)_|Equivalent capacitance<br>energyrelated|VGS= 0 V,<br>VDS= 0 to 640 V|-|91|-|pF|
|Co(tr)_(2)_|Equivalent capacitance<br>time related||-|244|-|pF|
|Qg|Totalgate charge|VDD= 640 V, ID= 24 A,<br>VGS= 10 V<br>(See_Figure 16: "Test circuit_<br>_for gate charge behavior"_)|-|43|-|nC|
|Qgs|Gate-source charge||-|12.8|-|nC|
|Qgd|Gate-drain charge||-|24.2|-|nC|
|Rg|Gate input resistance|f =1 MHz, ID= 0 A|-|3.5|-|Ω|



## **Notes:** 

(1)Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 

(2)Time related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 

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**Electrical characteristics** 

**Table 7: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDS= 400 V, ID= 12 A, RG= 4.7 Ω<br>VGS= 10 V<br>(See_Figure 15: "Test circuit for_<br>_resistive load switching times"_and<br>_Figure 20: "Switching time_<br>_waveform"_)|-|21|-|ns|
|tr|Rise time||-|15|-|ns|
|td(off)|Turn-off delaytime||-|100|-|ns|
|tf|Fall time||-|13.5|-|ns|



**Table 8: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain<br>current||-||24|A|
|ISDM_(1)_|Source-drain<br>current (pulsed)||-||96|A|
|VSD_(2)_|Forward on<br>voltage|ISD= 24 A, VGS= 0 V|-||1.5|V|
|trr|Reverse recovery<br>time|ISD= 24 A, di/dt = 100 A/µs<br>VDD= 60 V<br>(See_Figure 17: "Test circuit for_<br>_inductive load switching and diode_<br>_recovery times"_)|-|555||ns|
|Qrr|Reverse recovery<br>charge||-|9.95||µC|
|IRRM|Reverse recovery<br>current||-|36||A|
|trr|Reverse recovery<br>time|ISD= 24 A, di/dt = 100 A/µs<br>VDD= 60 V, Tj= 150 °C<br>(See_Figure 17: "Test circuit for_<br>_inductive load switching and diode_<br>_recovery times"_)|-|765||ns|
|Qrr|Reverse recovery<br>charge||-|13.2||µC|
|IRRM|Reverse recovery<br>current||-|34.5||A|



## **Notes:** 

(1)Pulse width limited by safe operating area. 

(2)Pulsed: pulse duration = 300 µs, duty cycle 1.5%. 

**Table 9: Gate-source Zener diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)GSO|Gate-source breakdown voltage|IGS= ±1 mA, ID= 0 A|30|-|-|V|



The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**==> picture [174 x 143] intentionally omitted <==**

**==> picture [164 x 156] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 3: Thermal impedance<br>K GC18460_ZTH<br>δ=0.5<br>δ=0.2<br>0.1<br>10 [-1] 0.05<br>0.02<br>0.01<br>10 [-2] Single pulse<br>10-3<br>10-5 10 [-4] 10 [-3] 10-2 10 [-1] tp(s)<br>**----- End of picture text -----**<br>


**Figure 4: Output characteristics Figure 5: Transfer characteristics** 

**==> picture [156 x 142] intentionally omitted <==**

**==> picture [157 x 142] intentionally omitted <==**

**Figure 6: Gate charge vs gate-source voltage** 

**==> picture [161 x 143] intentionally omitted <==**

**Figure 7: Static drain-source on-resistance** 

**==> picture [162 x 143] intentionally omitted <==**

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**Electrical characteristics** 

**==> picture [389 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 9: Normalized gate threshold voltage<br>Figure 8: Capacitance variations<br>vs temperature<br>**----- End of picture text -----**<br>


**==> picture [416 x 375] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 10: Normalized on-resistance vs  Figure 11: Normalized V(BR)DSS vs<br>temperature  temperature<br>Figure 12: Maximum avalanche energy vs  Figure 13: Source-drain diode forward<br>starting TJ  characteristics<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

**==> picture [195 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 14: Output capacitance stored energy<br>**----- End of picture text -----**<br>


**==> picture [163 x 142] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 622] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 15: Test circuit for resistive load  Figure 16: Test circuit for gate charge<br>switching times  behavior<br>Figure 17: Test circuit for inductive load<br>Figure 18: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>Figure 20: Switching time waveform<br>Figure 19: Unclamped inductive waveform<br>DocID028638 Rev 2  9/13<br>**----- End of picture text -----**<br>


**STW30N80K5** 

**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 TO-247 package information** 

**Figure 21: TO-247 package outline** 

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**Package information** 

**Table 10: TO-247 package mechanical data** 

|**Dim.**||**mm.**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.85||5.15|
|A1|2.20||2.60|
|b|1.0||1.40|
|b1|2.0||2.40|
|b2|3.0||3.40|
|c|0.40||0.80|
|D|19.85||20.15|
|E|15.45||15.75|
|e|5.30|5.45|5.60|
|L|14.20||14.80|
|L1|3.70||4.30|
|L2||18.50||
|ØP|3.55||3.65|
|ØR|4.50||5.50|
|S|5.30|5.50|5.70|



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**Revision history** 

## **5 Revision history** 

**Table 11: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|03-Dec-2015|1|First release.|
|21-Mar-2016|2|Document status promoted from preliminary to production data.<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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- [Supplier page](https://es.farnell.com/stmicroelectronics/stw30n80k5/mosfet-n-ch-800v-24a-150deg-c/dp/3367082)
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