# Power MOSFET, N Channel, 600 V, 20 A, 0.135 ohm, TO-247, Through Hole
**URL**: https://novapart.co/products/STW26NM60N/power-mosfet-n-channel-600-v-20-a-0135-ohm-to-247
**SKU**: STW26NM60N
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €2.6200
**Stock**: 1000+
**Lead Time**: 127 days (indicative)
## Description
Transistor Polarity:N Channel; Continuous Drain Current Id:20A; Drain Source Voltage Vds:600V; On Resistance Rds(on):0.135ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3V; Powe
## Specifications
| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 140W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-247 |
| Drain Source Voltage Vds | 600V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 20A |
| Drain Source On State Resistance | 0.135ohm |
| Gate Source Threshold Voltage Max | 3V |
## Datasheet
📄 [Download PDF](https://novapart.co/datasheet/farnell:2098389/)
## **STW26NM60N**
N-channel 600 V, 0.135 Ω typ., 20 A MDmesh™ II Power MOSFET in a TO-247 package
Datasheet - production data
## **Features**
**Order code VDS RDS(on) max ID** STW26NM60N 600 V 0.165 Ω 20 A ~~——~~
- 100% avalanche tested
- Low input capacitance and gate charge
**==> picture [62 x 54] intentionally omitted <==**
**----- Start of picture text -----**
3
2
1
TO-247
**----- End of picture text -----**
- Low gate input resistance
## **Applications**
- Switching applications
## **Description**
This device is an N-channel Power MOSFET developed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters.
**Figure 1: Internal schematic diagram**
D(2) company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. G(1) S(3) AM01475v1_noTab_noZen **Table 1: Device summary Order code Marking Package Packaging** STW26NM60N 26NM60N TO-247 Tube ~~_~~
This is information on a product in full production.
_www.st.com_
December 2016 DocID025246 Rev 2
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|**Contents**
**STW26NM60N **|**Contents**
**STW26NM60N **|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1
Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1
TO-247 package information ............................................................. 9|
|**5**|**Revision history ............................................................................ 11**|
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**Electrical ratings**
## **1 Electrical ratings**
**Table 2: Absolute maximum ratings**
|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|600|V|
|VGS|Gate-source voltage|±30|V|
|ID|Drain current (continuous) at TC= 25 °C|20|A|
|ID|Drain current (continuous) at TC= 100 °C|12.6|A|
|IDM_(1)_|Drain current (pulsed)|80|A|
|PTOT|Total dissipation at TC= 25 °C|140|W|
|dv/dt_(2)_|Peak diode recoveryvoltage slope|15|V/ns|
|Tstg|Storage temperature range|-55 to 150|°C|
|Tj|Operating junction temperature range|||
## **Notes:**
(1)Pulse width limited by safe operating area.
(2)ISD ≤ 20 A, di/dt ≤ 400 A/µs, VDS(peak) ≤ V(BR)DSS, VDD ≤ 80% V(BR)DSS
## **Table 3: Thermal data**
|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|0.89|°C/W|
|Rthj-amb|Thermal resistancejunction-ambient|50|°C/W|
**Table 4: Avalanche characteristics**
|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAS|Single pulse avalanche current (pulse width limited by
Tjmax)|6|A|
|EAS|Single pulse avalanche energy (starting TJ=25 °C, ID=IAS,
VDD=50 V)|610|mJ|
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**Electrical characteristics**
## **2 Electrical characteristics**
(TCASE = 25 °C unless otherwise specified)
**Table 5: On/off states**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source
breakdown voltage|ID= 1 mA, VGS= 0 V|600|||V|
|IDSS|Zero gate voltage drain
current|VGS= 0 V, VDS= 600 V|||1|µA|
|||VGS= 0 V, VDS= 600 V,
TC= 125 °C_(1)_|||100||
|IGSS|Gate-body leakage
current|VDS= 0 V, VGS= ±25 V|||±0.1|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|2|3|4|V|
|RDS(on)|Static drain-source on-
resistance|VGS= 10 V, ID= 10 A||0.135|0.165|Ω|
## **Notes:**
(1)Defined by design, not subject to production test.
**Table 6: Dynamic**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 50 V, f = 1 MHz,
VGS= 0 V|-|1800|-|pF|
|Coss|Output capacitance||-|115|-|pF|
|Crss|Reverse transfer
capacitance||-|6|-|pF|
|Coss eq._(1)_|Equivalent output
capacitance|VGS= 0 V, VDS= 0 to 480 V|-|310|-|pF|
|Qg|Totalgate charge|VDD= 480 V, ID= 20 A,
VGS= 10 V
(see_Figure 14: "Test circuit for_
_gate charge behavior"_)|-|60|-|nC|
|Qgs|Gate-source charge||-|8.5|-|nC|
|Qgd|Gate-drain charge||-|30|-|nC|
|RG|Gate input resistance|f=1 MHz, ID=0 A|-|2.8|-|Ω|
## **Notes:**
(1)Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDS
**Table 7: Switching times**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 300 V, ID= 10 A,
RG= 4.7 Ω, VGS= 10 V
(see_Figure 13: "Test circuit for_
_resistive load switching times"_
and_Figure 18: "Switching time_
_waveform"_)|-|13|-|ns|
|tr|Rise time||-|25|-|ns|
|td(off)|Turn-off delaytime||-|85|-|ns|
|tf|Fall time||-|50|-|ns|
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**Electrical characteristics**
**Table 8: Source-drain diode**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||20|A|
|ISDM_(1)_|Source-drain current
(pulsed)||-||80|A|
|VSD_(2)_|Forward on voltage|ISD= 20 A, VGS= 0 V|-||1.5|V|
|trr|Reverse recoverytime|ISD= 20 A, di/dt = 100 A/µs
VDD= 60 V
(see_Figure 15: "Test circuit for_
_inductive load switching and_
_diode recovery times"_)|-|370||ns|
|Qrr|Reverse recoverycharge||-|5.8||µC|
|IRRM|Reverse recovery current||-|31.6||A|
|trr|Reverse recoverytime|ISD= 20 A, di/dt = 100 A/µs
VDD= 60 V, Tj= 150 °C
(see_Figure 15: "Test circuit for_
_inductive load switching and_
_diode recovery times"_)|-|450||ns|
|Qrr|Reverse recoverycharge||-|7.5||µC|
|IRRM|Reverse recovery current||-|32.5||A|
## **Notes:**
(1)Pulse width limited by safe operating area.
(2)Pulsed: pulse duration = 300 µs, duty cycle 1.5%
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## **Electrical characteristics**
## **2.1 Electrical characteristics (curves)**
**Figure 2: Safe operating area**
**==> picture [128 x 10] intentionally omitted <==**
**----- Start of picture text -----**
Figure 3: Thermal impedance
**----- End of picture text -----**
**==> picture [379 x 11] intentionally omitted <==**
**----- Start of picture text -----**
Figure 4: Output characteristics Figure 5: Transfer characteristics
**----- End of picture text -----**
**==> picture [186 x 29] intentionally omitted <==**
**----- Start of picture text -----**
Figure 6: Static drain-source on-resistance
RDs(on) AMO
W
**----- End of picture text -----**
**Figure 7: Gate charge vs gate-source voltage**
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**Electrical characteristics**
**Figure 8: Capacitance variations**
**Figure 9: Normalized gate threshold voltage vs temperature**
**Figure 10: Normalized on-resistance vs temperature**
**Figure 11: Source-drain diode forward characteristics**
**Figure 12: Normalized V(BR)DSS vs temperature**
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**Test circuits**
## **3 Test circuits**
**==> picture [416 x 375] intentionally omitted <==**
**----- Start of picture text -----**
Figure 13: Test circuit for resistive load Figure 14: Test circuit for gate charge
switching times behavior
Figure 15: Test circuit for inductive load Figure 16: Unclamped inductive load test
switching and diode recovery times circuit
**----- End of picture text -----**
**==> picture [403 x 169] intentionally omitted <==**
**----- Start of picture text -----**
Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform
**----- End of picture text -----**
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**Package information**
## **4 Package information**
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark.
## **4.1 TO-247 package information**
**Figure 19: TO-247 package outline**
**==> picture [406 x 483] intentionally omitted <==**
**----- Start of picture text -----**
0075325_8
**----- End of picture text -----**
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**Package information**
**Table 9: TO-247 package mechanical data**
|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.85||5.15|
|A1|2.20||2.60|
|b|1.0||1.40|
|b1|2.0||2.40|
|b2|3.0||3.40|
|c|0.40||0.80|
|D|19.85||20.15|
|E|15.45||15.75|
|e|5.30|5.45|5.60|
|L|14.20||14.80|
|L1|3.70||4.30|
|L2||18.50||
|ØP|3.55||3.65|
|ØR|4.50||5.50|
|S|5.30|5.50|5.70|
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**Revision history**
## **5 Revision history**
**Table 10: Document revision history**
|**Date**|**Revision**|**Changes**|
|---|---|---|
|07-Jul-2016|1|First release.|
|12-Dec-2016|2|Modified_Table 6: "Dynamic"_and_Table 8: "Source-drain diode"_
Modified_Section 2.1: "Electrical characteristics (curves)"_
Minor text changes|
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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY**
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
- © 2016 STMicroelectronics – All rights reserved
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## Links
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