# Power MOSFET, N Channel, 650 V, 5 A, 0.98 ohm, TO-251, Through Hole

![Product image](https://novapart.co/image/farnell:2460389/)

**URL**: https://novapart.co/products/STU7N65M2/power-mosfet-n-channel-650-v-5-a-098-ohm-to-251
**SKU**: STU7N65M2
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.5040
**Stock**: 500+
**Lead Time**: 2 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:5A; Drain Source Voltage Vds:650V; On Resistance Rds(on):0.98ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3V;

## Specifications

| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 60W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-251 |
| Drain Source Voltage Vds | 650V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 5A |
| Drain Source On State Resistance | 0.98ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2460389/)

## **STP7N65M2, STU7N65M2** 

N-channel 650 V, 0.98 Ω typ., 5 A MDmesh™ M2 Power MOSFETs in TO-220 and IPAK packages Datasheet - production data 

## **Features** 

**==> picture [160 x 103] intentionally omitted <==**

**----- Start of picture text -----**<br>
TAB<br>TAB TO-220 1 [2 3]<br>3<br>IPAK 1 2<br>**----- End of picture text -----**<br>


|**Order code**|**VDS**|**RDS(on)**<br>**max**|**ID**|
|---|---|---|---|
|STP7N65M2|650 V|1.15 Ω|5 A|
|STU7N65M2|650 V|1.15 Ω|5 A|



- Extremely low gate charge 

- Excellent output capacitance (Coss) profile 

- 100% avalanche tested 

- Zener-protected 

**Figure 1: Internal schematic diagram** 

## **Applications** 

- Switching applications 

**==> picture [98 x 147] intentionally omitted <==**

**----- Start of picture text -----**<br>
D(2, TAB)<br>G(1)<br>S(3)<br>**----- End of picture text -----**<br>


## **Description** 

These devices are N-channel Power MOSFETs developed using the MDmesh™ M2 technology. Thanks to the strip layout associated with an improved vertical structure, the device exhibits both low on-resistance and optimized switching characteristics. It is therefore suitable for the most demanding high efficiency converters. 

AM01476v1_tab 

**Table 1: Device summary Order code Marking Package Packaging** STP7N65M2 7N65M2 TO-220 Tube STU7N65M2 7N65M2 IPAK Tube ~~re~~ 

This is information on a product in full production. 

_www.st.com_ 

May 2015 

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|**Contents**<br>**STP7N65M2, STU7N65M2**|**Contents**<br>**STP7N65M2, STU7N65M2**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 9**|
|**4**|**Package information ..................................................................... 10**|
||4.1<br>TO-220 type A package information ................................................ 11|
||4.2<br>IPAK(TO-251) type A package information ..................................... 13|
||4.3<br>IPAK (TO-251) type C package information .................................... 15|
|**5**|**Revision history ............................................................................ 17**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|± 25|V|
|ID|Drain current (continuous) at TC= 25 °C|5|A|
|ID|Drain current (continuous) at TC= 100 °C|3.2|A|
|IDM<br>_(1)_|Drain current (pulsed)|20|A|
|PTOT|Total dissipation at TC= 25 °C|60|W|
|dv/dt_(2)_|Peak diode recoveryvoltage slope|15|V/ns|
|dv/dt_(3)_|MOSFET dv/dt ruggedness|50||
|Tstg|Storage temperature|- 55 to 150|°C|
|Tj|Operating junction temperature|||



## **Notes:** 

(1) Pulse width limited by safe operating area 

(2) ISD ≤ 5 A, di/dt ≤ 400 A/µs; VDSpeak < V(BR)DSS, VDD=400 V 

(3) VDS ≤ 520 V 

**Table 3: Thermal data** 

|**Symbol**|**Symbol**|**Parameter**|**Value**|**Value**|**Value**|**Unit**|**Unit**|
|---|---|---|---|---|---|---|---|
||||**TO-220**|**IPAK**||||
|Rthj-case||Thermal resistancejunction-case max|2.08|||°C/W||
|Rthj-amb||Thermal resistance junction-ambient max|62.5|100||°C/W||
|||**Table 4: Avalanche characteristics**||||||
|**Symbol**||**Parameter**|||**Value**||**Unit**|
|IAR|Avalanche current, repetitive or not repetitive (pulse width limited byTjmax)||||1||A|
|EAS|Singlepulse avalanche energy(startingTj=25°C, ID= IAR; VDD=50 V)||||103||mJ|



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**STP7N65M2, STU7N65M2** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

**Table 5: On /off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0, ID= 1 mA|650|||V|
|IDSS|Zero gate voltage<br>drain current|VGS= 0, VDS= 650 V|||1|µA|
|||VGS= 0, VDS= 650 V,<br>TC=125 °C|||100|µA|
|IGSS|Gate-body leakage<br>current|VDS= 0, VGS= ± 25 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|2|3|4|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID= 2.5 A||0.98|1.15|Ω|



**Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0|-|270|-|pF|
|Coss|Output capacitance||-|14.5|-||
|Crss|Reverse transfer<br>capacitance||-|0.8|-||
|C<br>oss eq.<br>_(1)_|Equivalent output<br>capacitance|VDS= 0 to 520 V, VGS= 0|-|108|-|pF|
|RG|Intrinsicgate resistance|f = 1 MHz open drain|-|7|-|Ω|
|Qg|Totalgate charge|VDD= 520 V, ID= 5 A,<br>VGS= 10 V<br>(see_Figure 17: "Gate charge_<br>_test circuit"_)|-|9|-|nC|
|Qgs|Gate-source charge||-|2.3|-|nC|
|Qgd|Gate-drain charge||-|4.3|-|nC|



## **Notes:** 

(1)Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

**Table 7: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on<br>delaytime|VDD= 325 V, ID= 2.5 A,<br>RG= 4.7 Ω, VGS= 10 V<br>(see_Figure 16: "Switching times test circuit_<br>_for resistive load"_and_Figure 21: "Switching_<br>_time waveform"_)|-|8|-|ns|
|tr|Rise time||-|20|-|ns|
|td(off)|Turn-off<br>delaytime||-|30|-|ns|
|tf|Fall time||-|20|-|ns|



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**Electrical characteristics** 

**Table 8: Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||5|A|
|ISDM<br>_(1)_|Source-drain current<br>(pulsed)||-||20|A|
|VSD<br>_(2)_|Forward on voltage|ISD= 5 A, VGS= 0|-||1.6|V|
|trr|Reverse recovery<br>time|ISD= 5 A, di/dt = 100 A/µs<br>VDD= 60 V (see_Figure 21:_<br>_"Switching time waveform"_)|-|275||ns|
|Qrr|Reverse recovery<br>charge||-|1.62||µC|
|IRRM|Reverse recovery<br>current||-|11.8||A|
|trr|Reverse recovery<br>time|ISD= 5 A, di/dt = 100 A/µs<br>VDD= 60 V, Tj= 150 °C<br>(see_Figure 21: "Switching time_<br>_waveform"_)|-|430||ns|
|Qrr|Reverse recovery<br>charge||-|2.54||µC|
|IRRM|Reverse recovery<br>current||-|11.9||A|



## **Notes:** 

(1) Pulse width limited by safe operating area. 

(2) Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area for TO-220** 

**==> picture [197 x 160] intentionally omitted <==**

**Figure 3: Thermal impedance for TO-220** 

**==> picture [158 x 156] intentionally omitted <==**

**Figure 4: Safe operating area for IPAK** 

**==> picture [197 x 159] intentionally omitted <==**

**Figure 5: Thermal impedance for IPAK** 

**==> picture [202 x 156] intentionally omitted <==**

**----- Start of picture text -----**<br>
CG34360<br>K<br>10 [0]<br>c<br>10 [-1]<br>10 [-2]<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] tp  (s)<br>**----- End of picture text -----**<br>


**Figure 6: Output characteristics** 

**Figure 7: Transfer characteristics** 

**==> picture [421 x 164] intentionally omitted <==**

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**Electrical characteristics** 

**Figure 8: Gate charge vs gate-source voltage** 

**==> picture [187 x 160] intentionally omitted <==**

**Figure 10: Capacitance variations** 

**==> picture [186 x 160] intentionally omitted <==**

**Figure 12: Normalized gate threshold voltage vs temperature** 

**==> picture [181 x 160] intentionally omitted <==**

**Figure 9: Static drain-source on-resistance** 

**==> picture [195 x 160] intentionally omitted <==**

**Figure 11: Output capacitance stored energy** 

**==> picture [187 x 160] intentionally omitted <==**

**Figure 13: Normalized on-resistance vs temperature** 

**==> picture [174 x 160] intentionally omitted <==**

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## **Electrical characteristics** 

**Figure 14: Source-drain diode forward characteristics** 

**==> picture [195 x 160] intentionally omitted <==**

**Figure 15: Normalized V(BR)DSS vs temperature** 

**==> picture [182 x 160] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**Figure 16: Switching times test circuit for resistive load** 

**==> picture [207 x 79] intentionally omitted <==**

**Figure 18: Test circuit for inductive load switching and diode recovery times** 

**==> picture [213 x 129] intentionally omitted <==**

**Figure 20: Unclamped inductive waveform** 

**Figure 17: Gate charge test circuit** 

**==> picture [200 x 148] intentionally omitted <==**

**Figure 19: Unclamped inductive load test circuit** 

**==> picture [161 x 146] intentionally omitted <==**

**Figure 21: Switching time waveform** 

**==> picture [32 x 32] intentionally omitted <==**

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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package information** 

## **4.1 TO-220 type A package information** 

**Figure 22: TO-220 type A package outline** 

**==> picture [407 x 570] intentionally omitted <==**

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**Package information STP7N65M2, STU7N65M2** 

**Table 9: TO-220 type A mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.40||4.60|
|b|0.61||0.88|
|b1|1.14||1.70|
|c|0.48||0.70|
|D|15.25||15.75|
|D1||1.27||
|E|10||10.40|
|e|2.40||2.70|
|e1|4.95||5.15|
|F|1.23||1.32|
|H1|6.20||6.60|
|J1|2.40||2.72|
|L|13||14|
|L1|3.50||3.93|
|L20||16.40||
|L30||28.90||
|øP|3.75||3.85|
|Q|2.65||2.95|



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**Package information** 

## **4.2 IPAK(TO-251) type A package information** 

**Figure 23: IPAK (TO-251) type A package outline** 

**==> picture [406 x 461] intentionally omitted <==**

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**Package information STP7N65M2, STU7N65M2** 

|**Table 10: IPAK(TO-251) type Apackage mechanical**|**Table 10: IPAK(TO-251) type Apackage mechanical**|**Table 10: IPAK(TO-251) type Apackage mechanical**|**data**|
|---|---|---|---|
|**Dim.**||**mm**||
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|b|0.64||0.90|
|b2|||0.95|
|b4|5.20||5.40|
|B5||0.30||
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|E|6.40||6.60|
|e||2.28||
|e1|4.40||4.60|
|H||16.10||
|L|9.00||9.40|
|L1|0.80||1.20|
|L2||0.80|1.00|
|V1||10°||



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**Package information** 

## **4.3 IPAK (TO-251) type C package information** 

**Figure 24: IPAK (TO-251) type C package outline** 

**==> picture [406 x 368] intentionally omitted <==**

**----- Start of picture text -----**<br>
0068771_IK_typeC_rev13<br>**----- End of picture text -----**<br>


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**Package information** 

|**formation**<br>**STP7N65M2, STU7N65M2**|**formation**<br>**STP7N65M2, STU7N65M2**|**formation**<br>**STP7N65M2, STU7N65M2**|**formation**<br>**STP7N65M2, STU7N65M2**|
|---|---|---|---|
|**Table 11: IPAK(TO-251) type Cpackage mechanical data**||||
|**Dim.**||**mm**||
||**Min.**|**Typ.**|**Max.**|
|A|2.20|2.30|2.35|
|A1|0.90|1.00|1.10|
|b|0.66||0.79|
|b2|||0.90|
|b4|5.23|5.33|5.43|
|c|0.46||0.59|
|c2|0.46||0.59|
|D|6.00|6.10|6.20|
|D1|5.20|5.37|5.55|
|E|6.50|6.60|6.70|
|E1|4.60|4.78|4.95|
|e|2.20|2.25|2.30|
|e1|4.40|4.50|4.60|
|H|16.18|16.48|16.78|
|L|9.00|9.30|9.60|
|L1|0.90|1.00|1.20|
|L2|0.90|1.08|1.25|
|ϑ1|3°|5°|7°|
|ϑ2|1°|3°|5°|



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**Revision history** 

## **5 Revision history** 

**Table 12: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|07-Aug-2014|1|First release.|
|09-Oct-2014|2|Added  and .<br>Updated not found.<br>Minor text changes.|
|28-May-2015|3|Document status promoted form preliminary to production data.<br>Updatedpackage information.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2015 STMicroelectronics – All rights reserved 

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