# Dual MOSFET, N Channel, 60 V, 60 V, 8 A, 8 A, 0.024 ohm

![Product image](https://novapart.co/image/farnell:3129917/)

**URL**: https://novapart.co/products/STS8DN6LF6AG/dual-mosfet-n-channel-60-v-8-a-0024-ohm
**SKU**: STS8DN6LF6AG
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Dual MOSFETs
**Price**: €0.6080
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:Dual N Channel; Continuous Drain Current Id:8A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.021ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vg

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 3 - 168 hours |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | AEC-Q101 |
| Transistor Case Style | SOIC |
| Operating Temperature Max | 175°C |
| Power Dissipation N Channel | 3.2W |
| Power Dissipation P Channel | 3.2W |
| Drain Source Voltage Vds N Channel | 60V |
| Drain Source Voltage Vds P Channel | 60V |
| Continuous Drain Current Id N Channel | 8A |
| Continuous Drain Current Id P Channel | 8A |
| Drain Source On State Resistance N Channel | 0.024ohm |
| Drain Source On State Resistance P Channel | - |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3129917/)

## **STS8DN6LF6AG** 

Automotive-grade dual N-channel 60 V, 21 mΩ typ., 8 A STripFET™ F6 Power MOSFET in a SO-8 package 

Datasheet - production data 

**Features Order code VDS RDS(on) max. ID PTOT** STS8DN6LF6AG 60 V 24 mΩ 8 A 3.2 W  AEC-Q101 qualified  Very low on-resistance  Very low gate charge  High avalanche ruggedness  Low gate drive power loss ~~oe~~  Logic level **Figure 1: Internal schematic diagram Applications** 

**==> picture [473 x 208] intentionally omitted <==**

**----- Start of picture text -----**<br>
S1 1 8 D1  Switching applications<br>Description<br>G1 2 7 D1 This device is a dual N-channel Power MOSFET<br>developed using the STripFET™ F6 technology<br>with a new trench gate structure. The resulting<br>S2 3 6 D2 Power MOSFET exhibits very low RDS(on) in all<br>Te<br>packages.<br>G2 4 5 D2<br>a r i s<br>SC12820<br>Table 1: Device summary<br>Order code  Marking  Package  Packing<br>rs STS8DN6LF6AG  8DN6LF6  SO-8  Tape and reel<br>**----- End of picture text -----**<br>


This is information on a product in full production. 

December 2016 

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_www.st.com_ 

|**Contents**<br>**STS8DN6LF6AG**|**Contents**<br>**STS8DN6LF6AG**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>SO-8 package information ................................................................ 9|
||4.2<br>SO-8 packing information ................................................................ 11|
|**5**|**Revision history ............................................................................ 12**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|60|V|
|VGS|Gate-source voltage|±20|V|
|ID_(1)_|Drain current (continuous) at Tamb= 25 °C|8|A|
||Drain current (continuous) at Tamb= 100 °C|5.8||
|IDM_(2)_|Drain current (pulsed)|32|A|
|PTOT|Total dissipation at Tamb= 25 °C (one channel active)|3.2|W|
|Tstg|Storage temperature range|-55 to 175|°C|
|Tj|Operating junction temperature range|||



## **Notes:** 

- (1) When mounted on a 1-inch² FR-4, 2 Oz copper board, t < 10 s. 

- (2) Pulse width is limited by safe operating area 

## **Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-amb_(1)_|Thermal resistancejunction-ambient|47|°C/W|



## **Notes:** 

- (1) When mounted on a 1-inch² FR-4, 2 Oz copper board, t < 10 s. 

**Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAV|Avalanche current, not repetitive|6|A|
|EAS_(1)_|Singlepulse avalanche energy|72|mJ|



## **Notes:** 

(1) Starting Tj = 25 °C, ID = IAV, VDD = 43.5 V. 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(Tcase = 25 °C unless otherwise specified) 

## **Table 5: Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown voltage|VGS= 0 V, ID= 250µA|60|||V|
|IDSS|Zerogate voltage drain current|VGS= 0 V, VDS= 60 V|||1|µA|
|IGSS|Gate-bodyleakage current|VDS= 0 V, VGS= ±20 V|||±100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|1||2.5|V|
|RDS(on)|Static drain-source on-resistance|VGS= 10 V, ID= 4 A||21|24|mΩ|
|||VGS= 4.5 V, ID= 4 A||22|26||



## **Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 25 V, f = 1 MHz,<br>VGS= 0 V|-|1340|-|pF|
|Coss|Output capacitance||-|90|-||
|Crss|Reverse transfer capacitance||-|60|-||
|Qg|Totalgate charge|VDD= 30 V, ID= 8 A,<br>VGS= 10 V<br>(see_Figure 14: "Test circuit_<br>_for gate charge behavior"_)|-|27|-|nC|
|Qgs|Gate-source charge||-|4.6|-||
|Qgd|Gate-drain charge||-|4.3|-||



## **Table 7: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 30 V, ID= 4 A,<br>RG= 4.7 Ω, VGS= 10 V<br>(see_Figure 13: "Test circuit_<br>_for resistive load switching_<br>_times"_and_Figure 18:_<br>_"Switching time waveform"_)|-|9.6|-|ns|
|tr|Rise time||-|20|-||
|td(off)|Turn-off delaytime||-|56|-||
|tf|Fall time||-|7|-||



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**Electrical characteristics** 

**Table 8: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||8|A|
|ISDM_(1)_|Source-drain current<br>(pulsed)||-||32|A|
|VSD_(2)_|Forward on voltage|VGS= 0 V, ISD= 8 A|-||1.3|V|
|trr|Reverse recoverytime|ISD= 8 A, di/dt = 100 A/µs,<br>VDD= 48 V, Tj= 25 °C<br>(see_Figure 15: "Test circuit for_<br>_inductive load switching and_<br>_diode recovery times"_)|-|22.5||ns|
|Qrr|Reverse recoverycharge||-|22.2||nC|
|IRRM|Reverse recovery current||-|2.0||A|



## **Notes:** 

(1) Pulse width is limited by safe operating area. 

(2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. 

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## **Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**==> picture [467 x 190] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


**Figure 4: Output characteristics** 

**==> picture [178 x 164] intentionally omitted <==**

**Figure 5: Transfer characteristics** 

**==> picture [179 x 164] intentionally omitted <==**

**Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance** 

**==> picture [183 x 163] intentionally omitted <==**

**==> picture [179 x 158] intentionally omitted <==**

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**==> picture [439 x 206] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 8: Capacitance variations  Figure 9: Normalized gate threshold voltage vs<br>temperature<br>**----- End of picture text -----**<br>


**Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature** 

**==> picture [189 x 162] intentionally omitted <==**

**==> picture [193 x 162] intentionally omitted <==**

**Figure 12: Source-drain diode forward characteristics** 

**==> picture [173 x 157] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 375] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Test circuit for resistive load  Figure 14: Test circuit for gate charge<br>switching times  behavior<br>Figure 15: Test circuit for inductive load  Figure 16: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>**----- End of picture text -----**<br>


**==> picture [403 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 17: Unclamped inductive waveform  Figure 18: Switching time waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 SO-8 package information** 

**Figure 19: SO-8 package outline** 

**==> picture [409 x 391] intentionally omitted <==**

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**Package information** 

|**formation**|||**STS8DN6LF6AG**|
|---|---|---|---|
||**Table 9: SO-8 mechanical data**|||
|**Dim.**||**mm**||
||**Min.**|**Typ.**|**Max.**|
|A|||1.75|
|A1|0.10||0.25|
|A2|1.25|||
|b|0.31||0.51|
|b1|0.28||0.48|
|c|0.10||0.25|
|c1|0.10||0.23|
|D|4.80|4.90|5.00|
|E|5.80|6.00|6.20|
|E1|3.80|3.90|4.00|
|e||1.27||
|h|0.25||0.50|
|L|0.40||1.27|
|L1||1.04||
|L2||0.25||
|k|0°||8°|
|ccc|||0.10|



**Figure 20: SO-8 recommended footprint (dimensions are in mm)** 

**==> picture [409 x 204] intentionally omitted <==**

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**Package information** 

## **4.2 SO-8 packing information** 

**Figure 21: SO-8 tape and reel dimensions** 

**==> picture [408 x 278] intentionally omitted <==**

**Table 10: SO-8 tape and reel mechanical data** 

|Dim.||mm||
|---|---|---|---|
||Min.|Typ.|Max.|
|A||-|330|
|C|12.8||13.2|
|D|20.2|||
|N|60|||
|T|||22.4|
|Ao|8.1||8.5|
|Bo|5.5||5.9|
|Ko|2.1||2.3|
|Po|3.9||4.1|
|P|7.9||8.1|



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**Revision history** 

## **5 Revision history** 

**Table 11: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|06-Dec-2016|1|First release|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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## Links

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- [Supplier page](https://es.farnell.com/stmicroelectronics/sts8dn6lf6ag/mosfet-aec-q101-dual-n-ch-60v/dp/3129917)
---

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