# Power MOSFET, N Channel, 60 V, 7.5 A, 0.017 ohm, SOIC, Surface Mount

![Product image](https://novapart.co/image/farnell:2344088/)

**URL**: https://novapart.co/products/STS7NF60L/power-mosfet-n-channel-60-v-75-a-0017-ohm-soic
**SKU**: STS7NF60L
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.7510
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:7.5A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.017ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:1V; Powe

## Specifications

| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 2.5W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | SOIC |
| Drain Source Voltage Vds | 60V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 7.5A |
| Drain Source On State Resistance | 0.017ohm |
| Gate Source Threshold Voltage Max | 1V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2344088/)

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## **STS7NF60L** N-CHANNEL 60V - 0.017 Ω - 7.5A SO-8 STri FET™ II POWER MOSFET p 

|**TYPE**|**VDSS**|**RDS(on)**|**ID**|
|---|---|---|---|
|STS7NF60L|60 V|< 0.0195Ω|7.5 A|



- I TYPICAL RDS(on) = 0.017 Ω 

- I STANDARD OUTLINE FOR EASY AUTOMATED SURFACE MOUNT ASSEMBLY 

- I LOW THRESHOLD DRIVE 

## **DESCRIPTION** 

This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. 

## **APPLICATIONS** 

- I DC MOTOR DRIVE 

- I DC-DC CONVERTERS 

- I BATTERY MANAGEMENT IN NOMADIC EQUIPMENT 

- I POWER MANAGEMENT IN PORTABLE/DESKTOP PCs 

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## **INTERNAL SCHEMATIC DIAGRAM** 

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## **ABSOLUTE MAXIMUM RATINGS** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source Voltage (VGS= 0)|60|V|
|VDGR|Drain-gate Voltage (RGS= 20 kΩ)|60|V|
|VGS|Gate- source Voltage|± 16|V|
|ID|Drain Current (continuous) at TC= 25°C|7.5|A|
|ID|Drain Current (continuous) at TC= 100°C|4.7|A|
|IDM(•)|Drain Current (pulsed)|30|A|
|Ptot|Total Dissipation at TC= 25°C|2.5|W|
|EAS(1)|Single Pulse Avalanche Energy|350|mJ|



(•) Pulse width limited by safe operating area. 

(1) Starting Tj = 25[o] C, ID = 7.5 A VDD = 30 V 

. 

April 2002 

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## **THERMAL DATA** 

|Rthj-amb(#)<br>Tj<br>Tstg|Thermal Resistance Junction-ambient<br>Maximum Operating Junction Temperature<br>Storage Temperature<br>Max|50<br>150<br>-55 to 150|°C/W<br>°C<br>°C|
|---|---|---|---|



> (#) When Mounted on 1 inch2 FR-4 board, 2 oz of Cu and t [ 10 sec. 

## **ELECTRICAL CHARACTERISTICS** (Tcase = 25 °C unless otherwise specified) OFF 

|OFF|||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|V(BR)DSS|Drain-source<br>Breakdown Voltage|ID= 250 µA, VGS= 0|60|||V|
|IDSS|Zero Gate Voltage<br>Drain Current (VGS= 0)|VDS= Max Rating<br>VDS= Max Rating TC= 125°C|||1<br>10|µA<br>µA|
|IGSS|Gate-body Leakage<br>Current (VDS= 0)|VGS= ± 16 V|||±100|nA|
|ON(***)**|||||||
|**Symbol**|**Parameter**|**Test Conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|VGS(th)|Gate Threshold Voltage|VDS= VGS<br>ID= 250 µA|1|||V|
|RDS(on)|Static Drain-source On<br>Resistance|VGS= 10 V<br>ID= 3.5 A<br>VGS= 5 V<br>ID= 3.5 A||0.017<br>0.019|0.0195<br>0.0215|Ω<br>Ω|
|DYNAMIC|||||||
|**Symbol**|**Parameter**|**Test Conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|gfs|Forward Transconductance|VDS= 15 V<br>ID= 3.5 A||13||S|
|Ciss<br>Coss<br>Crss|Input Capacitance<br>Output Capacitance<br>Reverse Transfer<br>Capacitance|VDS= 25V, f = 1 MHz, VGS= 0||1700<br>300<br>100||pF<br>pF<br>pF|



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**STS7NF60L** 

## **ELECTRICAL CHARACTERISTICS** (continued) 

## SWITCHING ON[(*)] 

|SWITCHING|ON(*)||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Min.**|**Typ.**|**Max.**<br>**U**|**nit**|
|td(on)<br>tr|Turn-on Delay Time<br>Rise Time|VDD= 30 V<br>ID= 3<br>RG= 4.7Ω<br>VGS= 4<br>(Resistive Load, Figure 1)|.5 A<br>.5 V|15<br>27||ns<br>ns|
|Qg<br>Qgs<br>Qgd|Total Gate Charge<br>Gate-Source Charge<br>Gate-Drain Charge|VDD= 48V ID7.5A VGS=4<br>(see test circuit, Figure 2)|.5V|25<br>4.5<br>7|34<br><br><br>|nC<br>nC<br>nC|



## SWITCHING OFF[(*)] 

|SWITCHING|OFF(*)||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Min.**|**Typ.**|**Max.**<br>**U**|**nit**|
|td(off)<br>tf|Turn-off Delay Time<br>Fall Time|VDD= 30 V<br>ID= 3<br>RG= 4.7Ω,<br>VGS= 4<br>(Resistive Load, Figure 1)|.5 A<br>.5 V|47<br>20||ns<br>ns|



## SOURCE DRAIN DIODE[(*)] 

|**Symbol**|**Parameter**|**Test Conditions**|**Min.**|**Typ.**|**Max.**<br>**U**|**nit**|
|---|---|---|---|---|---|---|
|ISD<br>ISDM (•)|Source-drain Current<br>Source-drain Current (pulsed)||||7.5<br>30|A<br>A|
|VSD|Forward On Voltage|ISD= 7.5 A<br>VGS= 0|||1.2|V|
|trr<br>Qrr<br>IRRM|Reverse Recovery Time<br>Reverse Recovery Charge<br>Reverse Recovery Current|ISD=7.5 A<br>di/dt = 100<br>VDD= 20 V<br>Tj= 150°<br>(see test circuit, Figure 3)|A/µs<br>C|55<br>110<br>3.9||ns<br>nC<br>A|



(*) Pulse width [ 300 µs, duty cycle 1.5 %. 

(•)Pulse width limited by safe operating area. 

## Safe Operating Area 

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Thermal Impedance 

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**STS7NF60L** 

Output Characteristics 

Transconductance 

Gate Charge vs Gate-source Voltage 

## Transfer Characteristics 

Static Drain-source On Resistance 

Capacitance Variations 

4/8 

**STS7NF60L** 

Normalized Gate Threshold Voltage vs Temperature 

Normalized on Resistance vs Temperature 

Source-drain Diode Forward Characteristics 

Normalized Breakdown Voltage vs Temperature 

. . 

5/8 

## **STS7NF60L** 

**Fig. 1: Unclamped Inductive Load Test Circuit** 

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**Fig. 3:** Switching Times Test Circuits For Resistive Load 

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**Fig. 2:** Unclamped Inductive Waveform 

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**Fig. 4:** Gate Charge test Circuit 

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**Fig. 5:** Test Circuit For Inductive Load Switching And Diode Recovery Times 

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## **SO-8  MECHANICAL DATA** 

|**DIM.**|**mm**|**mm**|**mm**|**inch**|**inch**|**inch**|
|---|---|---|---|---|---|---|
||**MIN.**|**TYP.**|**MAX.**|**MIN.**|**TYP.**|**MAX.**|
|A|||1.75|||0.068|
|a1|0.1||0.25|0.003||0.009|
|a2|||1.65|||0.064|
|a3|0.65||0.85|0.025||0.033|
|b|0.35||0.48|0.013||0.018|
|b1|0.19||0.25|0.007||0.010|
|C|0.25||0.5|0.010||0.019|
|c1|45(typ.)||||||
|D|4.8||5.0|0.188||0.196|
|E|5.8||6.2|0.228||0.244|
|e||1.27|||0.050||
|e3||3.81|||0.150||
|F|3.8||4.0|0.14||0.157|
|L|0.4||1.27|0.015||0.050|
|M|||0.6|||0.023|
|S|8 (max.)||||||



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**STS7NF60L** 

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 

- The ST logo is registered trademark of STMicroelectronics  2002 STMicroelectronics - All Rights Reserved 

All other names are the property of their respective owners. 

STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. 

**http://www.st.com** 

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