# Power MOSFET, N Channel, 60 V, 5 A, 0.045 ohm, SOIC, Surface Mount

![Product image](https://novapart.co/image/farnell:1752188/)

**URL**: https://novapart.co/products/STS5NF60L/power-mosfet-n-channel-60-v-5-a-0045-ohm-soic
**SKU**: STS5NF60L
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.3830
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:5A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.045ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:1.7V; Power

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | AEC-Q101 |
| Power Dissipation | 2.5W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | SOIC |
| Drain Source Voltage Vds | 60V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 5A |
| Drain Source On State Resistance | 0.045ohm |
| Gate Source Threshold Voltage Max | 1.7V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1752188/)

**==> picture [61 x 39] intentionally omitted <==**

## **STS5NF60L** N-channel 60V - 0.045Ω - 5A - SO-8 STripFET™ Power MOSFET 

## **General features** 

|**Type**|**VDSS**|**RDS(on)**|**ID**|
|---|---|---|---|
|STS5NF60L|60V|<0.055Ω|5A|



- Standard outline for easy automated surface mount assembly 

- Low threshold drive 

## **Description** 

This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. 

## **Applications** 

- Switching application 

**==> picture [59 x 53] intentionally omitted <==**

## **SO-8** 

## **Internal schematic diagram** 

**==> picture [146 x 150] intentionally omitted <==**

## **Order codes** 

|**Part number**|**Marking**|**Package**|**Packaging**|
|---|---|---|---|
|STS5NF60L|S5NF60L|SO-8|Tape&reel|



1/12 

January 2007 

Rev 4 

_www.st.com_ 

**Contents** 

**STS5NF60L** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Electrical characteristics (curves)         . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Test circuit   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8**|
|**4**|**Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9**|
|**5**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11**|



2/12 

**STS5NF60L** 

**Electrical ratings** 

## **1 Electrical ratings** 

## **Table 1. Absolute maximum ratings** 

|**Table 1.**|**Absolute maximum ratings**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|VDS|Drain-source voltage (vgs= 0)|60|V|
|VGS|Gate- source voltage|±20|V|
|ID|Drain current (continuous) at TC= 25°C|5|A|
|ID|Drain current (continuous) at TC= 100°C|3|A|
|IDM<br>(1)|Drain current (pulsed)|20|A|
|PTOT|Total dissipation at TC= 25°C|2.5|W|
||Derating factor|0.02|W/°C|
|dv/dt(2)|Peak diode recovery voltage slope|5.5|V/ns|
|Tstg<br>Tj|Storage Temperature<br>Max operating junction temperature|-55 to 150<br>150|°C<br>°C|



1. Pulse width limited by safe operating area 

2. ISD ≤ 5A, di/dt ≤ 100A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 

|**Table 2.**<br>**Thermal data**|**Table 2.**<br>**Thermal data**|**Table 2.**<br>**Thermal data**|**Table 2.**<br>**Thermal data**|
|---|---|---|---|
|Rthj-a|(1)Thermal resistance junction-ambient Max|50|°C/W|
|Tl|Maximum lead temperature for soldering purpose<br>Typ|150|°C|



1. Mounted on FR-4 board (t 10 sec.). 

3/12 

**STS5NF60L** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

## (TCASE=25°C unless otherwise specified) 

## **Table 3. On/off states** 

|**Table 3.**|**On/off states**||||||||
|---|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**||**Max.**||**Unit**|
|V(BR)DSS|Drain-source<br>Breakdown voltage|ID= 250 µA, VGS= 0|60|||||V|
|IDSS|Zero gate voltage<br>Drain current (VGS= 0)|VDS= Max rating<br>VDS= Max rating,<br>TC=125°C||||1<br>10||µA<br>µA|
|IGSS|Gate-body leakage<br>current (VDS= 0)|VGS= ± 20V||||±100||nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|1|1.7||2.5||V|
|RDS(on)|Static drain-source on<br>resistance|VGS= 10V, ID= 2.5A<br>VGS= 4.5V, ID= 2.5A||0.045<br>0.050||0.055<br>0.065||Ω<br>Ω|
|**Table 4.**<br>**Dynamic**|||||||||
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**||**Unit**||
|gfs<br>(1)|Forward transconductance|VDS= 15V, ID=2.5 A||7|||S||
|Ciss<br>Coss<br>Crss|Input capacitance<br>Output capacitance<br>Reverse transfer<br>capacitance|VDS= 25V, f = 1 MHz,<br>VGS= 0||1250<br>130<br>26|||pF<br>pF<br>pF||
|Qg<br>Qgs<br>Qgd|Total gate charge<br>Gate-source charge<br>Gate-drain charge|VDD= 48V, ID= 5A,<br>VGS= 5V<br>(see Figure 13)||17<br>4.5<br>6|||nC<br>nC<br>nC||



1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5. 

## **Table 5. Switching times** 

|**Table 5.**|**Switching times**||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|td(on)<br>tr|Turn-on delay time<br>Rise time|VDD=30 V, ID=2.5A,<br>RG=4.7Ω,VGS= 4.5V<br>(see Figure 12)||13<br>28||ns<br>ns|
|td(off)<br>tf|Turn-off Delay Time<br>Fall Time|VDD= 30 V, ID= 2.5A<br>RG=4.7Ω,VGS= 4.5V<br>(see Figure 12)||45<br>10||ns<br>ns|



4/12 

**STS5NF60L** 

**Electrical characteristics** 

**Table 6.** 

## **Source drain diode** 

|**Table 6.**|**Source drain diode**||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min**|**Typ.**|**Max**|**Unit**|
|ISD<br>ISDM<br>(1)|Source-drain current<br>Source-drain current (pulsed)||||5<br>20|A<br>A|
|VSD<br>(2)|Forward on voltage|ISD= 5A, VGS= 0|||1.2|V|
|trr<br>Qrr<br>IRRM|Reverse recovery time<br>Reverse recovery charge<br>Reverse recovery current|ISD= 5A, VDD= 40V<br>di/dt = 100A/µs,<br>Tj= 150°C<br>(see Figure 14)||85<br>85<br>2||ns<br>nC<br>A|



1. Pulse width limited by safe operating area. 

2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% 

5/12 

**STS5NF60L** 

**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

## **Figure 1. Safe operating area** 

**Figure 2. Thermal impedance** 

**==> picture [152 x 149] intentionally omitted <==**

**==> picture [152 x 151] intentionally omitted <==**

## **Figure 3. Output characteristics** 

## **Figure 4. Transfer characteristics** 

**==> picture [164 x 157] intentionally omitted <==**

**Figure 5. Transconductance** 

**==> picture [164 x 157] intentionally omitted <==**

**Figure 6. Static drain-source on resistance** 

**==> picture [164 x 156] intentionally omitted <==**

**==> picture [152 x 145] intentionally omitted <==**

6/12 

**STS5NF60L** 

**Electrical characteristics** 

## **Figure 7. Gate charge vs. gate-source voltage Figure 8. Capacitance variations** 

**==> picture [164 x 149] intentionally omitted <==**

**==> picture [164 x 153] intentionally omitted <==**

**Figure 9. Normalized gate threshold voltage vs. temperature** 

**==> picture [164 x 149] intentionally omitted <==**

**Figure 10. Normalized on resistance vs. temperature** 

**==> picture [152 x 139] intentionally omitted <==**

**Figure 11. Source-drain diode forward characteristics** 

**==> picture [164 x 154] intentionally omitted <==**

7/12 

**STS5NF60L** 

**Test circuit** 

## **3 Test circuit** 

**Figure 12. Switching times test circuit for resistive load** 

**==> picture [173 x 92] intentionally omitted <==**

**Figure 14. Test circuit for inductive load switching and diode recovery times** 

**==> picture [173 x 101] intentionally omitted <==**

**Figure 16. Unclamped inductive waveform** 

**==> picture [173 x 142] intentionally omitted <==**

**Figure 13. Gate charge test circuit** 

**==> picture [172 x 118] intentionally omitted <==**

**Figure 15. Unclamped Inductive load test circuit** 

**==> picture [172 x 114] intentionally omitted <==**

**Figure 17. Switching time waveform** 

**==> picture [172 x 134] intentionally omitted <==**

8/12 

**STS5NF60L** 

**Package mechanical data** 

## **4 Package mechanical data** 

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at : _www.st.com_ 

9/12 

**STS5NF60L** 

**Package mechanical data** 

|||||||||||||||**inch**<br>**TYP.**<br>**MAX.**<br>0.068<br>0.009<br>0.064<br>0.033<br>0.018<br>0.010<br>0.019<br>0.196<br>0.244<br>0.050<br>0.150<br>0.157<br>0.050<br>0.023|**inch**<br>**TYP.**<br>**MAX.**<br>0.068<br>0.009<br>0.064<br>0.033<br>0.018<br>0.010<br>0.019<br>0.196<br>0.244<br>0.050<br>0.150<br>0.157<br>0.050<br>0.023|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|||||**S**|||**O-8**|**MECHANICAL DATA**||||||||
|||||||||||||||||
|||||||||||||||||
||**DIM.**|||**m**|||**m.**|||||||**inch**||
||||**M**|**IN.**|**T**||**YP**||**MAX.**||**MIN.**|||**TYP.**|**MAX.**|
||A||||||||1.75||||||0.068|
||a1|||0.1|||||0.25||0.003||||0.009|
||a2||||||||1.65||||||0.064|
||a3||0|.65|||||0.85||0.025||||0.033|
||b||0|.35|||||0.48||0.013||||0.018|
||b1||0|.19|||||0.25||0.007||||0.010|
||C||0|.25|||||0.|5|0.010||||0.019|
||c1|||||||||45 (typ.)||||||
||D|||4.8|||||5.|0|0.188||||0.196|
||E|||5.8|||||6.|2|0.228||||0.244|
||e||||1.||27|||||||0.050||
||e3||||3.||81|||||||0.150||
||F|||3.8|||||4.|0|0.14||||0.157|
||L|||0.4|||||1.2|7|0.015||||0.050|
||M||||||||0.|6|||||0.023|
||S|||||||||8 (max.)||||||
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10/12 

**STS5NF60L** 

**Revision history** 

## **5 Revision history** 

## **Table 7. Revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|21-Jun-2004|2|First release|
|06-Nov-2006|3|The document has been reformatted|
|30-Jan-2007|4|Typo mistake on_Table 1_.|



11/12 

**STS5NF60L** 

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12/12 



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