# Power MOSFET, N Channel, 450 V, 500 mA, 3.2 ohm, SOIC, Surface Mount

![Product image](https://novapart.co/image/farnell:2098345/)

**URL**: https://novapart.co/products/STS1DN45K3/power-mosfet-n-channel-450-v-500-ma-32-ohm-soic
**SKU**: STS1DN45K3
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.4680
**Stock**: 10+

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:500mA; Drain Source Voltage Vds:450V; On Resistance Rds(on):3.2ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3.75V; P

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 1.7W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | SOIC |
| Drain Source Voltage Vds | 450V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 500mA |
| Drain Source On State Resistance | 3.2ohm |
| Gate Source Threshold Voltage Max | 3.75V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2098345/)

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## **STS1DN45K3** Dual N-channel 450 V, 3.2 Ω , 0.5 A SuperMESH3™ Power MOSFET in SO-8 

**Preliminary data** 

## **Features** 

|**Type**|**VDSS**|**RDS(on)**<br>**max**|**ID**|**Pw**|
|---|---|---|---|---|
|STS1DN45K3|450 V|< 3.8Ω|0.5 A|1.7 W|



- 100% avalanche tested 

**==> picture [59 x 50] intentionally omitted <==**

- Low input capacitances and gate charge 

- Low gate input resistance 

**==> picture [22 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
SO-8<br>**----- End of picture text -----**<br>


## **Application** 

- Switching applications 

## **Description** 

SuperMESH3™ is a new Power MOSFET technology that is obtained via improvements applied to STMicroelectronics’ SuperMESH™ technology combined with a new optimized vertical structure. The resulting product has an extremely low on resistance, superior dynamic performance and high avalanche capability, making it especially suitable for the most demanding applications. 

## **Figure 1. Internal schematic diagram** 

**==> picture [164 x 159] intentionally omitted <==**

**Table 1. Device summary** 

|**Order codes**|**Marking**|**Packages**|**Packaging**|
|---|---|---|---|
|STS1DN45K3|1ll45|SO-8|Tape and reel|



April 2010 

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Doc ID 17338 Rev 1 

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

_www.st.com_ 

**Contents** 

**STS1DN45K3** 

## **Contents** 

|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|---|---|
|**2**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
|**3**|**Test circuits     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6**|
|**4**|**Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7**|
|**5**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9**|



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**Electrical ratings** 

## **1 Electrical ratings** 

## **Table 2. Absolute maximum ratings** 

|**Table 2.**|**Absolute maximum ratings**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|VDS|Drain-source voltage (VGS= 0)|450|V|
|VGS|Gate-source voltage|± 30|V|
|ID|Drain current (continuous) at TC= 25 °C|0.5|A|
|ID|Drain current (continuous) at TC= 100 °C|0.32|A|
|IDM<br>(1)|Drain current (pulsed)|2|A|
|PTOT|Total dissipation at TC= 25 °C (dual operation)|1.7|W|
||Total dissipation at TC= 25 °C (single operation)|1.3|W|
|IAR|Avalanche current, repetitive or not-repetitive (pulse<br>width limited by Tjmax)|0.5|A|
|EAS|Single pulse avalanche energy<br>(starting Tj= 25°C, ID= IAR, VDD= 50 V)|TBD|mJ|
|dv/dt(2)|Peak diode recovery voltage slope|TBD|V/ns|
|Tstg|Storage temperature|- 55 to 150|°C|
|Tj|Max. operating junction temperature|150|°C|



1. Pulse width limited by safe operating area 

2. ISD ≤  0. 5 A, di/dt ≤ TBD A/µs, VPeak < V(BR)DSS 

## **Table 3. Thermal data** 

|**Table 3.**|**Thermal data**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|Rthj-amb<br>(1)|Thermal resistance junction-amb max<br>(single operation)|62.5|°C/W|
||Thermal resistance junction-amb max<br>(dual operation)|78|°C/W|



1. When mounted on FR4 board (steady state) 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

## **Table 4. On /off states** 

|**Table 4.**|**On /off states**||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|V(BR)DSS|Drain-source<br>breakdown voltage|ID= 1 mA, VGS= 0|450|||V|
|IDSS|Zero gate voltage<br>drain current (VGS= 0)|VDS= Max rating<br>VDS= Max rating, TC=125 °C|||1<br>50|µA<br>µA|
|IGSS|Gate-body leakage<br>current (VDS= 0)|VGS= ± 20 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 50 µA|3|3.75|4.5|V|
|RDS(on)|Static drain-source on<br>resistance|VGS= 10 V, ID= 0.5 A||3.2|3.8|Ω|



## **Table 5. Dynamic** 

|**Table 5.**|**Dynamic**||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|Ciss<br>Coss<br>Crss|Input capacitance<br>Output capacitance<br>Reverse transfer<br>capacitance|VDS=25 V, f = 1 MHz,<br>VGS= 0|-|150<br>30<br>6|-|pF<br>pF<br>pF|
|Co(tr)<br>(1)|Equivalent<br>capacitance time<br>related|VDS= 0 to 360 V, VGS= 0|-|TBD|-|pF|
|Co(er)<br>(2)|Equivalent<br>capacitance energy<br>related||-|TBD|-|pF|
|RG|Intrinsic gate<br>resistance|f = 1 MHz open drain|-|TBD|-|Ω|
|Qg<br>Qgs<br>Qgd|Total gate charge<br>Gate-source charge<br>Gate-drain charge|VDD= 360 V, ID= 0.5 A,<br>VGS= 10 V<br>(see_Figure 3_)|-|6<br>TBD<br>TBD|-|nC<br>nC<br>nC|



1. Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

2. Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 

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**Electrical characteristics** 

## **Table 6. Switching times** 

|**Table 6.**|**Switching times**||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max**|**Unit**|
|td(on)<br>tr<br>td(off)<br>tf|Turn-on delay time<br>Rise time<br>Turn-off-delay time<br>Fall time|VDD= 225 V, ID= 0.5 A,<br>RG= 4.7Ω,VGS= 10 V<br>(see_Figure 4_)|-|TBD<br>TBD<br>TBD<br>TBD|-|ns<br>ns<br>ns<br>ns|



## **Table 7. Source drain diode** 

|**Table 7.**|**Source drain diode**||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|ISD<br>ISDM (1)|Source-drain current<br>Source-drain current (pulsed)||-||0.5<br>2|A<br>A|
|VSD (2)|Forward on voltage|ISD= 0.5 A, VGS= 0|-||1.6|V|
|trr<br>Qrr<br>IRRM|Reverse recovery time<br>Reverse recovery charge<br>Reverse recovery current|ISD= 0.5 A, di/dt = 100 A/µs<br>VDD= 100 V (see_Figure 7_)|-|TBD<br>TBD<br>TBD||ns<br>nC<br>A|
|trr<br>Qrr<br>IRRM|Reverse recovery time<br>Reverse recovery charge<br>Reverse recovery current|ISD= 0.5 A, di/dt = 100 A/µs<br>VDD= 100 V, Tj= 150 °C<br>(see_Figure 7_)|-|TBD<br>TBD<br>TBD||ns<br>nC<br>A|



1. Pulse width limited by safe operating area 

2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

## **Table 8. Gate-source Zener diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|BVGSO|Gate-source breakdown<br>voltage|Igs=± 1 mA (open drain)|30|||V|



The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components 

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**Test circuits** 

## **3 Test circuits** 

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**----- Start of picture text -----**<br>
Figure 2. Switching times test circuit for  Figure 3. Gate charge test circuit<br>resistive load<br>**----- End of picture text -----**<br>


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VDD<br>12V 47kΩ<br>1kΩ<br>100nF<br>RL 2200 3.3<br>µF µF<br>VDD IG=CONST<br>VD Vi=20V=VGMAX 100Ω D.U.T.<br>VGS<br>2200<br>RG D.U.T. µF 2.7kΩ VG<br>PW<br>47kΩ<br>1kΩ<br>PW<br>AM01468v1 AM01469v1<br>Figure 4. Test circuit for inductive load  Figure 5. Unclamped inductive load test<br>switching and diode recovery times circuit<br>**----- End of picture text -----**<br>


**==> picture [463 x 346] intentionally omitted <==**

**----- Start of picture text -----**<br>
L<br>A A A<br>D<br>G D.U.T. FASTDIODE L=100µH VD 2200 3.3<br>S B 3.3 1000 µF µF VDD<br>25 Ω B B D µF µF VDD ID<br>G<br>RG S<br>Vi D.U.T.<br>Pw<br>AM01470v1 AM01471v1<br>Figure 6. Unclamped inductive waveform Figure 7. Switching time waveform<br>V(BR)DSS ton toff<br>VD tdon tr tdoff tf<br>90% 90%<br>IDM<br>10%<br>ID 0 10% VDS<br>VDD VDD 90%<br>VGS<br>AM01472v1 0 10% AM01473v1<br>**----- End of picture text -----**<br>


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**Package mechanical data** 

## **4 Package mechanical data** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 

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**Package mechanical data** 

## **SO-8 mechanical data** 

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mm<br>Dim.<br>Min. Typ. Max.<br>A 1.75<br>A1 0.10 0.25<br>A2 1.25<br>b 0.28 0.48<br>c 0.17 0.23<br>D 4.80 4.90 5.00<br>E 5.80 6.00 6.20<br>E1 3.80 3.90 4.00<br>e 1.27<br>h 0.25 0.50<br>L 0.40 1.27<br>L1 1.04<br>k 0° 8°<br>ccc 0.10<br>0016023_D<br>**----- End of picture text -----**<br>


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**Revision history** 

## **5 Revision history** 

**Table 9. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|07-Apr-2010|1|First release|



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