# Capacitor, RF, High Q, 3.9 pF, Parascan STPTIC Series, 85 °C, WLCSP

![Product image](https://novapart.co/image/farnell:2490185/)

**URL**: https://novapart.co/products/STPTIC-39G2C5/capacitor-rf-high-q-39-pf-parascan-stptic-series
**SKU**: STPTIC-39G2C5
**Manufacturer**: STMICROELECTRONICS
**Category**: Passive Components || Capacitors || RF Capacitors
**Price**: €0.3540
**Stock**: 10+

## Description

Capacitance:3.9pF; Voltage Rating:-; Product Range:Parascan STPTIC Series; Capacitance Tolerance:-; Operating Temperature Max:85°C; Capacitor Case Style:WLCSP; Automotive Qualification Standard:-; SVHC

## Specifications

| Parameter | Value |
|---|---|
| Capacitance | 3.9pF |
| Product Range | Parascan STPTIC Series |
| Voltage Rating | - |
| Capacitor Case Style | WLCSP |
| Capacitance Tolerance | - |
| Operating Temperature Max | 85°C |
| Automotive Qualification Standard | - |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2490185/)

## **STPTIC-39G2** 

## Parascan™ tunable integrated capacitor 

**Datasheet** - **production data** 

## **Description** 

The ST integrated tunable capacitor offers excellent RF performance, low power consumption and high linearity required in adaptive RF tuning applications. The fundamental building block of PTIC is a tunable material called Parascan™, which is a version of barium strontium titanate (BST) developed by Paratek microwave. 

## **Features** 

- High power capability 

- 5:1 tuning range 

- High linearity 

- High quality factor (Q) 

- Low leakage current 

BST capacitors are tunable capacitors intended for use in mobile phone application and dedicated to RF tunable applications. These tunable capacitors are controlled through an extended bias voltage ranging from 1 to 24 V. The implementation of BST tunable capacitor in mobile phones enables significant improvement in terms of radiated performance making the performance almost insensitive to the external environment. 

## **Figure 1. PTIC functional block diagram** 

- Compatible with high voltage control IC (STHVDAC series) 

- Available in wafer level chip scale package: – WLCSP package 0.61 x 0.66 x 0.3 mm 

- ECOPACK[®] 2 compliant component 

## **Benefit** 

- RF tunable passive implementation in mobile phones to optimize antenna radiated performance 

## **Applications** 

- Cellular antenna open loop tunable matching network in multi-band GSM/WCDMA/LTE mobile phone 

- Open loop tunable RF filters 

TM: Parascan is a trademark of Paratek Microwave Inc. 

1/11 

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DocID028099 Rev 1 

This is information on a product in full production. 

_www.st.com_ 

**STPTIC-39G2** 

**Electrical characteristics** 

## **1 Electrical characteristics** 

**Table 1. Absolute maximum ratings (limiting values)** 

|**Symbol**|**Parameter**|**Rating**|**Unit**|
|---|---|---|---|
|PIN|Input peak power RFIN(CW mode)/all RF ports|+40|dBm|
|VESD(HBM)|Human body model, JESD22-A114-B, all I/O|Class 1B(1)|V|
|VESD(MM)|Machine model, JESD22-A115-A, all I/O|100|V|
|Tdevice|Device temperature|+125|°C|
|Tstg|Storage temperature|-55 to +150||
|Vx|Bias voltage|25|V|



1. Class 1B defined as passing 500 V, but fails after exposure to 1000V ESD pulse. 

**Table 2. Recommended operating conditions** 

||**Table 2. Recommended operating **|**conditions**|**conditions**|**conditions**||
|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Rating**|||**Unit**|
|||**Min.**|**Typ.**|**Max.**||
|PIN|RF input power||+33||dBm|
|FOP|Operating frequency|700||2700|MHz|
|Tdevice|Device temperature|||+100|°C|
|TOP|Operating temperature|-30||+85||
|VBIAS|Bias voltage|1||24|V|



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**STPTIC-39G2** 

**Electrical characteristics** 

**Table 3. Representative performance (Tamb = 25 °C otherwise specified)** 

|**Symbol**|**Parameter**|**Conditions**|**Value**|**Value**|**Value**|**Unit**|
|---|---|---|---|---|---|---|
||||**Min**|**Typ**|**Max**||
|C1V|capacitor at 1 V bias|STPTIC-39G2|3.96|4.5|5.04|pF|
|C2V|capacitor at 2 V bias|STPTIC-39G2||3.9||pF|
|C24V|capacitor at 24 V bias|STPTIC-39G2|0.72|0.78|0.84|pF|
|ΔC|Tuning range|Ratio between C1V/C24V<br>(1)|5/1||||
|IL|Leakage current|Measured with Vbias= 24 V|||100|nA|
|QLB|Quality factor|Measured at 700 MHz at 2 V|55|65|||
|QHB|Quality factor|Measured at 2700 MHz at 2 V|35|50|||
|IP3|Third order intercept point|Vbias= 1 V(2)(4)|52|60||dBm|
|||Vbias= 24 V(2)(4)||75|||
|H2|Second harmonic|Vbias= 1 V(3)(4)||-65|-45|dBm|
|||Vbias= 24 V(3)(4)||-75|||
|H3|Third harmonic|Vbias= 1 V(3)(4)||-35|-30|dBm|
|||Vbias= 24 V(3)(4)||-65|||
|tT|Transition time|Average for any transition between Cminto Cmax<br>(5)||40||µs|
|||Average transition between Cmaxto Cmin(5)||20|||



1. Measured at low frequency 

2. F1 = 894 MHz, F2 = 849 MHz, P1 = +25 dBm, P2 = +25 dBm, 2f1 - f2 = 939 MHz 

3. 850 MHz, Pin = +34 dBm 

4. IP3 and harmonics are measured in the shunt configuration in a 50 Ω environment 

5. One or both of RFin and RFout must be connected to DC ground, using the HVDAC turbo mode 

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**STPTIC-39G2** 

**Electrical characteristics** 

**Figure 2. Capacitor variation versus bias voltage** 

**Figure 3. Quality factor versus frequency** 

**Figure 4. Harmonic power versus bias voltage Figure 5. Harmonic power versus bias voltage (series) (shunt)** 

**Figure 6. Third order intercept point (IP3)** 

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**STPTIC-39G2** 

**Package information** 

## **2 Package information** 

- Epoxy meets UL94, V0 

- Lead-free package 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _www.st.com._ ECOPACK[®] is an ST trademark. 

## **2.1 Flip-Chip package information** 

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The land pattern below is recommended for soldering the STPTIC-G2 on PCB. 

NC stands for No Connect, this pad must not be connected on application board. Please leave this pad floating. 

**Table 4. Flip-Chip package dimensions** 

|**Dimensions (micron)**|**A1**|**A2**|**B1**|**B2**|**B4**|**C1**|**C2**|**D1**|**D2**|**D3**|**E1**|**E2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|STPTIC-15/27/33/39/47G2|640|590|120|400|120|85|420|200|90|290|125|165|
|STPTIC-56G2|710||||190||||||||
|STPTIC-68G2|780||||260||||||||
|STPTIC-82G2|880||||360||||||||
|Tolerance|±30|±30|±15|±10|±15|±15|±10|±20|±20|±40|±20|±20|



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**STPTIC-39G2** 

**Package information** 

## **Figure 8. Recommended PCB land pattern for Flip-Chip package** 

**Table 5. Dimensions** 

|**Dimensions**|**L1**|**W1**|**L3**|**L2**|**W2**|**L4**|**X1**|**X2**|**Y1**|**Y2**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Typical values (micron)**|160|160|260|210|210|310|320|270|240|190|



## **2.2 Packing information** 

## **Figure 9. Flip-Chip tape and reel outline** 

**Table 6. Dimensions** 

|**Pocket dimensions**|**L**|**W**|**H**|
|---|---|---|---|
|STPTIC-15/27/33/39/47G2|730|680|380|
|STPTIC-56G2|800|680|380|
|STPTIC-68G2|870|680|380|
|STPTIC-82G2|970|680|380|



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**STPTIC-39G2** 

**Package information** 

## **Figure 10. Flip-Chip marking** 

**Table 7. Pinout description** 

|**Pad / ball number**|**Pin name**|**Description**|
|---|---|---|
|A1|DC bias|DC bias voltage|
|B1|RF2|RF input / output(1)|
|A2|NC|Not connected|
|B2|RF1|RF input / output|



1. When connected in shunt, please connect RF2 (B1 ball) to GND 

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**STPTIC-39G2** 

**Reflow profile** 

## **3 Reflow profile** 

## **Figure 11. ST ECOPACK[®] recommended soldering reflow profile for PCB mounting** 

_Note:_ 

_Minimize air convection currents in the reflow oven to avoid component movement._ 

**Table 8. Recommended values for soldering reflow** 

|**Profile**|**Value**|**Value**|
|---|---|---|
||**Typical**|**Max.**|
|Temperature gradient in preheat (T = 70-180 °C)|0.9 °C/s|3 °C/s|
|Temperature gradient (T = 200-225 °C)|2 °C/s|3 °C/s|
|Peak temperature in reflow|240-245 °C|260 °C|
|Time above 220 °C|60 s|90 s|
|Temperature gradient in cooling|-2 to -3 °C/s|-6 °C/s|
|Time from 50 to 220 °C|160 to 220 s||



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**STPTIC-39G2** 

**Evaluation board** 

## **4 Evaluation board** 

**Figure 12. Series and shunt connection** 

## **Figure 13. Layer 1 and layer 4** 

**Figure 14. Layer 2 and layer 3** 

DocID028099 Rev 1 9/11 ~~A~~ 

**Ordering information** 

**STPTIC-39G2** 

## **5 Ordering information** 

## **Figure 15. Ordering information scheme** 

**Table 9. Ordering information** 

|**Part number**|**Marking**|**Base qty**|**Package**|**Delivery mode**|
|---|---|---|---|---|
|STPTIC-39G2C5|39G|15 000|Flip-Chip|Tape and reel|



## **6 Revision history** 

**Table 10. Document revision history** 

|**Date**|**Revision**||**Changes**|
|---|---|---|---|
|09-Jul-2015|1|Initial release.||



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**STPTIC-39G2** 

## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2015 STMicroelectronics – All rights reserved 

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- [Supplier page](https://es.farnell.com/stmicroelectronics/stptic-39g2c5/cap-3-9pf-wlcsp/dp/2490185)
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