# Power MOSFET, N Channel, 650 V, 12 A, 0.275 ohm, TO-220AB, Through Hole

![Product image](https://novapart.co/image/farnell:3367068/)

**URL**: https://novapart.co/products/STP18N65M2/power-mosfet-n-channel-650-v-12-a-0275-ohm-to
**SKU**: STP18N65M2
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.7670
**Stock**: 500+
**Lead Time**: 127 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh M2 |
| Qualification | - |
| Power Dissipation | 110W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-220AB |
| Drain Source Voltage Vds | 650V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 12A |
| Drain Source On State Resistance | 0.275ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3367068/)

## **STI18N65M2, STP18N65M2** 

N-channel 650 V, 0.275 Ω typ., 12 A MDmesh™ M2 Power MOSFET in I²PAK  and TO-220  packages 

**Datasheet** - **production data** 

## **Features** 

**==> picture [156 x 74] intentionally omitted <==**

**----- Start of picture text -----**<br>
TAB<br>TAB<br>1 [2] [3] 2 3<br>1<br>I [2] PAK TO-220<br>**----- End of picture text -----**<br>


|**Features**||||
|---|---|---|---|
|**Order code**|**VDS**|**RDS(on) max**|**ID**|
|STI18N65M2|650V|0.33Ω|12 A|
|STP18N65M2||||



- Extremely low gate charge 

- Excellent output capacitance (Coss) profile 

- 100% avalanche tested 

- Zener-protected 

**Figure 1. Internal schematic diagram** 

**==> picture [18 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
, TAB<br>**----- End of picture text -----**<br>


## **Applications** 

- Switching applications 

- LLC converters, resonant converters 

## **Description** 

These devices are N-channel Power MOSFETs developed using MDmesh™ M2 technology. Thanks to their strip layout and improved vertical structure, the devices exhibit low on-resistance and optimized switching characteristics, rendering them suitable for the most demanding high efficiency converters. 

|||||efficiency converters.||
|---|---|---|---|---|---|
|||AM15572v1||||
|||**Table 1. Device summary**||||
|**Order code**<br>STI18N65M2<br>STP18N65M2<br>~~——~~||**Marking**<br>18N65M2||**Package**<br>I2PAK<br>TO-220|**Packaging**<br>Tube|



_www.st.com_ 

January 2015 

DocID026870 Rev 2 

1/15 

This is information on a product in full production. 

**Contents** 

**STI18N65M2, STP18N65M2** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Test circuits     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8**|
|**4**|**Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9**|
|**5**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14**|



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**STI18N65M2, STP18N65M2** 

**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|± 25|V|
|ID|Drain current (continuous) at TC= 25 °C|12|A|
|ID|Drain current (continuous) at TC= 100 °C|8|A|
|IDM<br>(1)|Drain current (pulsed)|48|A|
|PTOT|Total dissipation at TC= 25 °C|110|W|
|dv/dt(2)|Peak diode recovery voltage slope|15|V/ns|
|dv/dt(3)|MOSFET dv/dt ruggedness|50|V/ns|
|Tstg|Storage temperature|- 55 to 150|°C|
|Tj|Max. operating junction temperature|150||



1. Pulse width limited by safe operating area 

2. ISD ≤ 12 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD=400 V. 

3. VDS ≤ 520V 

**Table 3. Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistance junction-case max|1.14|°C/W|
|Rthj-amb|Thermal resistance junction-ambient max|62.5||



**Table 4. Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR|Avalanche current, repetitive or not<br>repetitive (pulse width limited by Tjmax)|2|A|
|EAS|Single pulse avalanche energy<br>(starting Tj= 25 °C, ID= IAR; VDD= 50 V)|450|mJ|



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**STI18N65M2, STP18N65M2** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

**Table 5. On /off states** 

|||**Table 5. On /off states**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|V(BR)DSS|Drain-source<br>breakdown voltage|ID= 1 mA, VGS= 0 V|650|||V|
|IDSS|Zero gate voltage<br>drain current (VGS= 0)|VDS= 650 V|||1|µA|
|||VDS= 650 V, TC= 125 °C|||100|µA|
|IGSS|Gate-body leakage<br>current (VDS= 0)|VGS= ± 25 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 µA|2|3|4|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID= 6 A||0.275|0.33|Ω|



**Table 6. Dynamic** 

|||**Table 6. Dynamic**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0 V|-|770|-|pF|
|Coss|Output capacitance||-|35|-|pF|
|Crss|Reverse transfer<br>capacitance||-|1.2|-|pF|
|Coss eq.<br>(1)|Equivalent output<br>capacitance|VDS= 0 to 480 V, VGS= 0 V|-|175|-|pF|
|RG|Intrinsic gate<br>resistance|f = 1 MHz, ID= 0 A|-|6.1|-|Ω|
|Qg|Total gate charge|VDD= 520 V, ID= 12 A,<br>VGS= 10 V (see_Figure 15_)|-|20|-|nC|
|Qgs|Gate-source charge||-|3.6|-|nC|
|Qgd|Gate-drain charge||-|8.5|-|nC|



1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

**Table 7. Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 325 V, ID= 6 A,<br>RG= 4.7Ω,VGS= 10 V<br>(see_Figure 14_and_Figure 19_)|-|11|-|ns|
|tr|Rise time||-|7.5|-|ns|
|td(off)|Turn-off delay time||-|46|-|ns|
|tf|Fall time||-|12.5|-|ns|



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**STI18N65M2, STP18N65M2** 

**Electrical characteristics** 

**Table 8. Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||12|A|
|ISDM (1)|Source-drain current (pulsed)||-||48|A|
|VSD (2)|Forward on voltage|ISD= 12 A, VGS= 0 V|-||1.6|V|
|trr|Reverse recovery time|ISD= 12 A, di/dt = 100 A/µs<br>VDD= 60 V (see_Figure 16_)|-|331||ns|
|Qrr|Reverse recovery charge||-|3.4||µC|
|IRRM|Reverse recovery current||-|20.5||A|
|trr|Reverse recovery time|ISD= 12 A, di/dt = 100 A/µs<br>VDD= 60 V, Tj= 150 °C<br>(see_Figure 16_)|-|462||ns|
|Qrr|Reverse recovery charge||-|4.6||µC|
|IRRM|Reverse recovery current||-|20||A|



1. Pulse width limited by safe operating area. 

2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

DocID026870 Rev 2 

5/15 

**STI18N65M2, STP18N65M2** 

**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2. Safe operating area** 

## **Figure 3. Thermal impedance** 

## **Figure 4. Output characteristics** 

## **Figure 5. Transfer characteristics** 

## **Figure 6. Gate charge vs gate-source voltage** 

## **Figure 7. Static drain-source on-resistance** 

6/15 

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**STI18N65M2, STP18N65M2** 

**Electrical characteristics** 

**Figure 8. Capacitance variations** 

**Figure 10. Normalized gate threshold voltage vs temperature** 

**Figure 12. Source-drain diode forward characteristics** 

## **Figure 9. Output capacitance stored energy** 

**Figure 11. Normalized on-resistance vs temperature** 

**Figure 13. Normalized V(BR)DSS vs temperature** 

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**STI18N65M2, STP18N65M2** 

**Test circuits** 

## **3 Test circuits** 

**Figure 14. Switching times test circuit for resistive load** 

**Figure 15. Gate charge test circuit** 

**==> picture [460 x 326] intentionally omitted <==**

**----- Start of picture text -----**<br>
RL 2200 3.3<br>μF μF<br>VDD | =CONST<br>— VD V=20V=Veun © 1000 D.UT.<br>VGS<br>IL RG D.U.T. T5000 7 C } 14<br>PW LZ }<br>| 7 = c s /|2.7ka y.<br>JL aa ctL _t 47kQ<br>AM01468v1 PW | 1kQ AM01469v1<br>Figure 16. Test circuit for inductive load  Figure 17. Unclamped inductive load test circuit<br>switching and diode recovery times<br>L<br>A A A<br>D<br>FAST L=100μH VD<br>G D.U.T. DIODE 2200 3.3<br>S B 3.3 1000 μF μF VDD<br>25 Ω B B D μF μF VDD ID<br>G<br>RG S<br>Vi D.U.T.<br>Pw<br>AM01470v1 AM01471v1<br>ai att<br>Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform<br>**----- End of picture text -----**<br>


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**STI18N65M2, STP18N65M2** 

**Package mechanical data** 

## **4 Package mechanical data** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _www.st.com_ . ECOPACK[®] is an ST trademark. 

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**STI18N65M2, STP18N65M2** 

**Package mechanical data** 

**==> picture [162 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 20. I²PAK (TO-262) drawing<br>**----- End of picture text -----**<br>


**==> picture [405 x 320] intentionally omitted <==**

**----- Start of picture text -----**<br>
0004982_Rev_H<br>**----- End of picture text -----**<br>


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**Package mechanical data** 

**Table 9. I²PAK (TO-262) mechanical data** 

||**Table 9. I²PAK(TO-262) mechanical data**|**Table 9. I²PAK(TO-262) mechanical data**|**Table 9. I²PAK(TO-262) mechanical data**|
|---|---|---|---|
|**DIM.**|**mm.**|||
||**min.**|**typ**|**max.**|
|A|4.40||4.60|
|A1|2.40||2.72|
|b|0.61||0.88|
|b1|1.14||1.70|
|c|0.49||0.70|
|c2|1.23||1.32|
|D|8.95||9.35|
|e|2.40||2.70|
|e1|4.95||5.15|
|E|10||10.40|
|L|13||14|
|L1|3.50||3.93|
|L2|1.27||1.40|



DocID026870 Rev 2 

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**STI18N65M2, STP18N65M2** 

**Package mechanical data** 

**Figure 21. TO-220 type A drawing** 

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**STI18N65M2, STP18N65M2** 

**Package mechanical data** 

**Table 10. TO-220 type A mechanical data** 

||**Table 10. TO-220 type A mechanical data**|**Table 10. TO-220 type A mechanical data**|**Table 10. TO-220 type A mechanical data**|
|---|---|---|---|
|**Dim.**|**mm**|||
||**Min.**|**Typ.**|**Max.**|
|A|4.40||4.60|
|b|0.61||0.88|
|b1|1.14||1.70|
|c|0.48||0.70|
|D|15.25||15.75|
|D1||1.27||
|E|10||10.40|
|e|2.40||2.70|
|e1|4.95||5.15|
|F|1.23||1.32|
|H1|6.20||6.60|
|J1|2.40||2.72|
|L|13||14|
|L1|3.50||3.93|
|L20||16.40||
|L30||28.90||
|∅P|3.75||3.85|
|Q|2.65||2.95|



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**STI18N65M2, STP18N65M2** 

**Revision history** 

## **5 Revision history** 

**Table 11. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|16-Dec-2014|1|First release.|
|09-Jan-2015|2|Text edits throughout document<br>Updated_Figure 6: Gate charge vs gate-source voltage_|



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**STI18N65M2, STP18N65M2** 

## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2015 STMicroelectronics – All rights reserved 

DocID026870 Rev 2 

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