# Power MOSFET, P Channel, 40 V, 8 A, 0.0175 ohm, PowerFLAT, Surface Mount

![Product image](https://novapart.co/image/farnell:3129857/)

**URL**: https://novapart.co/products/STL8P4LLF6/power-mosfet-p-channel-40-v-8-a-00175-ohm
**SKU**: STL8P4LLF6
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.3620
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:P Channel; Continuous Drain Current Id:-8A; Drain Source Voltage Vds:-40V; On Resistance Rds(on):0.0175ohm; Rds(on) Test Voltage Vgs:-10V; Threshold Voltage V

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | P Channel |
| Product Range | STripFET F6 |
| Qualification | - |
| Power Dissipation | 2.9W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | PowerFLAT |
| Drain Source Voltage Vds | 40V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 8A |
| Drain Source On State Resistance | 0.0175ohm |
| Gate Source Threshold Voltage Max | 2.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3129857/)

## **STL8P4LLF6** 

P-channel 40 V, 0.0175 Ω typ.,8 A, STripFET™ F6 Power MOSFET in a PowerFLAT™ 3.3 x 3.3 package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS**|**RDS(on) max.**|**ID**|**PTOT**|
|---|---|---|---|---|
|STL8P4LLF6|40 V|0.0205 Ω|8 A|2.9 W|



**==> picture [92 x 71] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>2<br>3<br>4<br>PowerFLAT™ 3.3x3.3<br>**----- End of picture text -----**<br>


- Very low on-resistance 

- Very low gate charge 

- High avalanche ruggedness 

- Low gate drive power loss 

## **Applications** 

- Switching applications 

**Figure 1: Internal schematic diagram** 

## **Description** 

This device is a P-channel Power MOSFET developed using the STripFET™ F6 technology, with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. 

- [For the P-channel Power MOSFET, current ] polarity of voltages and current have to be reversed. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packaging**|
|---|---|---|---|
|STL8P4LLF6|8P4F6|PowerFLAT™ 3.3 x 3.3|Tape and reel|



March 2015 

DocID025617 Rev 2 

1/14 

This is information on a product in full production. 

_www.st.com_ 

|**Contents**<br>**STL8P4LLF6**|**Contents**<br>**STL8P4LLF6**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>PowerFLAT™ 3.3x3.3 package information .................................... 10|
|**5**|**Revision history ............................................................................ 13**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|40|V|
|VGS|Gate-source voltage|± 20|V|
|ID<br>_(1)_|Drain current (continuous) at Tpcb= 25 °C|8|A|
|ID<br>_(1)_|Drain current (continuous) at Tpcb= 100 °C|5|A|
|IDM<br>_(1)(2)_|Drain current (pulsed)|32|A|
|PTOT|Total dissipation at Tpcb= 25 °C|2.9|W|
|Tstg|Storage temperature|-55 to 150|°C|
|Tj|Maximumjunction temperature|150|°C|



## **Notes:** 

(1) this value is related to Rthj-pcb 

(2) Pulse width limited by safe operating area. 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case max|2.50|°C/W|
|Rthj-pcb<br>_(1)_|Thermal resistancejunction-pcb max.|42.8|°C/W|



## **Notes:** 

(1)When mounted on FR-4 board of 1 inch², 2oz Cu, t ≤ 10 s 

For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed. 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

|**Table 4: Static**|
|---|
|**Symbol**<br>**Parameter**<br>**Test conditions**<br>**Min.**<br>**Typ.**<br>**Max.**<br>**Unit**<br>V(BR)DSS<br>Drain-source breakdown<br>voltage<br>VGS= 0 V, ID= 250 µA<br>40<br>V<br>IDSS<br>Zero gate voltage Drain<br>current<br>VGS= 0 V, VDS= 40 V<br>1<br>µA<br>VGS= 0 V, VDS= 40 V,<br>TC= 125 °C<br>10<br>µA<br>IGSS<br>Gate-body leakage<br>current<br>VDS= 0 V, VGS= ± 20 V<br>±100<br>nA<br>VGS(th)<br>Gate threshold voltage<br>VDS= VGS, ID= 250µA<br>1<br>2.5<br>V<br>~~aee~~<br>~~ee ee~~<br>~~ee~~<br>~~esoe~~<br>~~a~~<br>~~ee~~<br>~~ee ee~~<br>~~a~~|
|RDS(on)<br>Static drain-source on-<br>resistance<br>VGS= 10 V, ID= 4 A<br>0.0175<br>0.0205<br>Ω<br>VGS= 4.5 V, ID= 4 A<br>0.021<br>0.029<br>~~a~~|
|**Table 5: Dynamic**|
|**Symbol**<br>**Parameter**<br>**Test conditions**<br>**Min.**<br>**Typ.**<br>**Max.**<br>**Unit**<br>Ciss<br>Input capacitance<br>VDS= 25 V, f = 1 MHz,<br>VGS= 0 V<br>-<br>2850<br>-<br>pF<br>Coss<br>Output capacitance<br>-<br>270<br>-<br>pF<br>Crss<br>Reverse transfer<br>capacitance<br>-<br>180<br>-<br>pF<br>Qg<br>Totalgate charge<br>VDD= 20 V, ID= 8 A,<br>VGS= 4.5 V (see_Figure_<br>_14: "Gate charge test_<br>_circuit"_)<br>-<br>22<br>-<br>nC<br>Qgs<br>Gate-source charge<br>-<br>9.4<br>-<br>nC<br>Qgd<br>Gate-drain charge<br>-<br>7.3<br>-<br>nC<br>~~a~~<br>~~a~~<br>~~es~~<br>~~oF~~<br>~~Pot~~<br>~~et~~<br>~~|~~<br>~~oe~~<br>~~ee~~<br>~~es~~|
|ID= 0 A, gate DC|
|RG<br>Gate input resistance<br>bias = 0 V, f = 1 MHz,<br>magnitude of alternative<br>-<br>1.4<br>-<br>Ω|
|signal = 20 mV|
|**Table 6: Switching times**|
|**Symbol**<br>**Parameter**<br>**Test conditions**<br>**Min.**<br>**Typ.**<br>**Max.**<br>**Unit**|
|td(on)<br>Turn-on delaytime<br>VDD= 20 V, ID= 4 A<br>-<br>43<br>-<br>ns|
|RG= 4.7 Ω, VGS= 10 V<br>tr<br>Rise time<br>-<br>47<br>-<br>ns|
|(see_Figure 13:_<br>_"Switching times test_<br>td(off)<br>Turn-off-delaytime<br>-<br>148<br>-<br>ns|
|_circuit for resistive load"_)<br>tf<br>Fall time<br>-<br>19<br>-<br>ns|



For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed. ~~©~~ 4/14 DocID025617 Rev 2 

**STL8P4LLF6** 

**Electrical characteristics** 

**Table 7: Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VSD<br>_(1)_|Forward on voltage|VGS= 0 V, ISD= 8 A|-||1.1|V|
|trr|Reverse recoverytime|ISD= 8 A,<br>di/dt = 100 A/µs,<br>VDD= 32 V, Tj= 150 °C<br>(see_Figure 15: "Test_<br>_circuit for inductive load_<br>_switching and diode_<br>_recovery times"_)|-|26||ns|
|Qrr|Reverse recovery<br>charge||-|21||nC|
|IRRM|Reverse recovery<br>current||-|1.7||A|



## **Notes:** 

(1) Pulse test: pulse duration = 300 µs, duty cycle 1.5% 

For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed. 

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**STL8P4LLF6** 

**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**==> picture [384 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


**Figure 4: Output characteristics Figure 5: Transfer characteristics** 

**==> picture [150 x 144] intentionally omitted <==**

**==> picture [150 x 144] intentionally omitted <==**

**==> picture [406 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 6: Normalized gate threshold voltage  Figure 7: Normalized V(BR)DSS vs<br>vs temperature  temperature<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

**==> picture [404 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 9: Normalized on-resistance vs.<br>Figure 8: Static drain-source on-resistance<br>temperature<br>**----- End of picture text -----**<br>


**==> picture [394 x 180] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 10: Gate charge vs gate-source<br>Figure 11: Capacitance variations voltage<br>voltage<br>**----- End of picture text -----**<br>


**Figure 12: Source-drain diode forward characteristics** 

**==> picture [151 x 144] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**Figure 13: Switching times test circuit for Figure 14: Gate charge test circuit resistive load** 

**==> picture [163 x 83] intentionally omitted <==**

**==> picture [180 x 109] intentionally omitted <==**

**Figure 15: Test circuit for inductive load switching and diode recovery times** 

**==> picture [215 x 126] intentionally omitted <==**

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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package information** 

## **4.1 PowerFLAT™ 3.3x3.3 package information** 

**Figure 16: PowerFLAT™ 3.3x3.3 package outline** 

**==> picture [406 x 574] intentionally omitted <==**

**----- Start of picture text -----**<br>
BOTTOM VIEW<br>SIDE VIEW<br>TOP VIEW<br>8465286_A<br>**----- End of picture text -----**<br>


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**Package information** 

|**F6**||**Package information**|**Package information**|
|---|---|---|---|
||**Table 8: PowerFLAT™**|**3.3x3.3 mechanical data**||
|**Dim.**||**mm**||
||**Min.**|**Typ.**|**Max.**|
|A|0.70|0.80|0.90|
|b|0.25|0.30|0.39|
|c|0.14|0.15|0.20|
|D|3.10|3.30|3.50|
|D1|3.05|3.15|3.25|
|D2|2.15|2.25|2.35|
|e|0.55|0.65|0.75|
|E|3.10|3.30|3.50|
|E1|2.90|3.00|3.10|
|E2|1.60|1.70|1.80|
|H|0.25|0.40|0.55|
|K|0.65|0.75|0.85|
|L|030|0.45|0.60|
|L1|0.05|0.15|0.25|
|L2|||0.5|
|ϑ|8°|10°|12°|



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**Package information** 

**Figure 17: PowerFLAT™ 3.3x3.3 recommended footprint** 

**==> picture [406 x 347] intentionally omitted <==**

**----- Start of picture text -----**<br>
8465286_footprint<br>**----- End of picture text -----**<br>


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**Revision history** 

## **5 Revision history** 

**Table 9: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|28-Jan-2014|1|Initial release.|
|24-Mar-2015|2|Text edits throughout document<br>On cover page, updated title, description and features table<br>Updated Table 4: Static<br>Updated Table 5: Dynamic<br>Updated Table 6: Switching times<br>Updated Table 7: Source-drain diode<br>Added Section 2.1: Electrical characteristics (curves)<br>Renamed and updated Section 4.1 PowerFLAT™ 3.3 x 3.3 package<br>information|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2015 STMicroelectronics – All rights reserved 

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