# Power MOSFET, N Channel, 100 V, 8 A, 0.017 ohm, PowerFLAT, Surface Mount

![Product image](https://novapart.co/image/farnell:2784050/)

**URL**: https://novapart.co/products/STL8N10F7/power-mosfet-n-channel-100-v-8-a-0017-ohm
**SKU**: STL8N10F7
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.3980
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:8A; Drain Source Voltage Vds:100V; On Resistance Rds(on):0.017ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4.5V; P

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 50W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | PowerFLAT |
| Drain Source Voltage Vds | 100V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 8A |
| Drain Source On State Resistance | 0.017ohm |
| Gate Source Threshold Voltage Max | 4.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2784050/)

## **STL8N10F7** 

N-channel 100 V, 0.017 Ω typ., 35 A, STripFET™ F7 Power MOSFET in a PowerFLAT™ 3.3 x 3.3 package 

**Datasheet** - **preliminary data** 

## **Features** 

|**Features**|**Features**||||
|---|---|---|---|---|
|**Order code**|**VDS**|**RDS(on)max**|**ID**|**PTOT**|
|STL8N10F7|100 V|0.02Ω|35 A|50 W|



- Among the lowest RDS(on) on the market 

**==> picture [34 x 24] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>2<br>3<br>4<br>**----- End of picture text -----**<br>


**PowerFLAT™ 3.3 x 3.3** 

- Excellent figure of merit (FoM) 

- Low Crss/Ciss ratio for EMI immunity 

- High avalanche ruggedness 

## **Applications** 

- Switching applications 

## **Figure 1.  Internal schematic diagram** 

## **Description** 

**==> picture [213 x 150] intentionally omitted <==**

**----- Start of picture text -----**<br>
D(5, 6, 7, 8)<br>8 7 6 5<br>G(4)<br>S(1, 2, 3) 1 2 3 4<br>AM15810v1<br>**----- End of picture text -----**<br>


This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. 

**Table 1. Device summary** 

|**Order code**<br>~~———~~|**Marking**<br>~~———~~|**Package**<br>~~———~~|**Packaging**<br>~~———~~|
|---|---|---|---|
|STL8N10F7<br>~~———~~|8N10F<br>~~———~~|PowerFLAT™ 3.3 x 3.3<br>~~———~~|Tape and reel<br>~~———~~|



December 2014 DocID025076 Rev 2 

1/14 _www.st.com_ 

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

**Contents** 

**STL8N10F7** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Test circuits     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8**|
|**4**|**Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9**|
|**5**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13**|



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**STL8N10F7** 

**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|100|V|
|VGS|Gate-source voltage|± 20|V|
|ID<br>(1)|Drain current (continuous) at TC= 25 °C|8|A|
|ID<br>(1)|Drain current (continuous) at TC= 100 °C|6|A|
|IDM<br>(1)(2)|Drain current (pulsed)|32|A|
|ID<br>(3)|Drain current (continuous) at Tpcb= 25 °C|35|A|
|ID<br>(3)|Drain current (continuous) at Tpcb= 100 °C|22|A|
|IDM<br>(2)(3)|Drain current (pulsed)|140|A|
|PTOT<br>(3)|Total dissipation at Tcase= 25 °C|50|W|
|PTOT<br>(1)|Total dissipation at Tpcb= 25 °C|3.5|W|
|TJ|Operating junction temperature|-55 to 150|°C|
|Tstg|Storage temperature||°C|



1. This value is rated according to Rthj-pcb. 

2. Pulse width limited by safe operating area. 

3. This value is rated according to Rthj-case. 

**Table 3. Thermal resistance** 

||**Table 3. Thermal resistance**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|Rthj-pcb<br>(1)|Thermal resistance junction-pcb|42.8|°C/W|
|Rthj-case|Thermal resistance junction-case|2.5|°C/W|



1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec 

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**STL8N10F7** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(TCASE=25 °C unless otherwise specified) 

**Table 4. On/off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|ID= 1 mA; VGS= 0|100|||V|
|IDSS|Zero gate voltage drain<br>current|VDS= 100 V; VGS= 0|||1|µA|
|||VDS= 100 V; VGS= 0;<br>TC=125 °C|||100|µA|
|IGSS|Gate body leakage current|VGS= 20 V; VDS= 0|||100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 µA|2.5||4.5|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 4 A||0.017|0.02|Ω|



**Table 5. Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS=50 V, f=1 MHz,<br>VGS=0|-|1640|-|pF|
|Coss|Output capacitance||-|360|-|pF|
|Crss|Reverse transfer<br>capacitance||-|25|-|pF|
|Qg|Total gate charge|VDD=50 V, ID= 8 A<br>VGS=10 V<br>_Figure 14_|-|25|-|nC|
|Qgs|Gate-source charge||-|12|-|nC|
|Qgd|Gate-drain charge||-|5|-|nC|



## **Table 6. Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD=50 V, ID= 4 A,<br>RG=4.7Ω,VGS= 10 V<br>_Figure 13_|-<br>-<br>-<br>-|15|-|ns|
|tr|Rise time|||17|-|ns|
|td(off)|Turn-off delay time|||24|-|ns|
|tf|Fall time|||8|-|ns|



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**Electrical characteristics** 

**Table 7. Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min**|**Typ.**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VSD<br>(1)|Forward on voltage|ISD= 8 A, VGS=0|-|-|1.1|V|
|trr|Reverse recovery time|ISD= 8 A,<br>di/dt = 100 A/µs,<br>VDD=80 V, Tj=150 °C|-|53||ns|
|Qrr|Reverse recovery charge||-|67||nC|
|IRRM|Reverse recovery current||-|2.5||A|



1. Pulsed: pulse duration=300 µs, duty cycle 1.5% 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2. Safe operating area** 

## **Figure 3. Thermal impedance** 

**Figure 4. Output characteristics** 

## **Figure 5. Transfer characteristics** 

**Figure 6. Normalized gate threshold voltage vs. temperature** 

**Figure 7. Normalized V(BR)DSS vs. temperature** 

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**Electrical characteristics** 

**Figure 8. Static drain-source on-resistance** 

**Figure 10. Gate charge vs. gate-source voltage** 

**Figure 9. Normalized on-resistance vs. temperature** 

**Figure 11. Capacitance variations** 

**==> picture [198 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
C AM16114v1<br>(pF)<br>Ciss<br>1000<br>Coss<br>100<br>Crss<br>0<br>0 20 40 60 80 VDS(V)<br>**----- End of picture text -----**<br>


**Figure 12. Source-drain diode forward characteristics** 

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**Test circuits** 

## **3 Test circuits** 

**Figure 13. Switching times test circuit for resistive load** 

**Figure 14. Gate charge test circuit** 

**==> picture [462 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>12V 47kΩ<br>1kΩ<br>100nF<br>RL 2200 3.3<br>μF μF<br>VDD IG=CONST<br>VD Vi=20V=VGMAX 100Ω D.U.T.<br>VGS<br>2200<br>RG D.U.T. μF 2.7kΩ VG<br>PW<br>47kΩ<br>1kΩ<br>PW<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


**Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test circuit switching and diode recovery times** 

**==> picture [462 x 346] intentionally omitted <==**

**----- Start of picture text -----**<br>
L<br>A A A<br>D<br>FAST L=100μH VD<br>G D.U.T. DIODE 2200 3.3<br>S B 3.3 1000 μF μF VDD<br>25 Ω B B D μF μF VDD ID<br>G<br>RG S<br>Vi D.U.T.<br>Pw<br>AM01470v1 AM01471v1<br>Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform<br>V(BR)DSS ton toff<br>VD tdon tr tdoff tf<br>90% 90%<br>IDM<br>10%<br>ID 0 10% VDS<br>VDD VDD 90%<br>VGS<br>AM01472v1 0 10% AM01473v1<br>**----- End of picture text -----**<br>


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**Package mechanical data** 

## **4 Package mechanical data** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _www.st.com_ . ECOPACK[®] is an ST trademark. 

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**Package mechanical data** 

**Table 8.PowerFLAT™ 3.3 x 3.3 mechanical data** 

||**Table 8.PowerFLAT™ 3.3 x 3.3 mechanical data**|**Table 8.PowerFLAT™ 3.3 x 3.3 mechanical data**|**Table 8.PowerFLAT™ 3.3 x 3.3 mechanical data**|
|---|---|---|---|
|**Dim.**|**mm**|||
||**Min.**|**Typ.**|**Max.**|
|A|0.70|0.80|0.90|
|b|0.25|0.30|0.39|
|c|0.14|0.15|0.20|
|D|3.10|3.30|3.50|
|D1|3.05|3.15|3.25|
|D2|2.15|2.25|2.35|
|e|0.55|0.65|0.75|
|E|3.10|3.30|3.50|
|E1|2.90|3.00|3.10|
|E2|1.60|1.70|1.80|
|H|0.25|0.40|0.55|
|K|0.65|0.75|0.85|
|L|0.30|0.45|0.60|
|L1|0.05|0.15|0.25|
|L2|||0.15|
|ϑ|8°|10°|12°|



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**Package mechanical data** 

**Figure 19. PowerFLAT™ 3.3 x 3.3 drawing** 

**==> picture [405 x 613] intentionally omitted <==**

**----- Start of picture text -----**<br>
BOTTOM VIEW<br>SIDE VIEW<br>TOP VIEW<br>8465286_A<br>**----- End of picture text -----**<br>


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11/14<br>**----- End of picture text -----**<br>


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**Package mechanical data** 

**==> picture [282 x 13] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 20. PowerFLAT™ 3.3 x 3.3 recommended footprint [(a)]<br>**----- End of picture text -----**<br>


**==> picture [405 x 426] intentionally omitted <==**

**----- Start of picture text -----**<br>
8465286_footprint<br>**----- End of picture text -----**<br>


- a. All dimensions are in millimeters 

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**Revision history** 

## **5 Revision history** 

**Table 9. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|31-Jul-2013|1|First release.|
|05-Dec-2014|2|Document status promoted from preliminary to production data.<br>Modified title, features and description in cover page.<br>Modified: RDS(on)typical and max values in first page and in_Table 4:_<br>_On/off states_<br>Modified:_Section 4: Package mechanical data_<br>Added_Section 2.1: Electrical characteristics (curves)_.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2014 STMicroelectronics – All rights reserved 

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