# Power MOSFET, N Channel, 100 V, 20 A, 0.025 ohm, PowerFLAT, Surface Mount

![Product image](https://novapart.co/image/farnell:2807206/)

**URL**: https://novapart.co/products/STL8DN10LF3/power-mosfet-n-channel-100-v-20-a-0025-ohm
**SKU**: STL8DN10LF3
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.7490
**Stock**: 10+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:20A; Drain Source Voltage Vds:100V; On Resistance Rds(on):0.025ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | STripFET F3 |
| Qualification | AEC-Q101 |
| Power Dissipation | 70W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | PowerFLAT |
| Drain Source Voltage Vds | 100V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 20A |
| Drain Source On State Resistance | 0.025ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2807206/)

## **STL8DN10LF3** 

Automotive-grade dual N-channel 100 V, 25 mΩ typ., 7.8 A STripFET™ F3 Power MOSFET in a PowerFLAT™ 5x6 DI 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS**|**RDS(on) max.**|ID|
|---|---|---|---|
|STL8DN10LF3|100 V|35 mΩ|7.8 A|



- Designed for automotive applications and AEC-Q101 qualified 

- Logic level VGS(th) 

- 175 °C maximum junction temperature 

- 100% avalanche rated 

- Wettable flank package 

## **Applications** 

- Switching applications 

## **Description** 

**Figure 1: Internal schematic diagram** 

This device is an N-channel Power MOSFET developed using STripFET™ F3 technology. It is designed to minimize on-resistance and gate charge to provide superior switching performance. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STL8DN10LF3|8DN10LF3|PowerFLATTM5x6 double island|Tape and reel|



DocID023009 Rev 8 

This is information on a product in full production. 

_www.st.com_ 

June 2016 

1/15 

**Contents** 

**STL8DN10LF3** 

## **Contents** 

|**1**|**Electrical ratings ............................................................................. 3**|
|---|---|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>PowerFLAT ™ 5x6 double island package information ..................... 9|
||4.2<br>Packing information ......................................................................... 12|
|**5**|**Revision history ............................................................................ 14**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|100|V|
|VGS|Gate-source voltage|±20|V|
|ID_(1)_|Drain current (continuous) at TC= 25 °C|20|A|
|ID_(1)_|Drain current (continuous) at Tc= 100 °C|20|A|
|ID_(2)_|Drain current (continuous) at Tpcb= 25 °C|7.8|A|
|ID_(2)_|Drain current (continuous) at Tpcb= 100 °C|5.5|A|
|IDM_(2)(3)_|Drain current (pulsed)|31.2|A|
|PTOT_(1)_|Total dissipation at TC= 25 °C|70|W|
|PTOT_(2)_|Total dissipation at Tpcb= 25°C|4.3|W|
|IAV|Not-repetitive avalanche current|7.8|A|
|EAS|Singlepulse avalanche energy|190|mJ|
|Tj|Operating junction temperature range|-55 to 175|°C|
|Tstg|Storage temperature range|||



## **Notes:** 

- (1)This value is rated according to Rthj-case and limited by package 

(2)The value is rated according to Rthj-pcb 

- (3)Pulse width limited by safe operating area. 

**Table 3: Thermal resistance** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|2.1|°C/W|
|Rthj-pcb_(1)_|Thermal resistancejunction-pcb|35|°C/W|



## **Notes:** 

- (1)When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s. 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

**Table 4: On/Off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown voltage|ID= 250 μA, VGS= 0 V|100|||V|
|IDSS|Zero gate voltage<br>drain current (VGS= 0)|VDS= 100 V|||1|µA|
|IGSS|Gate-body leakage<br>current(VDS= 0)|VGS= ±20 V|||±100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 μA|1||3|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID= 4 A||25|35|mΩ|
|||VGS= 5 V, ID= 4 A||40|50|mΩ|



## **Table 5: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 25 V, f = 1 MHz,<br>VGS= 0 V|-|970|-|pF|
|Coss|Output capacitance||-|115|-||
|Crss|Reverse transfer capacitance||-|11.5|-||
|Qg|Totalgate charge|VDD= 50 V, ID= 7.8 A,<br>VGS= 10 V (see_Figure_<br>_13: "Test circuit for gate_<br>_charge behavior"_)|-|20.5|-|nC|
|Qgs|Gate-source charge||-|4|-||
|Qgd|Gate-drain charge||-|5|-||
|RG|Intrinsic gate resistance|f =1 MHz open drain|-|3.65|-|Ω|



**Table 6: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 50 V, ID= 7.8 A,<br>RG= 4.7 Ω, VGS= 10 V (see<br>_Figure 12: "Test circuit for_<br>_resistive load switching_<br>_times"_)|-|8.7|-|ns|
|tr|Rise time||-|9.6|-||
|td(off)|Turn-off delay time||-|50.6|-||
|tf|Fall time||-|5.2|-||



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**Electrical characteristics** 

**Table 7: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||7.8|A|
|ISDM_(1)_|Source-drain current<br>(pulsed)||-||31.2|A|
|VSD_(2)_|Forward on voltage|IDS= 7.8 A, VGS= 0|||1.3|V|
|trr|Reverse recoverytime|ISD= 7.8 A, di/dt = 100 A/µs<br>VDD= 48 V, Tj= 150 °C (see<br>_Figure 14: "Test circuit for_<br>_inductive load switching and_<br>_diode recovery times"_)|-|42.5||ns|
|Qrr|Reverse recovery charge||-|87||nC|
|IRRM|Reverse recovery current||-|4.08||A|



## **Notes:** 

(1)Pulse width limited by safe operating area 

(2)Pulsed: pulse duration = 300 μs, duty cycle 1.5 % 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**==> picture [458 x 641] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>( ==Steve eeStierseerI ms7A d 3 TegoeaZth_AM13007V1<br>aie<br>mill<br>nee al<br>ao<br>A K Bi P D HeE e oe a l ie etnias i e<br>tk-oTcoca:SNE |<br>7 k Rins-peb<br>Ko ee a 2 is lll |<br>é =<. AN nNms |<br>Ktomar:<br>jeri=aHee = a a SiF sisingeett = il L<br>HHF Stiett aH ianil| illial is 3 - p | Stesraici<br>o n |  EUTIh 10 (V) ee 10 10ay mes 10  v9<br>Figure 4: Output characteristics  Figure 5: Transfer characteristics<br>ID AM13018v1 » AM13<br>(A)25 VGS  = 6, 7 ,8 ,9, 10 V ai (A) ||L{|+Tt| orev)<br>20 (ieeeee 5V HH i; |fooe|_|7|<br>HA | 20) | =oH<br>fo |_| y ||<br>15 eS steete 4V Foe| |_|SH/ |<br>Pinal |_| | |_|an_| |_|<br>iF Aatana = EEEa Too<br>10 feta =<br>5 lanpecaeaeae= 104FEES<br>casesasae nine<br>0 ‘apfae.caneeeee| |So= 5Fop44||mins+f<br>0 1 2 3 4 VDS(V) 154icra2 4 .<br>Figure 6: Gate charge vs gate-source voltage  Figure 7: Static drain-source on-resistance<br>* aMvm ama20<br>" ( mΩ a 7—<br>vest w<br> p TT mAL = Po<br>aoe 7 aan | |<br>vo" ofan 6 aon+++<br>2fineaay,f-Zoa- 25.  t=Po+<br>10°yffir aiit. 2|e pescanbe| || ae | |<br>pp caait penatean |<br>annPERCE= {iT7ocoeea|<br>ELECSe 244=" feeeee |<br>20 17 |_| 10 aa(n) ‘  REEE | L_ 1 Zane=<br>6/15 DocID023009 Rev 8<br>**----- End of picture text -----**<br>


**STL8DN10LF3** 

**==> picture [377 x 34] intentionally omitted <==**

**----- Start of picture text -----**<br>
Electrical characteristics<br>Figure 9: Normalized gate threshold voltage<br>Figure 8: Capacitance variations<br>vs temperature<br>**----- End of picture text -----**<br>


**Figure 10: Normalized on-resistance vs Figure 11: Normalized V(BR)DSS vs temperature temperature** 

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 578] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 12: Test circuit for resistive load  Figure 13: Test circuit for gate charge<br>switching times  behavior<br>Figure 14: Test circuit for inductive load<br>Figure 15: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>Figure 16: Unclamped inductive waveform  Figure 17: Switching time waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 PowerFLAT ™ 5x6 double island package information** 

**Figure 18: PowerFLAT™ 5x6 double island WF type R package outline** 

**==> picture [405 x 497] intentionally omitted <==**

**----- Start of picture text -----**<br>
8256945_r16_typeR-WF<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 8: PowerFLAT™ 5x6 double island WF type R mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|0.80||1.00|
|A1|0.02||0.05|
|A2||0.25||
|b|0.30||0.50|
|C|5.80|6.00|6.10|
|D|5.00|5.20|5.40|
|D2|4.15||4.45|
|D3|4.05|4.20|4.35|
|D4|4.80|5.00|5.10|
|D5|0.25|0.40|0.55|
|D6|0.15|0.30|0.45|
|D7|1.68||1.98|
|e||1.27||
|E|6.20|6.40|6.60|
|E2|3.50||3.70|
|E3|2.35||2.55|
|E4|0.40||0.60|
|E5|0.08||0.28|
|E6|0.20|0.325|0.45|
|E7|0.85|1.00|1.15|
|E8|0.55||0.75|
|E9|4.00|4.20|4.40|
|E10|3.55|3.70|3.85|
|K|1.275||1.575|
|L|0.725|0.825|0.925|
|L1|0.175|0.275|0.375|
|θ|0°||12°|



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**Package information** 

**Figure 19: PowerFLAT™ 5x6 double island recommended footprint (dimensions are in mm)** 

**==> picture [406 x 342] intentionally omitted <==**

**----- Start of picture text -----**<br>
8256945_FP_std_R16<br>**----- End of picture text -----**<br>


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**Package information** 

## **4.2 Packing information** 

**Figure 20: PowerFLAT™ 5x6 WF tape (dimensions are in mm)** 

**Figure 21: PowerFLAT™ 5x6 package orientation in carrier tape** 

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**Package information** 

**Figure 22: PowerFLAT™ 5x6 reel (dimensions are in mm)** 

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**Revision history** 

## **5 Revision history** 

**Table 9: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|28-Mar-2012|1|First release.|
|20-Jun-2012|2|Added Section 2.1: Electrical characteristics (curves). Updated<br>Section 4: Package information and title on the coverpage..|
|26-Jun-2012|3|Updated Figure 9: Capacitance variations. Document status<br>promoted frompreliminarytoproduction data|
|28-Oct-2013|4|– Updated: Section 4: Package information and Section 5: Packing<br>information Updated title and features in cover page – Modified:<br>VGS(th) value in Table 4 – Minor text changes|
|20-Feb-2014|5|Added: Features in cover page – Added: note 1 in Table 1 – Added:<br>Table 19 and Table 9 – Added: Figure 20 – Minor text changes|
|10-Jul-2015|6|Updated title and description in cover page. – Updated Section 4:<br>Package information.|
|09-Jun-2016|7|Updated Silhouette and description in cover page.<br>Updated Figure 18: "PowerFLAT™ 5x6 double island WF type R<br>package outline".<br>Minor text changes.|
|21-Jun-2016|8|Updated_Figure 18: "PowerFLAT™ 5x6 double island WF type R_<br>_package outline"_.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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