# Power MOSFET, N Channel, 60 V, 20 A, 0.035 ohm, PowerFLAT, Surface Mount

![Product image](https://novapart.co/image/farnell:2807205/)

**URL**: https://novapart.co/products/STL7N6LF3/power-mosfet-n-channel-60-v-20-a-0035-ohm
**SKU**: STL7N6LF3
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.3930
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:20A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.035ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:2.5

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | STripFET F3 |
| Qualification | AEC-Q101 |
| Power Dissipation | 52W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | PowerFLAT |
| Drain Source Voltage Vds | 60V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 20A |
| Drain Source On State Resistance | 0.035ohm |
| Gate Source Threshold Voltage Max | 2.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2807205/)

## **STL7N6LF3** 

Automotive-grade N-channel 60 V, 35 mΩ typ., 6.5 A STripFET™ F3 Power MOSFET in a PowerFLAT™ 5x6 package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS**|**RDS(on) max.**|ID|
|---|---|---|---|
|STL7N6LF3|60 V|43 mΩ|6.5 A|



- AEC-Q101 qualified 

- Logic level VGS(th) 

- 175 °C maximum junction temperature 

- 100% avalanche rated 

- Wettable flank package 

## **Applications** 

- Switching applications 

**Figure 1: Internal schematic diagram** 

## **Description** 

This device is an N-channel Power MOSFET developed using STripFET™ F3 technology. It is designed to minimize on-resistance and gate charge to provide superior switching performance. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STL7N6LF3|7N6LF3|PowerFLAT™ 5x6|Tape and reel|



This is information on a product in full production. 

_www.st.com_ 

February 2017 

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|**Contents**<br>**STL7N6LF3**|**Contents**<br>**STL7N6LF3**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>PowerFLAT 5x6 WF type R package information ............................. 9|
||4.2<br>Packing information ......................................................................... 12|
|**5**|**Revision history ............................................................................ 14**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|60|V|
|VGS|Gate-source voltage|±20|V|
|ID_(1)_|Drain current (continuous) at TC= 25 °C|20|A|
|ID_(1)_|Drain current (continuous) at Tc= 100 °C|16|A|
|ID_(2)_|Drain current (continuous) at Tpcb= 25 °C|6.5|A|
|ID_(2)_|Drain current (continuous) at Tpcb= 100 °C|4.6|A|
|IDM_(3),(2)_|Drain current (pulsed)|26|A|
|PTOT_(1)_|Total dissipation at TC= 25 °C|52|W|
|PTOT_(2)_|Total dissipation at Tpcb= 25°C|4.3|W|
|IAV|Not-repetitive avalanche current|6.5|A|
|EAS_(4)_|Singlepulse avalanche energy|190|mJ|
|Tj|Operating junction temperature range|-55 to 175|°C|
|Tstg|Storage temperature range|||



## **Notes:** 

(1) This value is rated according to Rthj-case 

(2) This value is rated according to Rthj-pcb 

(3) Pulse width limited by safe operating area. 

(4) Starting TJ= 25 °C, ID= 8 A, VDD= 25 V. 

**Table 3: Thermal resitance** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|2.9|°C/W|
|Rthj-pcb_(1)_|Thermal resistancejunction-pcb|35|°C/W|



## **Notes:** 

(1)When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

**Table 4: On/Off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 250 μA|60|||V|
|IDSS|Zero gate voltage<br>drain current|VGS= 0 V, VDS= 60 V|||1|µA|
|IGSS|Gate-body leakage<br>current|VDS= 0 V, VGS= ±20 V|||±100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 μA|1||2.5|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID= 3 A||35|43|mΩ|
|||VGS= 5 V, ID= 3 A||48|60|mΩ|



## **Table 5: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 25 V, f = 1 MHz,<br>VGS= 0 V|-|432|-|pF|
|Coss|Output capacitance||-|93|-||
|Crss|Reverse transfer capacitance||-|10.5|-||
|Qg|Totalgate charge|VDD= 30 V, ID= 6.5 A,<br>VGS= 0 to 10 V<br>(see_Figure 13: "Test circuit_<br>_for gate charge behavior"_)|-|8.7|-|nC|
|Qgs|Gate-source charge||-|1.9|-||
|Qgd|Gate-drain charge||-|1.9|-||
|RG|Intrinsic gate resistance|f =1 MHz, ID=0 A|-|6.3|-|Ω|



## **Table 6: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 30 V, ID= 3 A,<br>RG= 4.7 Ω, VGS= 10 V<br>(see_Figure 12: "Test circuit_<br>_for resistive load switching_<br>_times"_and_Figure 17:_<br>_"Switching time waveform"_)|-|6.7|-|ns|
|tr|Rise time||-|10.4|-||
|td(off)|Turn-off delay time||-|32.4|-||
|tf|Fall time||-|5.4|-||



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**Electrical characteristics** 

**Table 7: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||6.5|A|
|ISDM_(1)_|Source-drain current (pulsed)||-||26|A|
|VSD_(2)_|Forward on voltage|IDS= 6.5 A, VGS= 0 V|-||1.3|V|
|trr|Reverse recoverytime|ISD= 6.5 A, di/dt = 100 A/µs<br>VDD= 48 V, Tj= 150 °C<br>(see_Figure 14: "Test circuit_<br>_for inductive load switching_<br>_and diode recovery times"_)|-|24||ns|
|Qrr|Reverse recovery charge||-|23.3||nC|
|IRRM|Reverse recovery current||-|1.9||A|



## **Notes:** 

(1)Pulse width limited by safe operating area 

(2)Pulsed: pulse duration = 300 μs, duty cycle 1.5 % 

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## **Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**==> picture [128 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


**==> picture [5 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
d<br>**----- End of picture text -----**<br>


**Figure 4: Output characteristics** 

**Figure 5: Transfer characteristics** 

**Figure 6: Normalized V(BR)DSS vs temperature** 

**==> picture [186 x 30] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 7: Static drain-source on-resistance<br>ROS(on)<br>(mΩ)<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

**Figure 8: Gate charge vs gate-source voltage** 

**Figure 10: Normalized gate threshold voltage vs temperature** 

**Figure 9: Capacitance variation** 

**Figure 11: Normalized on-resistance vs temperature** 

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 375] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 12: Test circuit for resistive load  Figure 13: Test circuit for gate charge<br>switching times  behavior<br>Figure 14: Test circuit for inductive load  Figure 15: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>**----- End of picture text -----**<br>


**==> picture [403 x 170] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 16: Unclamped inductive waveform  Figure 17: Switching time waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 PowerFLAT 5x6 WF type R package information** 

**Figure 18: PowerFLAT™ 5x6 WF type R package outline** 

**==> picture [406 x 498] intentionally omitted <==**

**----- Start of picture text -----**<br>
A0Y5_8231817_R_WF_Rev_14<br>**----- End of picture text -----**<br>


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**Package information** 

|**formation**<br>**STL7N6LF3**|**formation**<br>**STL7N6LF3**|**formation**<br>**STL7N6LF3**|**formation**<br>**STL7N6LF3**|
|---|---|---|---|
|**Table 8: PowerFLAT™ 5x6 WF type R mechanical data**||||
|**Dim.**||**mm**||
||**Min.**|**Typ.**|**Max.**|
|A|0.80||1.00|
|A1|0.02||0.05|
|A2||0.25||
|b|0.30||0.50|
|C|5.80|6.00|6.10|
|D|5.00|5.20|5.40|
|D2|4.15||4.45|
|D3|4.05|4.20|4.35|
|D4|4.80|5.00|5.10|
|D5|0.25|0.4|0.55|
|D6|0.15|0.3|0.45|
|e||1.27||
|E|6.20|6.40|6.60|
|E2|3.50||3.70|
|E3|2.35||2.55|
|E4|0.40||0.60|
|E5|0.08||0.28|
|E6|0.20|0.325|0.45|
|E7|0.85|1.00|1.15|
|E9|4.00|4.20|4.40|
|E10|3.55|3.70|3.85|
|K|1.275||1.575|
|L|0.725|0.825|0.925|
|L1|0.175|0.275|0.375|
|ϴ|0°||12°|



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**Package information** 

**Figure 19: PowerFLAT™ 5x6 recommended footprint (dimensions are in mm)** 

**==> picture [406 x 332] intentionally omitted <==**

**----- Start of picture text -----**<br>
8231817_FOOTPRINT_rev14<br>**----- End of picture text -----**<br>


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**Package information** 

## **4.2 Packing information** 

**Figure 20: PowerFLAT™ 5x6 WF tape (dimensions are in mm)** 

**Figure 21: PowerFLAT™ 5x6 package orientation in carrier tape** 

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**Package information** 

**Figure 22: PowerFLAT™ 5x6 reel (dimensions are in mm)** 

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**Revision history** 

## **5 Revision history** 

**Table 9: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|14-Oct-2014|1|First release.|
|10-Feb-2015|2|Updated_Table 4: On/off states, Table 5: Dynamic, Table 6: Switching_<br>_times, Table 7: Source drain diode_and_Section 4: Package mechanical_<br>_data._|
|26-May-2015|3|Updated title and features.<br>Document status from preliminary to production data.|
|13-Feb-2017|4|Modified features on cover page.<br>Modified_Table 2: "Absolute maximum ratings"_and_Table 5: "Dynamic"_.<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2017 STMicroelectronics – All rights reserved 

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- [Supplier page](https://es.farnell.com/stmicroelectronics/stl7n6lf3/mosfet-aec-q101-n-ch-60v-powerlat/dp/2807205)
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