# Power MOSFET, N Channel, 60 V, 7 A, 0.025 ohm, PowerFLAT, Surface Mount
**URL**: https://novapart.co/products/STL7N6F7/power-mosfet-n-channel-60-v-7-a-0025-ohm-powerflat
**SKU**: STL7N6F7
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.2200
**Stock**: 1000+
**Lead Time**: 127 days (indicative)
## Specifications
| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 6Pins |
| Channel Type | N Channel |
| Product Range | STripFET F7 |
| Qualification | - |
| Power Dissipation | 2.4W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | PowerFLAT |
| Drain Source Voltage Vds | 60V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 7A |
| Drain Source On State Resistance | 0.025ohm |
| Gate Source Threshold Voltage Max | 4V |
## Datasheet
📄 [Download PDF](https://novapart.co/datasheet/farnell:3367063/)
## **STL7N6F7**
N-channel 60 V, 21 mΩ typ., 7 A STripFET™ F7 Power MOSFET in a PowerFLAT™ 2x2 package
Datasheet - production data
## **Features**
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**----- Start of picture text -----**
1
2 Order code VDS RDS(on) max ID
3
STL7N6F7 60 V 25 mΩ 7 A
6
1 5 Among the lowest RDS(on) on the market
eo 2
3 4 Excellent FoM (figure of merit)
Low Crss/Ciss ratio for EMI immunity
High avalanche ruggedness
PowerFLAT™ 2x2
Applications
Switching applications
Figure 1: Internal schematic diagram
Description
1(D) 2(D) 3(G)
This N-channel Power MOSFET utilizes
STripFET™ F7 technology with an enhanced
trench gate structure that results in very low on-
state resistance, while also reducing internal
capacitance and gate charge for faster and more
D S efficient switching.
6(D) 5(D) 4(S)
Bottom view
AM11269v1
Table 1: Device summary
Order code Marking Package Packing
——_———— STL7N6F7 ST7N PowerFLAT™ 2x2 Tape and reel
**----- End of picture text -----**
This is information on a product in full production.
April 2017
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_www.st.com_
|**Contents**
**STL7N6F7**|**Contents**
**STL7N6F7**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1
Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1
PowerFLAT 2x2 package information ............................................. 10|
|**5**|**Revision history ............................................................................ 12**|
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**Electrical ratings**
## **1 Electrical ratings**
**Table 2: Absolute maximum ratings**
|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|60|V|
|VGS|Gate-source voltage|± 20|V|
|ID|Drain current (continuous) at Tpcb= 25 °C|7|A|
|ID|Drain current (continuous) at Tpcb= 100 °C|4.5|A|
|IDM_(1)_|Drain current (pulsed)|28|A|
|PTOT|Total dissipation at Tpcb= 25 °C|2.4|W|
|TJ|Operating junction temperature range|-55 to 150|°C|
|Tstg|Storage temperature range|||
## **Notes:**
- (1)Pulse width limited by safe operating area.
**Table 3: Thermal data**
|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-pcb_(1)_|Thermal resistancejunction-pcb|52|°C/W|
## **Notes:**
(1)When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s.
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**Electrical characteristics**
## **2 Electrical characteristics**
(TC = 25 °C unless otherwise specified)
**Table 4: On /off states**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown
voltage|ID= 1 mA, VGS= 0 V|60|||V|
|IDSS|Zero gate voltage
drain current|VGS= 0 V , VDS= 60 V|||1|µA|
|IGSS|Gate-body leakage
current|VGS= 20 V, VDS= 0 V|||100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 μA|2||4|V|
|RDS(on)|Static drain-source
on-resistance|VGS= 10 V, ID= 3.5A||21|25|mΩ|
## **Table 5: Dynamic**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 30 V, f = 1 MHz,
VGS= 0 V|-|420|-|pF|
|Coss|Output capacitance||-|215|-|pF|
|Crss|Reverse transfer
capacitance||-|16|-|pF|
|Qg|Totalgate charge|VDD= 30 V, ID= 7 A
VGS= 0 to 10 V
(see_Figure 14: "Test circuit_
_for gate charge behavior"_)|-|8|-|nC|
|Qgs|Gate-source charge||-|2.3|-|nC|
|Qgd|Gate-drain charge||-|2.1|-|nC|
## **Table 6: Switching times**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 30 V, ID= 3.5A,
RG= 4.7 Ω, VGS= 10 V
(see_Figure 13: "Test circuit_
_for resistive load switching_
_times"_and_Figure 18:_
_"Switching time waveform"_)|-|7.85|-|ns|
|tr|Rise time||-|3.25|-|ns|
|td(off)|Turn-off delaytime||-|12.1|-|ns|
|tf|Fall time||-|3.95|-|ns|
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**Electrical characteristics**
**Table 7: Source-drain diode**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VSD_(1)_|Forward on voltage|ISD= 7 A, VGS= 0 V|-||1.2|V|
|trr|Reverse recovery time|ID= 7 A, di/dt = 100 A/µs
VDD= 48 V
(see_Figure 15: "Test circuit_
_for inductive load switching_
_and diode recovery times"_|-|17.1||ns|
|Qrr|Reverse recoverycharge||-|6.67||nC|
|IRRM|Reverse recovery current||-|0.8||A|
## **Notes:**
(1)Pulsed: pulse duration = 300 µs, duty cycle 1.5%
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## **Electrical characteristics**
## **2.1 Electrical characteristics (curves)**
**Figure 2: Safe operating area**
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Figure 3: Thermal impedance
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**Figure 4: Output characteristics**
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**Figure 5: Transfer characteristics**
**==> picture [179 x 164] intentionally omitted <==**
**Figure 6: Gate charge vs gate-source voltage**
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**Figure 7: Static drain-source on-resistance**
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**Electrical characteristics**
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**----- Start of picture text -----**
Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs
temperature
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**Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature**
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**Figure 12: Source-drain diode forward characteristics**
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**Test circuits**
## **3 Test circuits**
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**----- Start of picture text -----**
Figure 13: Test circuit for resistive load Figure 14: Test circuit for gate charge
switching times behavior
Figure 15: Test circuit for inductive load Figure 16: Unclamped inductive load test
switching and diode recovery times circuit
Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform
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**Package information**
## **4 Package information**
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark.
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**Package information**
- **4.1 PowerFLAT 2x2 package information**
**Figure 19: PowerFLAT™ 2x2 package outline**
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8368575_REV_4
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**Package information**
## **Table 8: PowerFLAT™ 2x2 mechanical data**
|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|0.70|0.75|0.80|
|A1|0.00|0.02|0.05|
|A3||0.20||
|b|0.25|0.30|0.35|
|D|1.90|2.00|2.10|
|E|1.90|2.00|2.10|
|D2|0.90|1.00|1.10|
|E2|0.80|0.90|1.00|
|e|0.55|0.65|0.75|
|K|0.15|0.25|0.35|
|K1|0.20|0.30|0.40|
|K2|0.25|0.35|0.45|
|L|0.20|0.25|0.30|
|L1|0.65|0.75|0.85|
**Figure 20: PowerFLAT™ 2x2 recommended footprint (dimensions are in mm)**
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Footprint
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**Revision history**
## **5 Revision history**
**Table 9: Document revision history**
|**Date**|**Revision**|**Changes**|
|---|---|---|
|27-Aug-2015|1|First release.|
|22-Oct-2015|2|Updated title and features in cover page Updated Table 4: "On /off
states", Table 5: "Dynamic" and Table 6: "Switching times".
Added Section 4.1: "Electrical characteristics (curves)"|
|03-Apr-2017|3|Modified title and features table on cover page
Modified_Table 4: "On /off states"_
Modified_Figure 4: "Output characteristics"_,_Figure 5: "Transfer_
_characteristics"_,_Figure 7: "Static drain-source on-resistance"_and
_Figure 12: "Source-drain diode forward characteristics"_
Minor text changes.|
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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY**
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
- © 2017 STMicroelectronics – All rights reserved
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## Links
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- [Supplier page](https://es.farnell.com/stmicroelectronics/stl7n6f7/mosfet-n-ch-60v-7a-150deg-c-2/dp/3367063)
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