# Dual MOSFET, N Channel, 60 V, 60 V, 20 A, 20 A, 0.043 ohm

![Product image](https://novapart.co/image/farnell:3132772/)

**URL**: https://novapart.co/products/STL7DN6LF3/dual-mosfet-n-channel-60-v-20-a-0043-ohm
**SKU**: STL7DN6LF3
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Dual MOSFETs
**Price**: €0.7970
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:Dual N Channel; Continuous Drain Current Id:20A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.035ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:2.5

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | STripFET F3 Series |
| Qualification | AEC-Q101 |
| Transistor Case Style | PowerFLAT |
| Operating Temperature Max | 175°C |
| Power Dissipation N Channel | 52W |
| Power Dissipation P Channel | 52W |
| Drain Source Voltage Vds N Channel | 60V |
| Drain Source Voltage Vds P Channel | 60V |
| Continuous Drain Current Id N Channel | 20A |
| Continuous Drain Current Id P Channel | 20A |
| Drain Source On State Resistance N Channel | 0.043ohm |
| Drain Source On State Resistance P Channel | - |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3132772/)

## **STL7DN6LF3** 

Automotive-grade dual N-channel 60 V, 35 mΩ typ., 6.5 A STri FET™ F3 Power MOSFET in PowerFLAT™ 5x6 double island p 

**Datasheet** - **production data** 

## **Features** 

|**Order code**|**VDS**|RDS(on)<br>max|ID|
|---|---|---|---|
|STL7DN6LF3|60 V|43 mΩ|6.5 A|



**==> picture [156 x 35] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>2<br>3<br>4<br>PowerFLAT™ 5x6 double island<br>**----- End of picture text -----**<br>


- Designed for automotive application and AEC-Q101 qualified 

- Logic level VGS(th) 

- 175 °C junction temperature 

- 100% avalanche rated 

- Wettable flank package 

## **Figure 1. Internal schematic diagram** 

## **Applications** 

- Switching applications 

## **Description** 

This device is a dual N-channel Power MOSFET developed using STripFET™ F3 technology. It is designed to minimize on-resistance and gate charge to provide superior switching performance. 

**Top view** 

**Table 1. Device summary** 

**Order code Marking Package Packaging** PowerFLAT™ 5x6 STL7DN6LF3 7DN6LF3 Tape and reel double island[(1)] ~~>~~ 1. For wettable flank option, please contact ST sale offices. ~~—~~ 

_www.st.com_ 

February 2015 

DocID023010 Rev 4 

1/18 

This is information on a product in full production. 

**Contents** 

**STL7DN6LF3** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Electrical characteristics (curves)       . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Test circuits     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8**|
|**4**|**Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9**|
|**5**|**Packaging information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15**|
|**6**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|60|V|
|VGS|Gate-source voltage|±20|V|
|ID<br>(1),(2)|Drain current (continuous) at TC= 25 °C|20|A|
|ID<br>(1)|Drain current (continuous) at TC= 100 °C|16|A|
|ID<br>(4)|Drain current (continuous) at Tpcb= 25 °C|6.5|A|
|ID<br>(4)|Drain current (continuous) at Tpcb=100 °C|4.6|A|
|IDM<br>(3),(4)|Drain current (pulsed)|26|A|
|PTOT|Total dissipation at TC= 25°C|52|W|
|PTOT<br>(4)|Total dissipation at Tpcb= 25°C|4.3|W|
|IAV|Not-repetitive avalanche current|6.5|A|
|EAS (5)|Single pulse avalanche energy|190|mJ|
|TJ<br>Tstg|Operating junction temperature<br>Storage temperature|-55 to 175|°C|



1. Specified by design. Not subject to production test. 

2. Current is limited by bonding, with an RthJC = 2.9 °C/W the chip is able to carry 22 A at 25 °C. 

3. Pulse width limited by safe operating area 

4. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec 

5. Starting TJ= 25 °C, ID= 8 A, VDD= 25 V 

**Table 3. Thermal resistance** 

||**Table 3. Thermal resistance**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|Rthj-case|Thermal resistance junction-case|2.9|°C/W|
|Rthj-pcb<br>(1)|Thermal resistance junction-pcb|35|°C/W|



1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TCASE = 25 °C unless otherwise specified) 

**Table 4. On/off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage (VGS= 0)|ID= 250 µA|60|||V|
|IDSS|Zero gate voltage drain<br>current (VGS= 0)|VDS= 60 V|||1|µA|
|IGSS|Gate body leakage current<br>(VDS= 0)|VGS= ±20 V|||±100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 µA|1||2.5|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 3 A<br>VGS= 5 V, ID= 3 A||35<br>48|43<br>60|mΩ<br>mΩ|



**Table 5. Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS=25 V, f=1 MHz,<br>VGS=0|-|432|-|pF|
|Coss|Output capacitance||-|93|-|pF|
|Crss|Reverse transfer<br>capacitance||-|10.5|-|pF|
|Qg|Total gate charge|VDD=30 V, ID= 6.5 A<br>VGS=10 V,_Figure 13_|-|8.7|-|nC|
|Qgs|Gate-source charge||-|1.9|-|nC|
|Qgd|Gate-drain charge||-|1.9|-|nC|
|RG|Intrinsic gate resistance|f=1 MHz open drain|-|6.3|-|Ω|



**Table 6. Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD=30 V, ID= 3 A,<br>RG=4.7Ω,VGS=10 V<br>_Figure 12_|-<br>-<br>-<br>-|6.7|-|ns|
|tr|Rise time|||10.4|-|ns|
|td(off)|Turn-off delay time|||32.4|-|ns|
|tf|Fall time|||5.4|-|ns|



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**Electrical characteristics** 

**Table 7. Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min**|**Typ.**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||6.5|A|
|ISDM<br>(1)|Source-drain current (pulsed)||-||26|A|
|VSD<br>(2)|Forward on voltage|ISD= 6.5 A, VGS=0|-||1.3|V|
|trr|Reverse recovery time|ISD= 6.5 A,<br>di/dt = 100 A/µs,<br>VDD=48 V, Tj=150 °C|-|24|-|ns|
|Qrr|Reverse recovery charge||-|23.3|-|nC|
|IRRM|Reverse recovery current||-|1.94|-|A|



1. Pulse width limited by safe operating area 

2. Pulsed: pulse duration= 300 µs, duty cycle 1.5% 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2. Safe operating area** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
ID AM13023v1<br>(A)<br>Tj=175°C<br>Tc=25°C<br>Single pulse<br>10<br>1 10ms<br>100ms<br>1s<br>0.1<br>0.1 1 10 VDS(V)<br>DS(on)<br>Operation in this area is<br>Limited by max R<br>**----- End of picture text -----**<br>


**Figure 4. Output characteristics** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM13024v1<br>ID<br>(A)<br>VGS=6, 7, 8, 9, 10V<br>25<br>5V<br>20<br>4V<br>15<br>10<br>5<br>0<br>0 1 2 3 4 VDS(V)<br>**----- End of picture text -----**<br>


## **Figure 6. Normalized V(BR)DSS vs temperature** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
V(BR)DSS AM13010v1<br>(norm)<br>ID=250µA<br>1.10<br>1.06<br>1.02<br>0.98<br>0.94<br>0.90<br>-75 -25 25 75 125 TJ(°C)<br>**----- End of picture text -----**<br>


## **Figure 3. Thermal impedance** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
Zth_AM13007v1<br>K<br>δ=0.5<br>0.2<br>0.1<br>10-1 0.05<br>0.02<br>0.01<br>10-2<br>Single pulse<br>10-3<br>10-4 10-3 10-2 10-1 100 101 tp [(s)]<br>**----- End of picture text -----**<br>


## **Figure 5. Transfer characteristics** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM13025v1<br>ID<br>(A)<br>VDS=5V<br>25<br>20<br>15<br>10<br>5<br>0<br>0 1 2 3 4 VGS(V)<br>**----- End of picture text -----**<br>


## **Figure 7. Static drain-source on-resistance** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM13026v1<br>RDS(on)<br>(mΩ) VGS=10V<br>35.4<br>35.2<br>35.0<br>34.8<br>34.6<br>34.4<br>2 3 4 5 ID(A)<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

## **Figure 8. Gate charge vs gate-source voltage** 

**Figure 9. Capacitance variations** 

**==> picture [462 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
VGS AM13027v1 C AM13028v1<br>(V) (pF)<br>VDD=30V<br>10 ID=6.5A Ciss<br>8<br>100<br>6<br>Coss<br>4<br>2<br>Crss<br>0 10<br>0 2 4 6 8 10 Qg(nC) 0 10 20 30 40 50 VDS(V)<br>**----- End of picture text -----**<br>


**Figure 10. Normalized gate threshold voltage vs temperature** 

**Figure 11. Normalized on-resistance vs temperature** 

**==> picture [462 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
VGS(th) AM13014v1 RDS(on) AM13015v1<br>(norm) ID=250µA (norm)<br>VGS=10V<br>2.0<br>1.2<br>1.6<br>1.0<br>1.2<br>0.8<br>0.8<br>0.6<br>0.4<br>0.4 0<br>-75 -25 25 75 125 TJ(°C) -75 -25 25 75 125 TJ(°C)<br>**----- End of picture text -----**<br>


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**Test circuits** 

## **3 Test circuits** 

**Figure 12. Switching times test circuit for resistive load** 

**Figure 13. Gate charge test circuit** 

**==> picture [462 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>12V 47kΩ<br>1kΩ<br>100nF<br>RL 2200 3.3<br>μF μF<br>VDD IG=CONST<br>VD Vi=20V=VGMAX 100Ω D.U.T.<br>VGS<br>2200<br>RG D.U.T. μF 2.7kΩ VG<br>PW<br>47kΩ<br>1kΩ<br>PW<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


**Figure 14. Test circuit for inductive load Figure 15. Unclamped inductive load test circuit switching and diode recovery times** 

**==> picture [462 x 346] intentionally omitted <==**

**----- Start of picture text -----**<br>
L<br>A A A<br>D<br>FAST L=100μH VD<br>G D.U.T. DIODE 2200 3.3<br>S B 3.3 1000 μF μF VDD<br>25 Ω B B D μF μF VDD ID<br>G<br>RG S<br>Vi D.U.T.<br>Pw<br>AM01470v1 AM01471v1<br>Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform<br>V(BR)DSS ton toff<br>VD tdon tr tdoff tf<br>90% 90%<br>IDM<br>10%<br>ID 0 10% VDS<br>VDD VDD 90%<br>VGS<br>AM01472v1 0 10% AM01473v1<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 

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**Package information** 

## **Figure 18. PowerFLAT 5x6 double island type R outline** 

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**Package information** 

**Table 8. PowerFLAT 5x6 double island type R mechanical data** 

|**Ref.**|**Dimensions (mm)**|**Dimensions (mm)**|**Dimensions (mm)**|
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|0.80||1.00|
|A1|0.02||0.05|
|A2||0.25||
|b|0.30||0.50|
|D|5.00|5.20|5.40|
|D2|1.68||1.88|
|E|5.95|6.15|6.35|
|E2|3.50||3.70|
|E4|0.55||0.75|
|E5|0.08||0.28|
|E6|2.35||2.55|
|E7|0.40||0.60|
|e||1.27||
|L|0.60||0.80|
|K|1.275||1.575|



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**Package information** 

## **Figure 19. PowerFLAT 5x6 double island WF type R outline** 

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**STL7DN6LF3** 

**Package information** 

**Table 9. PowerFLAT 5x6 double island WF type R mechanical data** 

|**Ref.**|**Dimensions (mm)**|**Dimensions (mm)**|**Dimensions (mm)**|
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|0.80||1.00|
|A1|0.02||0.05|
|A2||0.25||
|b|0.30||0.50|
|D|5.00|5.20|5.40|
|D2|1.68||1.88|
|E|6.20|6.40|6.60|
|E2|3.50||3.70|
|E4|0.55||0.75|
|E5|0.08||0.28|
|E6|2.35||2.55|
|E7|0.40||0.60|
|e||1.27||
|L|0.70||0.90|
|L1||0.275||
|K|1.275||1.575|



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**Package information** 

**Figure 20. PowerFLAT 5x6 double island recommended footprint (dimensions are in mm)** 

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**Packaging information** 

## **5 Packaging information** 

## **Figure 21. PowerFLAT™ 5x6 tape[(a)]** 

**==> picture [405 x 257] intentionally omitted <==**

**----- Start of picture text -----**<br>
P 2 P 0<br>(0.30 T ±0.05) Do 2.0±0.1 (I) 4.0±0.1 (II) E1<br>Ø1.55±0.05 Y 1.75±0.1<br>D1<br>Ø1.5 MIN.<br>CL<br>Y<br>P1(8.00±0.1) Ao(6.30±0.1)<br>Ko (1.20±0.1)<br>SECTION Y-Y<br>(I) Measured from centerline of sprocket holeto centerline of pocket. Base and bulk quantity 3000 pcs<br>(II) Cumulative tolerance of 10 sprocket<br>holes is ± 0.20 .<br>(III) Measured from centerline of sprocket<br>hole to centerline of pocket.<br>8234350_Tape_rev_C<br>REF.R0.50<br>REF 0.20<br>))((IIIF5.50±0.1 )(W12.00±0.3<br>5.30±0.1)(Bo<br>**----- End of picture text -----**<br>


## **Figure 22. PowerFLAT 5x6 WF tape[(a)]** 

**==> picture [405 x 256] intentionally omitted <==**

**----- Start of picture text -----**<br>
T0.30 0.05 Do1.50 +0.10.0 2.0P2 0.05(I) Po4.0 0.1(II) 1.75E1 0.1<br>Y<br>D1<br>1.50MIN<br>R0.30<br>MAX<br>Y<br>Ko (1.20±0.1) P1(8.00±0.1) Ao(6.70±0.1)<br>SECTION Y-Y<br>(I) Measured from centreline of sprocket hole<br>to centreline of pocket.<br>(II) Cumulative tolerance of 10 sprocket<br>holes is ± 0.20 . Base and bulk quantity 3000 pcs<br>(III) Measured from centreline of sprocket<br>hole to centreline of pocket.<br>8234350_TapeWF_rev_C<br>)<br>F(5.50±0.0.05)(III) (W12.00±0.1<br>Bo (5.35±0.05)<br>**----- End of picture text -----**<br>


a. All dimensions are in millimeters. 

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**Packaging information** 

## **Figure 23. PowerFLAT™ 5x6 package orientation in carrier tape** 

**==> picture [356 x 141] intentionally omitted <==**

**----- Start of picture text -----**<br>
Pin 1<br>identification<br>**----- End of picture text -----**<br>


## **Figure 24. PowerFLAT™ 5x6 reel** 

**==> picture [405 x 256] intentionally omitted <==**

**----- Start of picture text -----**<br>
R0.60<br>W3<br>PART NO. 11.9/15.4<br>1 .90<br>2.50<br>W2<br>18.4 (max)<br>R25.00<br>   ØN    A<br>4.00 178(±2.0) 330 (+0/-4.0)<br>2.50<br>ESD LOGO<br>W1<br>12.4 (+2/-0)<br>ØA<br>R1.10<br>Ø21.2<br>All dimensions are in millimeters<br>13.00<br>CORE DETAIL<br>8234350_Reel_rev_C<br>128<br>77<br>ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES<br>2.20<br>06PS<br>**----- End of picture text -----**<br>


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**Revision history** 

## **6 Revision history** 

**Table 10. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|28-Mar-2012|1|First release.|
|19-Jun-2012|2|_Section 2.1: Electrical characteristics (curves)_has been added.<br>Updated_Section 4: Package information_and tile on the coverpage.|
|26-Jun-2012|3|Document status promoted from preliminary to production data.|
|23-Feb-2015|4|Updated title, features and description in cover page.<br>Updated_Table 5: Dynamic_,_Table 6: Switching times_and<br>_Section 2.1: Electrical characteristics (curves)_.<br>Updated_Section 4: Package information_.<br>Added_Section 5: Packaging information_.<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2015 STMicroelectronics – All rights reserved 

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## Links

- [View this product on Novapart](https://novapart.co/products/STL7DN6LF3/dual-mosfet-n-channel-60-v-20-a-0043-ohm)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/stmicroelectronics/stl7dn6lf3/mosfet-dual-n-ch-60v-20a-52w/dp/3132772)
---

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