# Power MOSFET, N Channel, 20 V, 6 A, 0.025 ohm, PowerFLAT, Surface Mount

![Product image](https://novapart.co/image/farnell:3132755/)

**URL**: https://novapart.co/products/STL6N2VH5/power-mosfet-n-channel-20-v-6-a-0025-ohm-powerflat
**SKU**: STL6N2VH5
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.1580
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:6A; Drain Source Voltage Vds:20V; On Resistance Rds(on):0.025ohm; Rds(on) Test Voltage Vgs:4.5V; Threshold Voltage Vgs:700

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 6Pins |
| Channel Type | N Channel |
| Product Range | STripFET V |
| Qualification | - |
| Power Dissipation | 2.4W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 4.5V |
| Transistor Case Style | PowerFLAT |
| Drain Source Voltage Vds | 20V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 6A |
| Drain Source On State Resistance | 0.025ohm |
| Gate Source Threshold Voltage Max | 700mV |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3132755/)

## **STL6N2VH5** 

N-channel 20 V, 0.025 Ω typ., 6 A STripFET™ V Power MOSFET in a PowerFLAT™ 2x2 package **Datasheet — production data** 

**Features** 

1 **Order code VDS RDS(on) max. ID PTOT** 2 0.03 Ω (VGS=4.5 V) 3 STL6N2VH5 20 V 6 A 2.4 W 0.04 Ω (VGS=2.5 V) 1 6 • Very low switching gate charge 5 os 2 4 ~~TES~~ • Very low thermal resistance 3 • Conduction losses reduced **PowerFLAT™ 2x2** 

- Switching losses reduced 

- 2.5 V gate drive 

- Very low threshold device 

## **Figure 1.  Internal schematic diagram** 

**==> picture [157 x 161] intentionally omitted <==**

**----- Start of picture text -----**<br>
1(D) 2(D) 3(G)<br>D S<br>6(D) 5(D) 4(S)<br>AM11269v1<br>**----- End of picture text -----**<br>


## **Applications** 

- Switching applications 

## **Description** 

This device is an N-channel Power MOSFET developed using STMicroelectronics’ STripFET™V technology. The device has been optimized to achieve very low on-state resistance, contributing to a FOM that is among the best in its class. 

**Table 1. Device summary** 

**Order code Marking Packages Packaging** STL6N2VH5 STD1 PowerFLAT™ 2x2 Tape and reel ~~—$$~~ 

_www.st.com_ 

March 2014 

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This is information on a product in full production. 

**Contents** 

**STL6N2VH5** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Electrical characteristics (curves)       . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Test circuits     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8**|
|**4**|**Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9**|
|**5**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|20|V|
|VGS|Gate-source voltage|± 8|V|
|ID<br>(1)|Drain current (continuous) at Tpcb= 25 °C|6|A|
|ID<br>(1)|Drain current (continuous) at Tpcb= 100 °C|3.75|A|
|IDM<br>(1),(2)|Drain current (pulsed)|24|A|
|PTOT<br>(1)|Total dissipation at Tpcb= 25 °C|2.4|W|
|TJ|Operating junction temperature|-55 to 150|°C|
|Tstg|Storage temperature||°C|



1. The value is rated according Rthj-pcb 

2. Pulse width limited by safe operating area. 

**Table 3. Thermal resistance** 

||**Table 3. Thermal resistance**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|Rthj-pcb<br>(1)|Thermal resistance junction-pcb|52|°C/W|



1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec 

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**STL6N2VH5** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(TCASE = 25 °C unless otherwise specified) 

**Table 4. On/off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|ID= 250 μA, VGS= 0|20|||V|
|IDSS|Zero gate voltage drain<br>current (VGS= 0)|VDS= 20 V,|||1|μA|
|||VDS= 20 V, TJ= 125 °C|||10|μA|
|IGSS|Gate body leakage current<br>(VDS= 0)|VGS= ±8 V|||±100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 μA|0.7|||V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 4.5 V, ID= 3 A||0.025|0.03|Ω|
|||VGS=2.5 V, ID= 3 A||0.031|0.04|Ω|



**Table 5. Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 16 V, f=1 MHz,<br>VGS=0|-|367|-|pF|
|Coss|Output capacitance||-|92|-|pF|
|Crss|Reverse transfer<br>capacitance||-|16|-|pF|
|Qg|Total gate charge|VDD= 10 V, ID= 2 A<br>VGS= 4.5 V<br>_(see Figure 14)_|-|4.6|-|nC|
|Qgs|Gate-source charge||-|0.9|-|nC|
|Qgd|Gate-drain charge||-|1|-|nC|



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**Electrical characteristics** 

**Table 6. Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 10 V, ID= 2 A,<br>RG= 4.7Ω,VGS= 4.5 V<br>_(see Figure 13)_|-|4.8|-|ns|
|tr|Rise time||-|14.4|-|ns|
|td(off)|Turn-off delay time||-|17|-|ns|
|tf|Fall time||-|4|-|ns|



**Table 7. Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min**|**Typ.**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||6|A|
|ISDM<br>(1)|Source-drain current (pulsed)||-||24|A|
|VSD<br>(2)|Forward on voltage|ISD= 2 A, VGS= 0|-||1.1|V|
|trr|Reverse recovery time|ISD= 2 A,<br>di/dt = 100 A/μs,<br>VDD= 16 V, TJ= 150 °C|-|10||ns|
|Qrr|Reverse recovery charge||-|24||nC|
|IRRM|Reverse recovery current||-|4.8||A|



1. Pulse width limited by safe operating area 

2. Pulsed: pulse duration=300μs, duty cycle 1.5% 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

## **Figure 2. Safe operating area** 

## **Figure 3. Thermal impedance** 

**==> picture [462 x 374] intentionally omitted <==**

**----- Start of picture text -----**<br>
ID AM18126v1 K AM18127v1<br>(A) δ=0.5<br>0.2<br>100µs<br>0.1<br>10 10 [-1]<br>0.05<br>1ms<br>0.02<br>0.01 pcb<br>1 10 [-2]<br>10ms<br>Single pulse<br>Tj=150°C<br>Tc=25 ° C<br>Single pulse<br>0.1 10 [-3]<br>0.1 1 10 VDS(V) 10 [-5] 10-4 10 [-3] 10 [-2] 10 [-1] 10 [0] tp(s)<br>Figure 4. Output characteristics Figure 5. Transfer characteristics<br>AM18128v1 AM18129v1<br>ID(A) ID<br>VGS=2.5, 3.5, 4.5, 5.5, 6.5 V (A) VDS=4V<br>20 20<br>1.5V<br>16 16<br>12 12<br>8 8<br>4 4<br>0.5V<br>0 0<br>0 1 2 3 4 VDS(V) 0 0.2 0.4 0.6 0.8 1 1.2 VGS(V)<br>DS(on)<br>Operation in this area is<br>Limited by max R<br>**----- End of picture text -----**<br>


## **Figure 6. Gate charge vs gate-source voltage** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
VGS AM18130v1<br>(V) VDD=10V<br>I D =2A<br>6<br>4<br>2<br>0<br>0 2 4 6 Qg(nC)<br>**----- End of picture text -----**<br>


**Figure 7. Static drain-source on-resistance** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM18132v1<br>RDS(on)<br>(mΩ)<br>VGS=4.5V<br>26<br>25.6<br>25.2<br>24.8<br>24.4<br>24<br>1 1.5 2 2.5 3 3.5 ID(A)<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

**Figure 8. Capacitance variations** 

**Figure 9. Normalized gate threshold voltage vs temperature** 

**==> picture [462 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
C AM18133v1 VGS(th) AM18134v1<br>(pF) (norm)<br>1.2 ID=250µA<br>Ciss<br>1<br>0.8<br>100<br>Coss 0.6<br>0.4<br>0.2<br>Crss<br>10 0<br>0 4 8 12 16 VDS(V) -55 -30 -5 20 45 70 95 120 TJ(°C)<br>**----- End of picture text -----**<br>


**Figure 10. Normalized on-resistance vs temperature** 

**Figure 11. Normalized V(BR)DSS vs temperature** 

**==> picture [462 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
RDS(on) AM18135v1 V(BR)DSS AM18136v1<br>(norm)<br>(norm)<br>ID=2A<br>ID=1mA<br>VGS=10V<br>1.6 1.1<br>1.4<br>1.2 1.05<br>1<br>0.8 1<br>0.6<br>0.4 0.95<br>0.2<br>0 0.9<br>-55 -30 -5 20 45 70 95 120 TJ(°C) -55 -30 -5 20 45 70 95 120 TJ(°C)<br>**----- End of picture text -----**<br>


**Figure 12. Source-drain diode forward characteristics** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM18137v1<br>VSD (V)<br>TJ=-55°C<br>0.9<br>0.8<br>TJ=25°C<br>0.7<br>0.6<br>TJ=150°C<br>0.5<br>0.4<br>0.3<br>0.5 1.5 2.5 3.5 4.5 ISD(A)<br>**----- End of picture text -----**<br>


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**Test circuits** 

## **3 Test circuits** 

**Figure 13. Switching times test circuit for resistive load** 

**Figure 14. Gate charge test circuit** 

**==> picture [462 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>12V 47kΩ<br>1kΩ<br>100nF<br>RL 2200 3.3<br>μF μF<br>VDD IG=CONST<br>VD Vi=20V=VGMAX 100Ω D.U.T.<br>VGS<br>2200<br>RG D.U.T. μF 2.7kΩ VG<br>PW<br>47kΩ<br>1kΩ<br>PW<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


**Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test circuit switching and diode recovery times** 

**==> picture [462 x 346] intentionally omitted <==**

**----- Start of picture text -----**<br>
L<br>A A A<br>D<br>FAST L=100μH VD<br>G D.U.T. DIODE 2200 3.3<br>S B 3.3 1000 μF μF VDD<br>25 Ω B B D μF μF VDD ID<br>G<br>RG S<br>Vi D.U.T.<br>Pw<br>AM01470v1 AM01471v1<br>Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform<br>V(BR)DSS ton toff<br>VD tdon tr tdoff tf<br>90% 90%<br>IDM<br>10%<br>ID 0 10% VDS<br>VDD VDD 90%<br>VGS<br>AM01472v1 0 10% AM01473v1<br>**----- End of picture text -----**<br>


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**Package mechanical data** 

## **4 Package mechanical data** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _www.st.com_ . ECOPACK[®] is an ST trademark. 

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**Package mechanical data** 

## **Figure 19. PowerFLAT™ 2 x 2 drawing** 

**==> picture [405 x 540] intentionally omitted <==**

**----- Start of picture text -----**<br>
8368575_REV_C<br>**----- End of picture text -----**<br>


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**Package mechanical data** 

**Table 8. PowerFLAT™ 2x2 mechanical data** 

|**Dim.**|**mm.**|**mm.**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|0.70|0.75|0.80|
|A1|0.00|0.02|0.05|
|A3||0.20||
|b|0.25|0.30|0.35|
|D|1.90|2.00|2.10|
|E|1.90|2.00|2.10|
|D2|0.90|1.00|1.10|
|E2|0.80|0.90|1.00|
|e|0.55|0.65|0.75|
|K|0.15|0.25|0.35|
|K1|0.20|0.30|0.40|
|K2|0.25|0.35|0.45|
|L|0.20|0.25|0.30|
|L1|0.65|0.75|0.85|



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**Package mechanical data** 

**==> picture [388 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 20. PowerFLAT™ 2 x 2 recommended footprint (dimensions in millimeters)<br>**----- End of picture text -----**<br>


**==> picture [405 x 427] intentionally omitted <==**

**----- Start of picture text -----**<br>
Footprint<br>**----- End of picture text -----**<br>


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**Revision history** 

## **5 Revision history** 

**Table 9. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|24-Apr-2012|1|First release.|
|10-Jan-2013|2|– Modified: RDS(on)values<br>– Document status promoted from target data to preliminary data|
|19-Mar-2014|3|– Modified: the entire typical values in_Table 5_,_6_and_7_<br>– Added:_Section 2.1: Electrical characteristics (curves)_<br>– Minor text changes|



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