# Power MOSFET, P Channel, 40 V, 60 A, 0.0115 ohm, PowerFLAT, Surface Mount

![Product image](https://novapart.co/image/farnell:2807203RL/)

**URL**: https://novapart.co/products/STL60P4LLF6/power-mosfet-p-channel-40-v-60-a-00115-ohm
**SKU**: STL60P4LLF6
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.5120
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:P Channel; Continuous Drain Current Id:-60A; Drain Source Voltage Vds:-40V; On Resistance Rds(on):0.0115ohm; Rds(on) Test Voltage Vgs:-10V; Threshold Voltage Vgs:-

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | P Channel |
| Product Range | STripFET F6 |
| Qualification | - |
| Power Dissipation | 100W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | PowerFLAT |
| Drain Source Voltage Vds | 40V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 60A |
| Drain Source On State Resistance | 0.0115ohm |
| Gate Source Threshold Voltage Max | 1V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2807203RL/)

## **STL60P4LLF6** 

## P-channel 40 V, 0.0115 Ω typ.,60 A STripFET™ F6 Power MOSFET in a PowerFLAT™ 5x6 package Datasheet - production data 

- Very low on-resistance 

- Very low gate charge 

- High avalanche ruggedness 

- Low gate drive power loss 

## **Applications** 

Switching applications 

## **Description** 

**Figure 1: Internal schematic diagram** 

This device is a P-channel Power MOSFET developed using the STripFET™ F6 technology with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. 

|**Order codes**|**Marking**|**Package**|**Packaging**|
|---|---|---|---|
|STL60P4LLF6 60P4LLF6|STL60P4LLF6 60P4LLF6|STL60P4LLF6 60P4LLF6PowerFLA™<br>5x6|PowerFLA™<br>Tape and reel|



- [For the P-channel Power MOSFETs the ] actual polarity of the voltages and the current must be reversed. 

## **Features** 

|**Order codes**|**VDS**|**RDS(on)max.**|**ID**|
|---|---|---|---|
|STL60P4LLF6|40 V|0.014 Ω|60|



December 2014 

DocID026840 Rev 2 

1/14 

This is information on a product in full production. 

_www.st.com_ 

|**Contents**<br>**STL60P4LLF6**|**Contents**<br>**STL60P4LLF6**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package mechanical data ............................................................... 9**|
||4.1<br>PowerFLAT™ 5x6 type S-R drawings ............................................... 9|
|**5**|**Packaging mechanical data .......................................................... 11**|
|**6**|**Revision history ............................................................................ 13**|



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**STL60P4LLF6** 

**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**<br>~~a~~|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS<br>~~a~~|Drain-source voltage|40|V|
|VGS<br>~~a~~<br>~~a~~|Gate-source voltage<br>~~a~~|± 20<br>~~a~~|V<br>~~a~~|
|ID<br>_(1)_<br>~~a~~|Drain current (continuous) at TC= 25 °C<br>~~a~~|60<br>~~a~~|A<br>~~a~~|
|ID<br>_(1)_<br>~~a~~|Drain current (continuous) at TC= 100 °C<br>~~a~~|42<br>~~a~~|A<br>~~a~~|
|ID<br>_(1)(3)_<br>~~a~~<br>~~a~~|Drain current (pulsed)<br>~~a~~<br>~~a~~<br>~~a~~|240<br>~~a~~<br>~~a~~<br>~~a~~|A<br>~~a~~<br>~~a~~<br>~~a~~|
|ID<br>_(2)_<br>~~a~~|Drain current (continuous) at Tpcb= 25 °C<br>~~a~~|13<br>~~a~~|~~a~~|
|ID<br>_(2)_<br>~~a~~<br>~~a~~|Drain current (continuous) at Tpcb= 100 °C<br>~~a~~<br>~~a~~|9.3<br>~~a~~<br>~~a~~|A<br>~~a~~<br>~~a~~|
|IDM<br>_(2)(3)_<br>~~a~~|Drain current (pulsed)<br>~~a~~|52<br>~~a~~|A<br>~~a~~|
|PTOT<br>_(1)_<br>~~a~~|Total dissipation at TC= 25 °C<br>~~a~~|100<br>~~a~~|W<br>~~a~~|
|PTOT<br>_(2)_<br>~~a~~|Total dissipation at Tpcb= 25 °C<br>~~a~~|4.8<br>~~a~~|W<br>~~a~~|
|~~a~~<br>~~Ce~~|Deratingfactor(2)<br>~~a~~<br>~~Ce~~|0.03<br>~~a~~<br>~~Ce~~|W/°C<br>~~a~~<br>~~Ce~~|
|Tstg<br>~~a~~|Storage temperature|- 55 to 175|°C|
|Tj<br>~~a~~<br>~~a~~|Max. operating junction temperature|175|°C|



## **Notes:** 

(1) The value is rated according to Rthj-c 

(2) This value is rated according to Rthj-pcb 

- (3) Pulse width is limited by safe operating area 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case max.|1.5|°C/W|
|Rthj-pcb<br>_(1)_|Thermal resistancejunction-pcb, single operation|31.3|°C/W|



## **Notes:** 

- (1)When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec 

For the P-channel Power MOSFETs the actual polarity of the voltages and the current must be reversed. 

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**STL60P4LLF6** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

||**Table 4:On/offstates**|**Table 4:On/offstates**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0,<br>ID= 250µA|40|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0,<br>VDS= 40 V|||1|µA|
|||VGS= 0,<br>VDS= 40 V,<br>TC= 125 °C|||10|µA|
|IGSS|Gate-body leakage<br>current|VDS= 0,<br>VGS= ± 20 V|||±100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS,<br>ID= 250 µA|1|||V|
|RDS(on)|Static drain source<br>on-resistance|VGS= 10 V,<br>ID= 6.5 A||0.0115|0.014|Ω|
|||VGS= 4.5 V,<br>ID= 6.5 A||0.015|0.019|Ω|



||**Table 5: Dynamic**|**Table 5: Dynamic**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|CISS|Input capacitance|VDS= 25 V, f = 1 MHz,<br>VGS= 0|-|3525|-|pF|
|COSS|Output capacitance|||344||pF|
|Crss|Reverse transfer<br>capacitance|||238||pF|
|Qg|Total gate charge|VDD= 20 V, ID= 13 A,<br>VGS= 4.5 V||34||nC|
|Qgs|Gate-source charge|||11.3||nC|
|Qgd|Gate-drain charge|||13.8||nC|



||**Table 6: Switching times**|**Table 6: Switching times**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|td(on)|Turn-on delaytime<br>Rise time<br>Turn-off delay time<br>Fall time|VDD= 20 V, ID= 6.5 A,<br>RG= 4.7 Ω, VGS= 10 V|-|49.4|-|ns|
|tr|||-|60.6|-|ns|
|td(off)|||-|170|-|ns|
|tf|||-|20|-|ns|



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**STL60P4LLF6** 

**Electrical characteristics** 

## **Table 7: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VSD<br>_(1)_|Forward on voltage|ISD= 6.5 A, VGS= 0|-||1.1|V|
|trr|Reverse recoverytime|ISD= 13 A, di/dt = 100 A/µs<br>VDD= 24 V, Tj=150 °C|-|29||ns|
|Qrr|Reverse recoverycharge||-|27.6||nC|
|IRRM|Reverse recoverycurrent||-|1.9||A|



## **Notes:** 

(1) Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

For the P-channel Power MOSFETs the actual polarity of the voltages and the current must be reversed. 

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**STL60P4LLF6** 

**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**==> picture [391 x 175] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>ID GIPG010820141518LM<br>(A)<br>100<br>100µs<br>10 1ms<br>10ms<br>1<br>0.1<br>Tj=175 °C<br>Tc=25 °C<br>Single pulse<br>0.01<br>0.1 1 10 VDS(V)<br>Operation in this area isDS(on)<br>Limited by max R<br>**----- End of picture text -----**<br>


**Figure 4: Output characteristics** 

**==> picture [158 x 153] intentionally omitted <==**

**Figure 5: Transfer characteristics** 

**==> picture [163 x 153] intentionally omitted <==**

**==> picture [409 x 175] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 6: Gate charge vs gate-source voltage  Figure 7: Static drain-source on-resistance<br>GIPG020920141000LM GIPG010920141638LM<br>VGS RDS(on)<br>(V) (mΩ)<br>VDD = 20 V VGS=10V<br>12 13<br>ID = 10 A<br>10<br>12<br>8<br>11<br>6<br>10<br>4<br>2 9<br>0 8<br>0 20 40 60 80 Qg(nC) 0 1 2 3 4 5 6 7 8 9 10 11 12 ID(A)<br>**----- End of picture text -----**<br>


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**STL60P4LLF6** 

**Electrical characteristics** 

**Figure 8: Capacitance variation** 

**==> picture [171 x 153] intentionally omitted <==**

**Figure 9: Normalized gate threshold voltage vs temperature** 

**==> picture [172 x 153] intentionally omitted <==**

**Figure 10: Normalized on-resistance vs Figure 11: Normalized VBR(DSS) vs temperature temperature** 

**==> picture [171 x 142] intentionally omitted <==**

**==> picture [170 x 141] intentionally omitted <==**

**Figure 12: Source-drain diode forward characteristics** 

**==> picture [154 x 133] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 586] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Switching times test circuit for<br>Figure 14: Gate charge test circuit<br>resistive load<br>VDD<br>12 V 47 kΩ<br>1 kΩ<br>100 nF<br>I G = CONST<br>Vi ≤ V GS 100 Ω D.U.T.<br>2.7 kΩ VG<br>2200 μ F<br>47 kΩ<br>1 kΩ<br>PW<br>AM01469v1<br>Figure 15: Test circuit for inductive load  Figure 16: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>Figure 17: Unclamped inductive waveform  Figure 18: Switching time waveform<br>V(BR)DSS t on toff<br>t d(on) t r td(off) t f<br>VD<br>90% 90%<br>I DM<br>10%<br>I D 0 10% VDS<br>VDD VDD<br>90%<br>VGS<br>AM01472v1 0 10% AM01473v1<br>**----- End of picture text -----**<br>


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**Package mechanical** data 

## **4 Package mechanical data** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: www.st.com. ECOPACK[®] is an ST trademark. 

## **4.1 PowerFLAT™ 5x6 type S-R drawings** 

**Figure 19: PowerFLAT™ 5x6 drawings** 

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**STL60P4LLF6** 

**Package mechanical** data 

|**chanical** data|**STL60P4LLF6**|**STL60P4LLF6**|**STL60P4LLF6**|
|---|---|---|---|
||**Table 8: PowerFLAT™5x6 type S-R mechanical data**|||
|**Dim.**||**mm**||
||**Min.**|**Typ.**|**Max.**|
|A|0.80||1.00|
|A1|0.02||0.05|
|A2||0.25||
|b|0.30||0.50|
|D|5.00|5.20|5.40|
|E|5.95|6.15|6.35|
|D2|4.11||4.31|
|E2|3.50||3.70|
|e||1.27||
|L|0.60||0.80|
|K|1.275||1.575|



**Figure 20: PowerFLAT™ 5x6 recommended footprint** 

**==> picture [407 x 281] intentionally omitted <==**

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**Packaging mechanical** data 

## **5 Packaging mechanical data** 

**Figure 21: PowerFLAT™ 5x6 tape** 

**==> picture [407 x 261] intentionally omitted <==**

**Figure 22: PowerFLAT™ 5x6 package orientation in carrier tape** 

Pin identification 

**==> picture [329 x 129] intentionally omitted <==**

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**Packaging mechanical** data 

**Figure 23: PowerFLAT™ 5x6 reel** 

**==> picture [407 x 259] intentionally omitted <==**

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**Revision history** 

## **6 Revision history** 

||**Table 9: Document revision history**|**Table 9: Document revision history**|
|---|---|---|
|**Date**|**Revision**|**Changes**|
|04-Sep-2014|1|Initial release.|
|16-Dec-2014|2|Document status promoted from preliminary data to<br>production data.<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2014 STMicroelectronics – All rights reserved 

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- [Supplier page](https://es.farnell.com/stmicroelectronics/stl60p4llf6/mosfet-p-ch-40v-60a-powerflat/dp/2807203RL)
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