# Dual MOSFET, Dual N Channel, 40 V, 18 A, 0.016 ohm

![Product image](https://novapart.co/image/farnell:4826861RL/)

**URL**: https://novapart.co/products/STL52DN4LF7AG/dual-mosfet-n-channel-40-v-18-a-0016-ohm
**SKU**: STL52DN4LF7AG
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Dual MOSFETs
**Price**: €0.4620
**Stock**: 200+
**Lead Time**: 34 days (indicative)

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:4826861RL/)

## **STL52DN4LF7AG** 

Automotive-grade dual N-channel 40 V, 9 mΩ typ., 18 A STripFET™ F7 Power MOSFET in a PowerFLAT™ 5x6 DI 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS**|**RDS(on) max.**|ID|
|---|---|---|---|
|STL52DN4LF7AG|40 V|16 mΩ|18 A|



- AEC-Q101 qualified 

- Among the lowest RDS(on) on the market 

- Excellent FoM (figure of merit) 

- Low Crss/Ciss ratio for EMI immunity 

- High avalanche ruggedness 

- Wettable flank package 

## **Applications** 

- Switching applications 

## **Description** 

**Figure 1: Internal schematic diagram** 

This N-channel Power MOSFET utilizes 

STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STL52DN4LF7AG|52DN4LF7|PowerFLAT™ 5x6 double island|Tape and reel|



December 2017 

DocID029278 Rev 4 

This is information on a product in full production. 

_www.st.com_ 

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**Contents** 

**STL52DN4LF7AG** 

## **Contents** 

|**1**|**Electrical ratings ............................................................................. 3**|
|---|---|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ......................................................**6**|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>PowerFLAT™ 5x6 double island WF type R  package information .**10**|
||4.2<br>Packing information .........................................................................**13**|
|**5**|**Revision history ............................................................................ 15**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|40|V|
|VGS|Gate-source voltage|±20|V|
|ID_(1)_|Drain current (continuous) at TC= 25 °C|18|A|
|ID_(1)_|Drain current (continuous) at Tc= 100 °C|18|A|
|IDM_(1)(2)_|Drain current (pulsed)|72|A|
|PTOT|Total dissipation at TC= 25 °C|65|W|
|Tstg|Storage temperature range|-55 to 175|°C|
|TJ|Operationjunction temperature range|||



## **Notes:** 

(1)Drain current is limited by package, the current capability of the silicon is 46 A at 25 °C and 33 A at 100 °C. (2)Pulse width limited by safe operating area 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|2.3|°C/W|
|Rthj-pcb_(1)_|Thermal resistancejunction-pcb|32||



## **Notes:** 

(1)When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s 

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**STL52DN4LF7AG** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

## **Table 4: On/Off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|ID= 1 mA, VGS= 0 V|40|||V|
|IDSS|Zero gate voltage<br>drain current|VGS= 0 V<br>VDS= 40 V|||10|µA|
|IGSS|Gate-body leakage<br>current|VGS= ± 20 V, VDS= 0 V|||100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 μA|1.5||2.5|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID= 6 A||9|16|mΩ|
|||VGS= 4.5 V, ID= 6 A||12|20||



## **Table 5: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 25 V, f = 1 MHz,<br>VGS= 0 V|-|500|-|pF|
|Coss|Output capacitance||-|140|-|pF|
|Crss|Reverse transfer<br>capacitance||-|20|-|pF|
|Qg|Totalgate charge|VDD= 20 V, ID= 12 A,<br>VGS= 0 to 10 V<br>(see_Figure 14: "Test circuit for_<br>_gate charge behavior"_)|-|9.4|-|nC|
|Qgs|Gate-source charge||-|1.6|-|nC|
|Qgd|Gate-drain charge||-|2|-|nC|



**Table 6: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 32 V, ID= 6 A,<br>RG= 4.7 Ω, VGS= 10 V<br>(see_Figure 13: "Test circuit for_<br>_resistive load switching times"_<br>and_Figure 18: "Switching time_<br>_waveform"_)|-|6.5|-|ns|
|tr|Rise time||-|5|-|ns|
|td(off)|Turn-off delay time||-|48|-|ns|
|tf|Fall time||-|14.5|-|ns|



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**Electrical characteristics** 

**Table 7: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD_(1)_|Source-drain<br>current||-||18|A|
|ISDM_(2)_|Source-drain<br>current<br>(pulsed)||-||72|A|
|VSD_(3)_|Forward on<br>voltage|ISD= 12 A, VGS= 0 V|-||1.3|V|
|trr|Reverse<br>recoverytime|ISD= 12 A, di/dt = 100 A/µs<br>VDD= 32 V<br>(see_Figure 15: "Test circuit for inductive_<br>_load switching and diode recovery_<br>_times"_)|-|18||ns|
|Qrr|Reverse<br>recoverycharge||-|7.5||nC|
|IRRM|Reverse<br>recoverycurrent||-|0.8||A|



## **Notes:** 

(1)Drain current is limited by package, the current capability of the silicon is 46 A at 25 °C. 

(2) Pulse width limited by safe operating area. 

(3)Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

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**STL52DN4LF7AG** 

## **Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**==> picture [194 x 163] intentionally omitted <==**

**==> picture [128 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


**==> picture [170 x 164] intentionally omitted <==**

**Figure 4: Output characteristics** 

**==> picture [178 x 164] intentionally omitted <==**

**Figure 5: Transfer characteristics** 

**==> picture [179 x 164] intentionally omitted <==**

**Figure 6: Gate charge vs gate-source voltage** 

**==> picture [183 x 163] intentionally omitted <==**

**Figure 7: Static drain-source on-resistance** 

**==> picture [184 x 164] intentionally omitted <==**

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**Electrical characteristics** 

**==> picture [436 x 202] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 8: Capacitance variations  Figure 9: Normalized gate threshold voltage vs<br>temperature<br>**----- End of picture text -----**<br>


**Figure 10: Normalized on-resistance vs temperature** 

**==> picture [196 x 169] intentionally omitted <==**

**Figure 11: Normalized V(BR)DSS vs temperature** 

**==> picture [195 x 165] intentionally omitted <==**

**Figure 12: Source-drain diode forward characteristics** 

**==> picture [188 x 171] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 375] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Test circuit for resistive load  Figure 14: Test circuit for gate charge<br>switching times  behavior<br>Figure 15: Test circuit for inductive load  Figure 16: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>**----- End of picture text -----**<br>


**==> picture [403 x 170] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 17: Unclamped inductive waveform  Figure 18: Switching time waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**STL52DN4LF7AG** 

## **Package information** 

## **4.1 PowerFLAT™ 5x6 double island WF type R  package information** 

**Figure 19: PowerFLAT™ 5x6 double island WF type R package outline** 

**==> picture [406 x 496] intentionally omitted <==**

**----- Start of picture text -----**<br>
8256945_r16_typeR-WF<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 8: PowerFLAT™ 5x6 double island WF type R mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|0.80||1.00|
|A1|0.02||0.05|
|A2||0.25||
|b|0.30||0.50|
|C|5.80|6.00|6.10|
|D|5.00|5.20|5.40|
|D2|4.15||4.45|
|D3|4.05|4.20|4.35|
|D4|4.80|5.00|5.10|
|D5|0.25|0.40|0.55|
|D6|0.15|0.30|0.45|
|D7|1.68||1.98|
|e||1.27||
|E|6.20|6.40|6.60|
|E2|3.50||3.70|
|E3|2.35||2.55|
|E4|0.40||0.60|
|E5|0.08||0.28|
|E6|0.20|0.325|0.45|
|E7|0.85|1.00|1.15|
|E8|0.55||0.75|
|E9|4.00|4.20|4.40|
|E10|3.55|3.70|3.85|
|K|1.275||1.575|
|L|0.725|0.825|0.925|
|L1|0.175|0.275|0.375|
|θ|0°||12°|



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## **Package information** 

**Figure 20: PowerFLAT™ 5x6 double island recommended footprint (dimensions are in mm)** 

**==> picture [406 x 342] intentionally omitted <==**

**----- Start of picture text -----**<br>
8256945_FP_std_R16<br>**----- End of picture text -----**<br>


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**Package information** 

## **4.2 Packing information** 

**Figure 21: PowerFLAT™ 5x6 WF tape (dimensions are in mm)** 

**Figure 22: PowerFLAT™ 5x6 package orientation in carrier tape** 

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**Package information** 

**Figure 23: PowerFLAT™ 5x6 reel (dimensions are in mm)** 

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**Revision history** 

## **5 Revision history** 

**Table 9: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|28-Apr-2016|1|First release.|
|20-Jun-2016|2|Updated_Figure 1: "Internal schematic diagram"_and_Section 7.1:_<br>_"PowerFLAT™ 5x6 double island WF type R package information"_<br>Minor text changes.|
|13-Sep-2016|3|Updated_Section 5: "Electrical characteristics"_|
|18-Dec-2017|4|Datasheet promoted from preliminary data to production data.<br>Modified title.<br>Modified_Table 4: "On/Off states"_,_Table 5: "Dynamic"_,_Table 6:_<br>_"Switching times"_and_Table 7: "Source-drain diode"_.<br>Added_Section 5.1: "Electrical characteristics (curves)"_.<br>Minor text changes.|



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**STL52DN4LF7AG** 

## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2017 STMicroelectronics – All rights reserved 

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## Links

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- [Supplier page](https://es.farnell.com/stmicroelectronics/stl52dn4lf7ag/mosfet-dual-n-ch-40v-18a-powerflat/dp/4826861RL)
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