# Power MOSFET, N Channel, 100 V, 18 A, 0.02 ohm, PowerFLAT, Surface Mount

![Product image](https://novapart.co/image/farnell:2729694RL/)

**URL**: https://novapart.co/products/STL45N10F7AG/power-mosfet-n-channel-100-v-18-a-002-ohm
**SKU**: STL45N10F7AG
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.4530
**Stock**: 10+

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:18A; Drain Source Voltage Vds:100V; On Resistance Rds(on):0.02ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4.5V

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 5Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | AEC-Q101 |
| Power Dissipation | 72W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | PowerFLAT |
| Drain Source Voltage Vds | 100V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 18A |
| Drain Source On State Resistance | 0.02ohm |
| Gate Source Threshold Voltage Max | 4.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2729694RL/)

## **STL45N10F7AG** 

Automotive-grade N-channel 100 V, 20 mΩ typ., 18 A, STripFET™ F7 Power MOSFET in a PowerFLAT™ 5x6 package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS**|**RDS(on) max**|**ID**|**PTOT**|
|---|---|---|---|---|
|STL45N10F7AG|100 V|24 mΩ|18 A|72 W|



- AEC-Q101 qualified 

- Among the lowest RDS(on) on the market 

- Excellent FoM (figure of merit) 

- Low Crss/Ciss ratio for EMI immunity 

- High avalanche ruggedness 

- Wettable flank package 

## **Applications** 

**Figure 1: Internal schematic diagram** 

- Switching applications 

## **Description** 

This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STL45N10F7AG|45N10F7|PowerFLAT™ 5x6|Tape and reel|



This is information on a product in full production. 

_www.st.com_ 

February 2017 

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**Contents** 

**STL45N10F7AG** 

## **Contents** 

|**1**|**Electrical ratings ............................................................................. 3**|
|---|---|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>PowerFLAT™ 5x6 WF type R package information .......................... 9|
||4.2<br>PowerFLAT™ 5x6 packing information ........................................... 12|
|**5**|**Revision history ............................................................................ 14**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|100|V|
|VGS|Gate-source voltage|±20|V|
|ID_(1)_|Drain current (continuous) at TC= 25 °C|18|A|
|ID_(1)_|Drain current (continuous) at TC= 100 °C|18|A|
|IDM_(2)_|Drain current (pulsed)|72|A|
|PTOT|Total dissipation at TC= 25 °C|72|W|
|EAS_(3)_|Singlepulse avalanche energy|150|mJ|
|TJ|Operating junction temperature range|-55 to 175|°C|
|Tstg|Storage temperature range|||



## **Notes:** 

(1)Limited by package. 

(2)Pulse width limited by safe operating area. 

(3)Starting Tj = 25 °C, ID = 9 A, VDD = 60 V 

**Table 3: Thermal resistance** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|2.08|°C/W|
|Rthj-pcb_(1)_|Thermal resistancejunction-pcb|31.3|°C/W|



## **Notes:** 

(1)When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 s 

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**STL45N10F7AG** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(TCASE = 25 °C unless otherwise specified) 

**Table 4: On/off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 250 µA|100|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= 100 V|||1|µA|
|||VGS= 0 V, VDS= 100 V;<br>TC= 125 °C_(1)_|||10||
|IGSS|Gate bodyleakage current|VDS= 0 V, VGS= 20 V|||100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|2.5||4.5|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 9 A||20|24|mΩ|



## **Notes:** 

(1)Defined by design, not subject to production test. 

**Table 5: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 50 V, f = 1 MHz,<br>VGS= 0 V|-|1450|-|pF|
|Coss|Output capacitance||-|350|-|pF|
|Crss|Reverse transfer<br>capacitance||-|25|-|pF|
|Qg|Total gate charge|VDD= 50 V, ID= 18 A, VGS= 0<br>to 10 V<br>(see_Figure 14: "Test circuit_<br>_for gate charge behavior"_)|-|19.5|-|nC|
|Qgs|Gate-source charge||-|9.1|-|nC|
|Qgd|Gate-drain charge||-|4.3|-|nC|



**Table 6: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 50 V, ID= 9 A,<br>RG= 4.7 Ω, VGS= 10 V<br>(see_Figure 13: "Test circuit_<br>_for resistive load switching_<br>_times"_and_Figure 18:_<br>_"Switching time waveform"_)|-|15|-|ns|
|tr|Rise time||-|5.5|-|ns|
|td(off)|Turn-off delaytime||-|17|-|ns|
|tf|Fall time||-|5|-|ns|



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**Electrical characteristics** 

**Table 7: Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||18|A|
|ISDM_(1)_|Source-drain current<br>(pulsed)||-||72|A|
|VSD_(2)_|Forward on voltage|ISD= 9 A, VGS= 0 V|-||1.2|V|
|trr|Reverse recoverytime|ISD= 18 A, di/dt = 100 A/µs,<br>VDD= 80 V<br>(see_Figure 15: "Test circuit_<br>_for inductive load switching_<br>_and diode recovery times"_)|-|46||ns|
|Qrr|Reverse recoverycharge||-|46||nC|
|IRRM|Reverse recovery current||-|2||A|



## **Notes:** 

(1)Pulse width limited by safe operating area 

(2)Pulsed: pulse duration=300 µs, duty cycle 1.5% 

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**STL45N10F7AG** 

**Electrical characteristics 2.1 Electrical characteristics (curves)** 

**==> picture [439 x 190] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


**Figure 4: Output characteristics** 

**==> picture [179 x 164] intentionally omitted <==**

**Figure 5: Transfer characteristics** 

**==> picture [179 x 164] intentionally omitted <==**

**Figure 6: Gate charge vs gate-source voltage** 

**==> picture [183 x 163] intentionally omitted <==**

**Figure 7: Static drain-source on-resistance** 

**==> picture [184 x 164] intentionally omitted <==**

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**----- Start of picture text -----**<br>
STL45N10F7AG Electrical characteristics<br>Figure 8: Capacitance variations  Figure 9: Normalized gate threshold voltage vs<br>temperature<br>**----- End of picture text -----**<br>


**==> picture [466 x 201] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 10: Normalized on-resistance vs temperature  Figure 11: Source-drain diode forward<br>characteristics<br>**----- End of picture text -----**<br>


**Figure 12: Normalized V(BR)DSS vs temperature** 

**==> picture [170 x 143] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 375] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Test circuit for resistive load  Figure 14: Test circuit for gate charge<br>switching times  behavior<br>Figure 15: Test circuit for inductive load  Figure 16: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>**----- End of picture text -----**<br>


**==> picture [403 x 170] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 17: Unclamped inductive waveform  Figure 18: Switching time waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 PowerFLAT™ 5x6 WF type R package information** 

**Figure 19: PowerFLAT™ 5x6 WF type R package outline** 

**==> picture [406 x 498] intentionally omitted <==**

**----- Start of picture text -----**<br>
A0Y5_8231817_R_WF_Rev_14<br>**----- End of picture text -----**<br>


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**Package information** 

|**formation**<br>**STL45N10F7AG**|**formation**<br>**STL45N10F7AG**|**formation**<br>**STL45N10F7AG**|**formation**<br>**STL45N10F7AG**|
|---|---|---|---|
|**Table 8: PowerFLAT™ 5x6 WF type R mechanical data**||||
|**Dim.**||**mm**||
||**Min.**|**Typ.**|**Max.**|
|A|0.80||1.00|
|A1|0.02||0.05|
|A2||0.25||
|b|0.30||0.50|
|C|5.80|6.00|6.10|
|D|5.00|5.20|5.40|
|D2|4.15||4.45|
|D3|4.05|4.20|4.35|
|D4|4.80|5.00|5.10|
|D5|0.25|0.4|0.55|
|D6|0.15|0.3|0.45|
|e||1.27||
|E|6.20|6.40|6.60|
|E2|3.50||3.70|
|E3|2.35||2.55|
|E4|0.40||0.60|
|E5|0.08||0.28|
|E6|0.20|0.325|0.45|
|E7|0.85|1.00|1.15|
|E9|4.00|4.20|4.40|
|E10|3.55|3.70|3.85|
|K|1.275||1.575|
|L|0.725|0.825|0.925|
|L1|0.175|0.275|0.375|
|ϴ|0°||12°|



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**Package information** 

**Figure 20: PowerFLAT™ 5x6 recommended footprint (dimensions are in mm)** 

**==> picture [406 x 332] intentionally omitted <==**

**----- Start of picture text -----**<br>
8231817_FOOTPRINT_rev14<br>**----- End of picture text -----**<br>


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**Package information** 

## **4.2 PowerFLAT™ 5x6 packing information** 

**Figure 21: PowerFLAT™ 5x6 WF tape (dimensions are in mm)** 

**Figure 22: PowerFLAT™ 5x6 package orientation in carrier tape** 

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**Package information** 

**Figure 23: PowerFLAT™ 5x6 reel (dimensions are in mm)** 

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**Revision history** 

## **5 Revision history** 

**Table 9: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|16-Feb-2017|1|First release.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2017 STMicroelectronics – All rights reserved 

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## Links

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- [Supplier page](https://es.farnell.com/stmicroelectronics/stl45n10f7ag/mosfet-n-ch-100v-18a-powerflat/dp/2729694RL)
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