# Power MOSFET, N Channel, 100 V, 40 A, 0.02 ohm, PowerFLAT, Surface Mount

![Product image](https://novapart.co/image/farnell:3367054/)

**URL**: https://novapart.co/products/STL40N10F7/power-mosfet-n-channel-100-v-40-a-002-ohm
**SKU**: STL40N10F7
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.5480
**Stock**: 1000+
**Lead Time**: 2 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | STripFET F7 |
| Qualification | - |
| Power Dissipation | 70W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | PowerFLAT |
| Drain Source Voltage Vds | 100V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 40A |
| Drain Source On State Resistance | 0.02ohm |
| Gate Source Threshold Voltage Max | 4.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3367054/)

## **STL40N10F7** 

N-channel 100 V, 0.02 Ω typ., 10 A STripFET™ F7 Power MOSFET in a PowerFLAT™ 5x6 package 

Datasheet - production data 

## **Features** 

|**Order code**<br>~~Soa~~|**VDS**<br>~~Soa~~|**RDS(on) max.**<br>~~Soa~~<br>~~se~~|ID<br>~~se~~|**PTOT**|
|---|---|---|---|---|
|STL40N10F7<br>~~Soa~~|100 V<br>~~Soa~~|0.024Ω<br>~~Soa~~<br>~~se~~|10 A<br>~~se~~|5 W|



- Among the lowest RDS(on) on the market 

- Excellent figure of merit (FoM) 

- Low Crss/Ciss ratio for EMI immunity 

- High avalanche ruggedness 

## **Applications** 

- Switching applications 

## **Description** 

**Figure 1: Internal schematic diagram** 

This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STL40N10F7|40N10F7|PowerFLATTM5x6|Tape and reel|



This is information on a product in full production. 

_www.st.com_ 

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|**Contents**<br>**STL40N10F7**|**Contents**<br>**STL40N10F7**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................... 3**|
|**2**|**Electrical characteristics ................................................................. 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ...................................................................................... 8**|
|**4**|**Package information ........................................................................ 9**|
||4.1<br>PowerFLAT 5x6 type R package information .................................. 10|
||4.2<br>Packing information ......................................................................... 12|
|**5**|**Revision history .............................................................................. 14**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|100|V|
|VGS|Gate-source voltage|± 20|V|
|ID<br>_(1)_|Drain current (continuous) at TC= 25 °C|40|A|
|ID<br>_(1)_|Drain current (continuous) at TC= 100 °C|28|A|
|ID<br>_(2)_|Drain current (continuous) at Tpcb= 25 °C|10|A|
|ID<br>_(2)_|Drain current (continuous) at Tpcb= 100 °C|7|A|
|IDM<br>_(2)(3)_|Drain current (pulsed)|40|A|
|PTOT<br>_(1)_|Total dissipation at TC= 25 °C|70|W|
|PTOT<br>_(2)_|Total dissipation at Tpcb= 25 °C|5|W|
|Tj|Operating junction temperature range|-55 to 175|°C|
|Tstg|Storage temperature range|||



## **Notes:** 

- (1) This value is rated according to Rthj-c 

- (2) This value is rated according to Rthj-pcb 

- (3) Pulse width limited by safe operating area 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistance junction-case max.|2.08|°C/W|
|Rthj-pcb<br>_(1)_|Thermal resistance junction-pcb max.|30|°C/W|



## **Notes:** 

(1) When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 sec 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

**Table 4: On/Off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|ID= 250 μA, VGS= 0 V|100|||V|
|IDSS|Zero gate voltage<br>drain current|VGS= 0 V<br>VDS= 100 V|||10|µA|
|||VGS= 0 V, VDS= 100 V, TC=<br>125° C|||100|μA|
|IGSS|Gate-body leakage<br>current|VDS= 0 V, VGS= +20 V|||100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 μA|3||4.5|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID= 10 A||0.02|0.024|Ω|



## **Table 5: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 50 V, f = 1 MHz,<br>VGS= 0 V|-|1270|-|pF|
|Coss|Output capacitance||-|290|-|pF|
|Crss|Reverse transfer<br>capacitance||-|24|-|pF|
|Qg|Total gate charge|VDD= 50 V, ID= 32 A,<br>VGS= 10 V (see_Figure 14: "Test_<br>_circuit for gate charge behavior"_)|-|19|-|nC|
|Qgs|Gate-source charge||-|9|-|nC|
|Qgd|Gate-drain charge||-|4.5|-|nC|



## **Table 6: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay<br>time|VDD= 50 V, ID= 16 A,<br>RG= 4.7 Ω, VGS= 10 V (see_Figure 13:_<br>_"Test circuit for resistive load switching_<br>_times"_)|-|12|-|ns|
|tr|Rise time||-|17.5|-|ns|
|td(off)|Turn-off delay<br>time||-|22|-|ns|
|tf|Fall time||-|5.6|-|ns|



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**Electrical characteristics** 

|||**Table 7: Source-drain diode**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|ISD|Source-drain<br>curren|ISD= 32 A, VGS= 0 V|-||32|A|
|ISDM<br>_(1)_|Source-drain<br>current (pulsed)||||128|A|
|VSD<br>_(2)_|Forward on<br>voltage||||1.1|V|
|trr|Reverse<br>recovery time|ISD= 32 A, di/dt = 100 A/µs<br>VDD= 80 V. TJ= 150° C (see_Figure 15:_<br>_"Test circuit for inductive load switching_<br>_and diode recovery times"_|-|41||ns|
|Qrr|Reverse<br>recovery charge||-|47||nC|
|IRRM|Reverse<br>recovery current||-|2.3||A|



## **Notes:** 

(1) Pulse width limited by safe operating area 

(2) Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**==> picture [386 x 157] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>ID GIPG270320141147SA ‘ GIPG270320141356SA<br>(A)  Say d<br>0.2<br>10<br>10" f l 0.050.1<br>1<br>0.02<br>10ms 0.01<br>107 All Ztb=h =tp/Tk Rins—peb<br>100ms<br>0.1 1s<br>Tj=175°C<br>Single pulseTpcb=25°C Single tpL-<br>0.01 10° pulse kal<br>0.1 1 10 VDS(V) 10° 10* 10% 10% 10' 10° 10! tp(s)<br>DS(on)<br>Operation in this area is<br>Limited by max R<br>**----- End of picture text -----**<br>


**Figure 4: Output characteristics** 

**Figure 5: Transfer characteristics** 

**Figure 6: Gate charge vs gate-source voltage** 

**Figure 7: Static drain-source on-resistance** 

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**Electrical characteristics** 

**Figure 8: Capacitance variations** 

**Figure 9: Normalized gate threshold voltage vs temperature** 

**Figure 10: Normalized on-resistance vs Figure 11: Normalized V(BR)DSS vs temperature temperature** 

**==> picture [5 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
µ<br>**----- End of picture text -----**<br>


**Figure 12: Source-drain diode forward characteristics** 

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 393] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Test circuit for resistive load  Figure 14: Test circuit for gate charge<br>switching times  behavior<br>Figure 15: Test circuit for inductive load<br>Figure 16: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>**----- End of picture text -----**<br>


**==> picture [403 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 17: Unclamped inductive waveform  Figure 18: Switching time waveform<br>**----- End of picture text -----**<br>


**==> picture [94 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
DocID024671 Rev 4<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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## **Package information** 

## **4.1 PowerFLAT 5x6 type R package information** 

**Figure 19: PowerFLAT™ 5x6 type R package outline** 

**==> picture [406 x 545] intentionally omitted <==**

**----- Start of picture text -----**<br>
A0ER_8231817_Rev12<br>**----- End of picture text -----**<br>


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**Package information** 

|**F7**|**Package information**|**Package information**|**Package information**|
|---|---|---|---|
||**Table 8: PowerFLAT™ 5x6 type R mechanical data**|||
|**Dim.**||**mm**||
||**Min.**|**Typ.**|**Max.**|
|A|0.80||1.00|
|A1|0.02||0.05|
|A2||0.25||
|b|0.30||0.50|
|C|5.80|6.00|6.20|
|D|5.00|5.20|5.40|
|D2|4.15||4.45|
|D3|4.05|4.20|4.35|
|D4|4.80|5.0|5.20|
|D5|0.25|0.4|0.55|
|D6|0.15|0.3|0.45|
|e||1.27||
|E|5.95|6.15|6.35|
|E2|3.50||3.70|
|E3|2.35||2.55|
|E4|0.40||0.60|
|E5|0.08||0.28|
|E6|0.2|0.325|0.450|
|E7|0.75|0.90|1.25|
|K|1.275||1.575|
|L|0.60||0.80|
|L1|0.05|0.15|0.25|
|θ|0°||12°|



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## **Package information** 

**Figure 20: PowerFLAT™ 5x6 recommended footprint (dimensions are in mm)** 

**==> picture [92 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
8231817_FOOTPRINT_simp_R12<br>**----- End of picture text -----**<br>


## **4.2** 

## **Packing information** 

**Figure 21: PowerFLAT™ 5x6 tape (dimensions are in mm)** 

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**Package information** 

**Figure 22: PowerFLAT™ 5x6 package orientation in carrier tape** 

**Figure 23: PowerFLAT™ 5x6 reel** 

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**Revision history** 

## **5 Revision history** 

**Table 9: Document revision history** 

|**Date**|**Revis**<br>**ion**|**Changes**|
|---|---|---|
|20-May-2015|1|First release.|
|02-Nov-2015|2|Document status promoted from preliminary to production data.<br>Modified: VGS(th)values in tab 4.<br>Updated the entire typical values in tab 5, tab 6 and tab7<br>Added Electrical characteristics (curves)<br>Updated Figure 13, 14, 15 and 16<br>Minor text changes.|
|18-Dec-2015|3|Updated title, features and description.<br>Updated_Table 2: "Absolute maximum ratings"_and_Table 4: "On/Off_<br>_states"_.<br>Minor text changes.|
|01-Feb 2016|4|Updated_Table 5: "Dynamic"_<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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## Links

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- [Supplier page](https://es.farnell.com/stmicroelectronics/stl40n10f7/mosfet-n-ch-100v-40a-175deg-c/dp/3367054)
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