# Power MOSFET, N Channel, 600 V, 2.2 A, 1.5 ohm, PowerFLAT, Surface Mount

![Product image](https://novapart.co/image/farnell:2629759RL/)

**URL**: https://novapart.co/products/STL3NM60N/power-mosfet-n-channel-600-v-22-a-15-ohm-powerflat
**SKU**: STL3NM60N
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.8050
**Stock**: 10+

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:2.2A; Drain Source Voltage Vds:600V; On Resistance Rds(on):1.5ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3V;

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | Mdmesh II |
| Qualification | - |
| Power Dissipation | 22W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | PowerFLAT |
| Drain Source Voltage Vds | 600V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 2.2A |
| Drain Source On State Resistance | 1.5ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2629759RL/)

## **STL3NM60N** 

N-channel 600 V, 1.5 Ω, 2.2 A MDmesh™ II Power MOSFET in a PowerFLAT™ 3.3 x 3.3 HV package 

**Datasheet** - **production data** 

## **Features** 

**==> picture [129 x 89] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>2<br>3<br>4<br>8 7 5 6<br>6 7<br>5 8<br>PowerFLAT™ 3.3x3.3 HV<br>**----- End of picture text -----**<br>


**Order code RDS(on) max. ID** STL3NM60N 1.8 Ω 2.2 A ~~—~~ • 100% avalanche tested 

- Low input capacitance and gate charge 

- Low gate input resistance 

## **Application** 

- Switching applications 

## **Figure 1. Internal schematic diagram** 

**==> picture [158 x 129] intentionally omitted <==**

**----- Start of picture text -----**<br>
G<br>4 5<br>3 6<br>D<br>2 7<br>1 S 8<br>Bottom View<br>**----- End of picture text -----**<br>


## **Description** 

This device is an N-channel Power MOSFET developed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. 

**Table 1. Device summary Order code Marking Package Packaging** STL3NM60N 3NM60N PowerFLAT™ 3.3 x 3.3 HV Tape and reel ~~—————~~ 

November 2014 

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This is information on a product in full production. 

_www.st.com_ 

**Contents** 

**STL3NM60N** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Electrical characteristics (curves)       . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Test circuits     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8**|
|**4**|**Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9**|
|**5**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|600|V|
|VGS|Gate-source voltage|± 25|V|
|ID<br>(1)|Drain current (continuous) at TC= 25 °C|2.2|A|
|ID<br>(1)|Drain current (continuous) at TC=100 °C|1.7|A|
|ID<br>(2)|Drain current (continuous) at Tamb= 25 °C|0.65|A|
|ID<br>(2)|Drain current (continuous) at Tamb=100 °C|0.5|A|
|IDM<br>(2)(3)|Drain current (pulsed)|2.6|A|
|PTOT<br>(2)|Total dissipation at Tamb= 25 °C|2|W|
|PTOT<br>(1)|Total dissipation at TC= 25 °C|22|W|
|IAS|Avalanche current, repetitive or not-repetitive(3)|1|A|
|EAS|Single pulse avalanche energy(4)|119|mJ|
||Derating factor(2)|0.016|W/°C|
|dv/dt(5)|Peak diode recovery voltage slope|15|V/ns|
|TJ<br>Tstg|Operating junction temperature<br>storage temperature|-55 to 150|°C|



1. The value is rated according Rthj-case. 

2. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec 

3. Pulse width limited by Tjmax 

4. Starting Tj = 25 °C,ID= IAS, VDD= 50V 

5. ISD ≤ 2.2 A, dv/dt ≤ 400 A/µs,VDS peak ≤ V(BR)DSS, VDD= 80% V(BR)DSS 

**Table 3. Thermal resistance** 

||**Table 3. Thermal resistance**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|Rthj-case|Thermal resistance junction-case max.|5.6|°C/W|
|Rthj-amb<br>(1)|Thermal resistance junction-amb max.|62.5|°C/W|



1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec. 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TCASE=25°C unless otherwise specified) 

**Table 4. On/off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage (VGS= 0)|ID= 1 mA|600|||V|
|IDSS|Zero gate voltage drain<br>current (VGS= 0)|VDS= 600 V,|||1|µA|
|||VDS= 600 V, Tc= 125 °C|||100|µA|
|IGSS|Gate body leakage current<br>(VDS= 0)|VGS= ± 25 V|||±100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 µA|2|3|4|V|
|RDS(on)|Static drain-source on<br>resistance|VGS= 10 V, ID= 1 A||1.5|1.8|Ω|



**Table 5. Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 50V, f=1 MHz,<br>VGS=0|-|188|-|pF|
|Coss|Output capacitance||-|13|-|pF|
|Crss|Reverse transfer<br>capacitance||-|1.1|-|pF|
|Coss eq.<br>(1)|Output equivalent<br>capacitance|VGS=0, VDS=0 to 480 V|-|100|-|pF|
|Rg|Gate input resistance|f =1 MHz gate DC bias=0<br>test signal level = 20 mV<br>open drain|-|6|-|Ω|
|Qg|Total gate charge|VDD= 480 V, ID= 2.2 A<br>VGS=10 V<br>_(seeFigure 15)_|-|9.5|-|nC|
|Qgs|Gate-source charge||-|1.6|-|nC|
|Qgd|Gate-drain charge||-|5.3|-|nC|



1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

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**Electrical characteristics** 

**Table 6. Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 300 V, ID= 1.1 A,<br>RG= 4.7Ω,VGS= 10 V<br>_(seeFigure 14)_|-|8.6|-|ns|
|tr|Rise time||-|6.2|-|ns|
|td(off)|Turn-off delay time||-|20.8|-|ns|
|tf|Fall time||-|20|-|ns|



**Table 7. Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min**|**Typ.**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||2.2|A|
|ISDM<br>(1)|Source-drain current (pulsed)||-||8.8|A|
|VSD<br>(2)|Forward on voltage|ISD= 2.2 A, VGS=0|-||1.6|V|
|trr|Reverse recovery time|ISD= 2.2 A,<br>di/dt = 100 A/µs,<br>VDD= 60 V<br>_(seeFigure 16)_|-|168||ns|
|Qrr|Reverse recovery charge||-|672||nC|
|IRRM|Reverse recovery current||-|8||A|
|trr|Reverse recovery time|ISD= 2.2 A,<br>di/dt = 100 A/µs,<br>VDD= 60 V, Tj= 150 °C<br>_(seeFigure 16)_|-|2.3||ns|
|Qrr|Reverse recovery charge||-|913||nC|
|IRRM|Reverse recovery current||-|9||A|



1. Pulse width limited by safe operating area. 

2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2. Safe operating area** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
ID AM11244v1<br>(A)<br>Tj=150°C<br>Tamb=25°C<br>1<br>Sinlge pulse<br>0.1<br>10µs<br>100µs<br>0.01 1ms<br>10ms<br>0.001<br>0.1 1 10 100 VDS(V)<br>DS(on)<br>Operation in this area is<br>Limited by max R<br>**----- End of picture text -----**<br>


## **Figure 4. Output characteristics** 

## **Figure 3. Thermal impedance** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
Zth_powerFLAT 3.3x3.3<br>K<br>d=0.5<br>0.2<br>0.05<br>0.1<br>10-1 0.02<br>0.01 Zth=k Rthj-amb<br>Rthj-amb=62.5 °C/W<br>d=tp/t<br>tp<br>10-2 Single pulse t<br>10-3 10-2 10-1 100 101 102 tp [(s)]<br>**----- End of picture text -----**<br>


## **Figure 5. Transfer characteristics** 

**==> picture [462 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM11245v1 AM11246v1<br>ID ID<br>(A) (A)<br>VGS=10V VDS=21V<br>5 5<br>4 4<br>6V<br>3 3<br>2 2<br>5V<br>1 1<br>0 0<br>0 5 10 15 20 25 30 VDS(V) 0 2 4 6 8 10 VGS(V)<br>**----- End of picture text -----**<br>


## **Figure 6. Gate charge vs gate-source voltage** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
VGS AM11247v1VDS(V)<br>(V)<br>VDD=480V<br>12<br>ID=2.2A 500<br>VDS<br>10<br>400<br>8<br>300<br>6<br>200<br>4<br>100<br>2<br>0 0<br>0 2 4 6 8 10 Qg(nC)<br>**----- End of picture text -----**<br>


## **Figure 7. Static drain-source on resistance** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM11248v1<br>RDS(on)<br>(Ω)<br>1.58 VGS=10V<br>1.56<br>1.54<br>1.52<br>1.50<br>1.48<br>1.46<br>1.44<br>1.42<br>1.40<br>0 0.5 1 1.5 2 ID(A)<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

**Figure 8. Capacitance variations** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
C AM11249v1<br>(pF)<br>1000<br>Ciss<br>100<br>10 Coss<br>1 Crss<br>0.1 1 10 100 VDS(V)<br>**----- End of picture text -----**<br>


**Figure 10. Normalized gate threshold voltage vs temperature** 

**Figure 9. Output capacitance stored energy** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
Eoss AM11250v1<br>(µJ)<br>1.5<br>1<br>0.5<br>0<br>0 100 200 300 400 500 600 VDS(V)<br>**----- End of picture text -----**<br>


**Figure 11. Normalized on resistance vs temperature** 

**==> picture [462 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
VGS(th) AM11252v1 RDS(on) AM11253v1<br>(norm) (norm)<br>2.5<br>1.10<br>ID=250µA<br>ID=2.2A<br>2.1<br>1.00<br>1.7<br>0.90<br>1.3<br>0.80<br>0.9<br>0.70 0.5<br>-50 -25 0 25 50 75 100 TJ(°C) -50 -25 0 25 50 75 100 TJ(°C)<br>**----- End of picture text -----**<br>


**Figure 12. Normalized V(BR)DSS vs temperature** 

**Figure 13. Source-drain diode forward characteristics** 

**==> picture [462 x 177] intentionally omitted <==**

**----- Start of picture text -----**<br>
V(BR)DSS AM11251v1 VSD AM11254v1<br>(norm) (V)<br>1.07 1.4<br>ID=1mA TJ=-50°C<br>1.05 1.2<br>TJ=25°C<br>1.03 1.0<br>1.01 0.8<br>TJ=150°C<br>0.99 0.6<br>0.97 0.4<br>0.95 0.2<br>0.93 0<br>-50 -25 0 25 50 75 100 TJ(°C) 0 0.5 1.0 1.5 2.0 ISD(A)<br>**----- End of picture text -----**<br>


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**Test circuits** 

## **3 Test circuits** 

**Figure 14. Switching times test circuit for resistive load** 

**Figure 15. Gate charge test circuit** 

**==> picture [462 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>12V 47kΩ<br>1kΩ<br>100nF<br>RL 2200 3.3<br>μF μF<br>VDD IG=CONST<br>VD Vi=20V=VGMAX 100Ω D.U.T.<br>VGS<br>2200<br>RG D.U.T. μF 2.7kΩ VG<br>PW<br>47kΩ<br>1kΩ<br>PW<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


**Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test circuit switching and diode recovery times** 

**==> picture [462 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
L<br>A A A<br>D<br>FAST L=100μH VD<br>G D.U.T. DIODE 2200 3.3<br>S B 3.3 1000 μF μF VDD<br>25 Ω B B D μF μF VDD ID<br>G<br>RG S<br>Vi D.U.T.<br>Pw<br>AM01470v1 AM01471v1<br>**----- End of picture text -----**<br>


**Figure 18. Unclamped inductive waveform** 

**Figure 19. Switching time waveform** 

**==> picture [462 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
V(BR)DSS ton toff<br>VD tdon tr tdoff tf<br>90% 90%<br>IDM<br>10%<br>ID 0 10% VDS<br>VDD VDD 90%<br>VGS<br>AM01472v1 0 10% AM01473v1<br>**----- End of picture text -----**<br>


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**Package mechanical data** 

## **4 Package mechanical data** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _www.st.com_ . ECOPACK[®] is an ST trademark. 

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**Package mechanical data** 

## **Figure 20. PowerFLAT™ 3.3 x 3.3 HV drawing** 

**==> picture [121 x 105] intentionally omitted <==**

**==> picture [4 x 3] intentionally omitted <==**

**----- Start of picture text -----**<br>
.<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
8374983_Rev_A<br>**----- End of picture text -----**<br>


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**Package mechanical data** 

**Table 8. PowerFLAT™ 3.3 x 3.3 HV mechanical data** 

|**Dim.**|**mm**|**mm**|**mm**|
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|0.80|0.90|1.00|
|A1|0|0.02|0.05|
|b|0.25|0.30|0.40|
|D||3.30||
|D2|2.50|2.65|2.75|
|E||3.30||
|E2|1.15|1.30|1.40|
|e||0.65||
|L|0.20|0.30|0.40|
|aaa||0.10||
|bbb||0.10||
|ccc||0.10||
|ddd||0.05||
|eee||0.08||



**Figure 21. PowerFLAT™ 3.3 x 3.3 HV recommended footprint (dimensions are in mm)** 

**==> picture [398 x 234] intentionally omitted <==**

**----- Start of picture text -----**<br>
8374983_footprint<br>**----- End of picture text -----**<br>


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**Revision history** 

## **5 Revision history** 

**Table 9. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|12-Mar-2012|1|First release.|
|19-Nov-2014|2|Document status changed from preliminary to production data.<br>Updated_Figure 1.: Internal schematic diagram_,_Figure 2.: Safe_<br>_operating area_,_Figure 3.: Thermal impedance_and_Figure 12.:_<br>_Normalized V(BR)DSS vs temperature_.<br>Updated_Table 5.: Dynamic_and_Table 7.: Source drain diode_.<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2014 STMicroelectronics – All rights reserved 

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