# Power MOSFET, N Channel, 800 V, 1.5 A, 3.7 ohm, PowerFLAT, Surface Mount

![Product image](https://novapart.co/image/farnell:2849656RL/)

**URL**: https://novapart.co/products/STL2N80K5/power-mosfet-n-channel-800-v-15-a-37-ohm-powerflat
**SKU**: STL2N80K5
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.4180
**Stock**: 1000+
**Lead Time**: 2 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:1.5A; Drain Source Voltage Vds:800V; On Resistance Rds(on):3.7ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; P

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | MDmesh K5 |
| Qualification | - |
| Power Dissipation | 33W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | PowerFLAT |
| Drain Source Voltage Vds | 800V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 1.5A |
| Drain Source On State Resistance | 3.7ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2849656RL/)

## **STL2N80K5** 

N-channel 800 V, 3.7 Ω typ., 1.5 A MDmesh™ K5 Power MOSFET in a PowerFLAT™ 5x6 VHV package **Datasheet** - **production data** 

## **Features** 

|**Order code**|**VDS**|**RDS(on)max.**|**ID**|
|---|---|---|---|
|STL2N80K5|800 V|4.5Ω|1.5 A|



- Industry’s lowest RDS(on) 

**==> picture [113 x 49] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>2<br>3<br>4<br>PowerFLAT™ 5x6 VHV<br>**----- End of picture text -----**<br>


- Industry’s best figure of merit (FoM) 

- Ultra low gate charge 

- 100% avalanche tested 

- Zener-protected 

## **Applications** 

## **Figure 1.  Internal schematic diagram** 

**==> picture [214 x 157] intentionally omitted <==**

**----- Start of picture text -----**<br>
D(5, 6, 7, 8) 8 7 6 5<br>G(4)<br>1 2 3 4<br>Top View<br>S(1, 2, 3)<br>AM15540v1<br>**----- End of picture text -----**<br>


- Switching applications 

## **Description** 

This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in onresistance and ultra-low gate charge for applications requiring superior power density and high efficiency. 

**Table 1. Device summary** 

|**Order code**|**Marking**|**Packages**|**Packaging**|
|---|---|---|---|
|STL2N80K5|2N80K5|PowerFLAT™ 5x6 VHV|Tape and reel|



_www.st.com_ 

September 2015 

DocID025104 Rev 3 

1/17 

This is information on a product in full production. 

**Contents** 

**STL2N80K5** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Electrical characteristics (curves)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Test circuits     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9**|
|**4**|**Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10**|
|**5**|**Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14**|
|**6**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|± 30|V|
|ID<br>(1)|Drain current (continuous) at TC= 25 °C|1.5|A|
|ID<br>(1)|Drain current (continuous) at TC= 100 °C|1|A|
|IDM<br>(1),(2)|Drain current (pulsed)|6|A|
|PTOT<br>(1)|Total dissipation at TC= 25 °C|33|W|
|IAR<br>(3)|Avalanche current, repetitive or not-<br>repetitive (pulse width limited by Tjmax)|0.5|A|
|EAS<br>(4)|Single pulse avalanche energy<br>(starting Tj= 25 °C, ID= IAR, VDD= 50 V)|60.5|mJ|
|dv/dt(5)|Peak diode recovery voltage slope|4.5|V/ns|
|dv/dt(6)|MOSFET dv/dt ruggedness|50|V/ns|
|Tstg|Storage temperature|- 55 to 150|°C|
|Tj|Max. operating junction temperature||°C|



1. The value is rated according to Rthj-case and limited by package. 

2. Pulse width limited by safe operating area. 

3. Pulse width limited by Tjmax 

4. Starting Tj=25 °C, ID=IAR, VDD=50 V 

5. ISD ≤ 1.5 A, di/dt ≤ 100 A/µs, VDS(peak) ≤ V(BR)DSS 

6. VDS ≤ 640 V 

**Table 3. Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistance junction-case max|3.7|°C/W|
|Rthj-amb<br>(1)|Thermal resistance junction-amb max|59|°C/W|



1. When mounted on 1inch² FR-4 board, 2 oz Cu. 

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**STL2N80K5** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

**Table 4. On /off states** 

|||**Table 4. On /off states**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|V(BR)DSS|Drain-source<br>breakdown voltage|VGS= 0, ID= 1 mA|800|||V|
|IDSS|Zero gate voltage<br>drain current|VGS= 0, VDS= 800 V|||1|µA|
|||VDS= 800 V, TC=125 °C|||50|µA|
|IGSS|Gate-body leakage<br>current|VDS= 0, VGS= ± 20 V|||± 10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 100 µA|3|4|5|V|
|RDS(on)|Static drain-source<br>on- resistance|VGS= 10 V, ID= 1 A||3.7|4.5|Ω|



**Table 5. Dynamic** 

|||**Table 5. Dynamic**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|Ciss|Input capacitance|VGS= 0, VDS= 100 V,<br>f = 1 MHz|-|105|-|pF|
|Coss|Output capacitance||-|8|-|pF|
|Crss|Reverse transfer<br>capacitance||-|0.5|-|pF|
|Co(tr)<br>(1)|Equivalent<br>capacitance time<br>related|VGS= 0, VDS= 0 to 640 V|-|16|-|pF|
|Co(er)<br>(2)|Equivalent<br>capacitance energy<br>related||-|7|-|pF|
|RG|Intrinsic gate<br>resistance|f = 1 MHz, ID=0|-|18|-|Ω|
|Qg|Total gate charge|VDD= 640 V, ID= 2 A,<br>VGS= 10 V<br>(see_Figure 16_)|-|5|-|nC|
|Qgs|Gate-source charge||-|1|-|nC|
|Qgd|Gate-drain charge||-|3.7|-|nC|



1. Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

2. Coss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 

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**Electrical characteristics** 

**Table 6. Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 400 V, ID= 1 A,<br>RG= 4.7Ω, VGS= 10 V<br>(see_Figure 15_),<br>(see_Figure 20_)|-|8|-|ns|
|tr|Rise time||-|12|-|ns|
|td(off)|Turn-off delay time||-|19|-|ns|
|tf|Fall time||-|32|-|ns|



**Table 7. Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||1.5|A|
|ISDM|Source-drain current (pulsed)||-||6|A|
|VSD<br>(1)|Forward on voltage|VGS= 0, ISD= 2 A|-||1.5|V|
|trr|Reverse recovery time|ISD= 2 A, di/dt = 100 A/µs<br>VDD= 60 V (see_Figure 17_)|-|255||ns|
|Qrr|Reverse recovery charge||-|1||µC|
|IRRM|Reverse recovery current||-|8||A|
|trr|Reverse recovery time|ISD= 2 A, di/dt = 100 A/µs<br>VDD= 60 V, Tj= 150 °C<br>(see_Figure 17_)|-|285||ns|
|Qrr|Reverse recovery charge||-|1.45||µC|
|IRRM|Reverse recovery current||-|7.5||A|



1. Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

**Table 8. Gate-source Zener diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min**|**Typ.**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)GSO|Gate-source breakdown voltage|IGS= ± 1mA, ID=0|30|-|-|V|



The built-in back-to-back Zener diodes have specifically been designed to enhance the device's ESD capability. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2. Safe operating area** 

## **Figure 3. Thermal impedance** 

**==> picture [187 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
ZthPowerFlat_5x6_27<br>K<br>δ=0.5<br>SE Sass<br>0.2<br>10 [-1] 0.1<br>—f<br>fp 0.05<br>WAWf 0.01 0.02 case<br>Zt h = k Rens-<br>10 [-2]<br>5= te/T<br>Single pulse<br>elT |<br>10 [-3]<br>10 [-5] 10 -4 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1] tp(s)<br>**----- End of picture text -----**<br>


**Figure 4. Output characteristics** 

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**----- Start of picture text -----**<br>
AM18075v1<br>ID(A) VGS=10, 11V<br>3.0<br>2.5<br>9V<br>2.0<br>1.5<br>8V<br>1.0<br>0.5 7V<br>6V<br>0.0<br>0 2 4 6 8 10 12 14 16 VDS(V)<br>**----- End of picture text -----**<br>


## **Figure 5. Transfer characteristics** 

**==> picture [194 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM18085v1<br>ID<br>(A)<br>VDS=20V<br>3<br>2.5<br>2<br>1.5<br>1<br>0.5<br>0<br>5 6 7 8 9 10 VGS(V)<br>**----- End of picture text -----**<br>


**Figure 6. Gate charge vs gate-source voltage** 

**==> picture [195 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
VGS AM18076v1<br>(V) VDS<br>VDD = 640 V (V)<br>14 700<br>VDS ID = 2 A<br>12 600<br>10 500<br>8 400<br>6 300<br>4 200<br>2 100<br>0 0<br>0 1 2 3 4 5 6 Qg(nC)<br>**----- End of picture text -----**<br>


**Figure 7. Static drain-source on-resistance** 

**==> picture [203 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM18077v1<br>RDS(on)<br>(Ω)<br>VGS=10V<br>6<br>4<br>2<br>0<br>0.0 0.5 1.0 1.5 2.0 2.5 ID(A)<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

**Figure 8. Capacitance variations** 

## **Figure 9. Output capacitance stored energy** 

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**----- Start of picture text -----**<br>
C AM18078v1 Eoss AM18079v1<br>(pF) (μJ)<br>f = 1MHz<br>100<br>100 Ciss<br>2<br>10<br>Coss<br>Crss<br>1<br>0.1 0<br>0.1 1 10 100 VDS(V) 0 200 400 600 800 VDS(V)<br>Figure 10. Normalized gate threshold voltage vs  Figure 11. Normalized on-resistance vs<br>temperature temperature<br>VGS(th) AM18082v1 AM18081v1<br>(norm) RDS(on)<br>1.2 ID=100 μA (norm) ID=1 A<br>VGS=10 V<br>1.1 2.5<br>1<br>2<br>0.9<br>1.5<br>0.8<br>0.7<br>1<br>0.6<br>0.5<br>0.5<br>0.4 0<br>-100 -50 0 50 100 150 TJ(°C) -100 -50 0 50 100 150 TJ(°C)<br>**----- End of picture text -----**<br>


**Figure 12. Normalized V(BR)DSS vs temperature** 

**Figure 13. Source-drain diode forward characteristics** 

**==> picture [462 x 177] intentionally omitted <==**

**----- Start of picture text -----**<br>
V(BR)DSS(norm) AM18083v1 VSD(V) AM18084v1<br>ID=1mA TJ=-50°C<br>1.1 1<br>1.05 0.9 TJ=25°C<br>1 0.8<br>0.95 0.7 T J =150°C<br>0.9 0.6<br>0.85 0.5<br>-100 -50 0 50 100 TJ(°C) 0 0.5 1 1.5 2 ISD(A)<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

**Figure 14. Maximum avalanche energy vs starting TJ** 

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**Test circuits** 

## **3 Test circuits** 

**Figure 15. Switching times test circuit for resistive load** 

**Figure 16. Gate charge test circuit** 

**==> picture [462 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>12V 47kΩ<br>1kΩ<br>100nF<br>RL 2200 3.3<br>μF μF<br>VDD IG=CONST<br>VD Vi=20V=VGMAX 100Ω D.U.T.<br>VGS<br>2200<br>RG D.U.T. μF 2.7kΩ VG<br>PW<br>47kΩ<br>1kΩ<br>PW<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


**Figure 17. Test circuit for inductive load Figure 18. Unclamped inductive load test circuit switching and diode recovery times** 

**==> picture [462 x 346] intentionally omitted <==**

**----- Start of picture text -----**<br>
L<br>A A A<br>D<br>FAST L=100μH VD<br>G D.U.T. DIODE 2200 3.3<br>S B 3.3 1000 μF μF VDD<br>25 Ω B B D μF μF VDD ID<br>G<br>RG S<br>Vi D.U.T.<br>Pw<br>AM01470v1 AM01471v1<br>Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform<br>V(BR)DSS ton toff<br>VD tdon tr tdoff tf<br>90% 90%<br>IDM<br>10%<br>ID 0 10% VDS<br>VDD VDD 90%<br>VGS<br>AM01472v1 0 10% AM01473v1<br>**----- End of picture text -----**<br>


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**Package mechanical data** 

## **4 Package mechanical data** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _www.st.com_ . ECOPACK[®] is an ST trademark. 

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**Package mechanical data** 

## **Figure 21. PowerFLAT™ 5x6 VHV** 

**==> picture [399 x 560] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bottom view<br>Side view<br>Top view<br>8368144_REV_B<br>**----- End of picture text -----**<br>


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**Package mechanical data** 

**Table 9. PowerFLAT™ 5x6 VHV mechanical data** 

|**DIM**|**mm.**|**mm.**|**mm.**|
|---|---|---|---|
||**min.**|**typ.**|**max.**|
|A|0.80||1.00|
|A1|0.02||0.05|
|A2||0.25||
|b|0.30||0.50|
|D|5.00|5.20|5.40|
|E|5.95|6.15|6.35|
|D2|4.30|4.40|4.50|
|E2|2.40|2.50|2.60|
|e||1.27||
|L|0.50|0.55|0.60|
|K|2.60|2.70|2.80|
|aaa||0.15||
|bbb||0.15||
|ccc||0.10||
|eee||0.10||



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**Package mechanical data** 

## **Figure 22. PowerFLAT™ 5x6 VHV (dimensions are in mm)** 

**==> picture [397 x 435] intentionally omitted <==**

**----- Start of picture text -----**<br>
8368144_REV_B_footprint<br>**----- End of picture text -----**<br>


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**Packaging mechanical data** 

## **5 Packaging mechanical data** 

## **Figure 23. PowerFLAT™ 5x6 tape** 

**==> picture [405 x 257] intentionally omitted <==**

**----- Start of picture text -----**<br>
P 2 P 0<br>(0.30 T ±0.05) Do 2.0±0.1 (I) 4.0±0.1 (II) E1<br>Ø1.55±0.05 Y 1.75±0.1<br>D1<br>Ø1.5 MIN.<br>CL<br>Y<br>P1(8.00±0.1) Ao(6.30±0.1)<br>Ko (1.20±0.1)<br>SECTION Y-Y<br>(I) Measured from centerline of sprocket holeto centerline of pocket. Base and bulk quantity 3000 pcs<br>All dimensions are in millimeters<br>(II) Cumulative tolerance of 10 sprocket<br>holes is ± 0.20 .<br>(III) Measured from centerline of sprocket<br>hole to centerline of pocket.<br>8234350_Tape_rev_C<br>REF.R0.50<br>REF 0.20<br>))((IIIF5.50±0.1 )(W12.00±0.3<br>5.30±0.1)(Bo<br>**----- End of picture text -----**<br>


**Figure 24. PowerFLAT™ 5x6 package orientation in carrier tape.** 

**==> picture [390 x 144] intentionally omitted <==**

**----- Start of picture text -----**<br>
Pin 1<br>identification<br>**----- End of picture text -----**<br>


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**Packaging mechanical data** 

**==> picture [158 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 25. PowerFLAT™ 5x6 reel<br>**----- End of picture text -----**<br>


**==> picture [405 x 256] intentionally omitted <==**

**----- Start of picture text -----**<br>
R0.60<br>W3<br>PART NO. 11.9/15.4<br>1 .90<br>2.50<br>W2<br>18.4 (max)<br>R25.00<br>   ØN    A<br>4.00 178(±2.0) 330 (+0/-4.0)<br>2.50<br>ESD LOGO<br>W1<br>12.4 (+2/-0)<br>ØA<br>R1.10<br>Ø21.2<br>All dimensions are in millimeters<br>13.00<br>CORE DETAIL<br>8234350_Reel_rev_C<br>128<br>77<br>ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES<br>2.20<br>06PS<br>**----- End of picture text -----**<br>


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**Revision history** 

## **6 Revision history** 

**Table 10. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|09-Aug-2013|1|First release.|
|24-Jul-2014|2|– Modified: title<br>– Modified: Features table<br>– Modified: ID, IDM, PTOT, IAR, EASvalues and note_5_in_Table 2_<br>– Modified: Rthj-casevalue in_Table 3_<br>– Modified: RDS(on)values in_Table 4_<br>– Modified: the entire typical values in_Table 5_, 6 and 7<br>– Added:_Section 2.1: Electrical characteristics (curves)_<br>– Minor text changes.|
|25-Sep-2015|3|– Updated title in cover page.<br>– Updated_Figure 6_,_Figure 7_and_Figure 8_.<br>– Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2015 STMicroelectronics – All rights reserved 

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## Links

- [View this product on Novapart](https://novapart.co/products/STL2N80K5/power-mosfet-n-channel-800-v-15-a-37-ohm-powerflat)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/stmicroelectronics/stl2n80k5/mosfet-n-ch-800v-1-5a-powerflat/dp/2849656RL)
---

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