# Power MOSFET, N Channel, 80 V, 95 A, 5600 µohm, PowerFLAT, Surface Mount

![Product image](https://novapart.co/image/farnell:3775643/)

**URL**: https://novapart.co/products/STL105N8F7AG/power-mosfet-n-channel-80-v-95-a-5600-ohm
**SKU**: STL105N8F7AG
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.6110
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | STripFET F7 |
| Qualification | AEC-Q101 |
| Power Dissipation | 127W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | PowerFLAT |
| Drain Source Voltage Vds | 80V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 95A |
| Drain Source On State Resistance | 5600µohm |
| Gate Source Threshold Voltage Max | 4.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3775643/)

**STL105N8F7AG** 

Datasheet 

Automotive N-channel 80 V, 5.6 mΩ typ., 95 A, STripFET F7 Power MOSFET in a PowerFLAT 5x6 package 

## **Features** 

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4<br>3<br>NU 2<br>1<br>PowerFLAT 5x6<br>**----- End of picture text -----**<br>


|**Order code**<br>**VDS**<br>STL105N8F7AG<br>80 V<br>AEC-Q101 qualified<br>~~a~~<br>oo|**RDS(on) max.**<br>6.5 mΩ<br>~~a~~|**ID**<br>95 A|
|---|---|---|



- AEC-Q101 qualified 

- Among the lowest RDS(on) on the market 

- Excellent FoM (figure of merit) 

- Low Crss/Ciss ratio for EMI immunity 

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D(5, 6, 7, 8) 8 7 6 5<br>G(4)<br>1 2 3 4<br>S(1, 2, 3) Top View<br>AM15540v2<br>**----- End of picture text -----**<br>


- High avalanche ruggedness 

- Wettable flank package 

## **Applications** 

- Switching applications 

## **Description** 

This N-channel Power MOSFET utilizes STripFET F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. 

## **Product status link** ~~EEE~~ 

|**Product summary**<br>~~a~~|**Product summary**<br>~~a~~|
|---|---|
|**Order code**|STL105N8F7AG|
|**Marking**|105N8F7|
|**Package**|PowerFLAT 5x6|
|**Packing**|Tape and reel|



**DS13615** - **Rev 2** - **March 2021** For further information contact your local STMicroelectronics sales office. 

www.st.com 

**STL105N8F7AG Electrical ratings** 

## **1 Electrical ratings** 

**Table 1. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|80|V|
|VGS|Gate-source voltage|±20|V|
|ID|Drain current (continuous) at TC= 25 °C|95|A|
||Drain current (continuous) at TC= 100 °C|68||
|IDM(1)|Drain current (pulsed)|380|A|
|PTOT|Total power dissipation at TC= 25 °C|127|W|
|IAV|Avalanche current, repetitive or not repetitive<br>(pulse width limited by maximum junction temperature)|40|A|
|EAS|Single pulse avalanche energy<br>(TJ= 25 °C, ID= IAV, VDD= 60 V, RGmin = 47 Ω)|135|mJ|
|TJ|Operating junction temperature range|-55 to 175|°C|
|Tstg|Storage temperature range||°C|



_1. Pulse width limited by safe operating area._ 

**Table 2. Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|RthJC|Thermal resistance, junction-to-case|1.18|°C/W|
|RthJB(1)|Thermal resistance, junction-to-board|31.3|°C/W|



_1. When mounted on an FR-4 board of 1 inch², 2oz Cu, t < 10s._ 

**DS13615** - **Rev 2** 

**page 2/14** 

**STL105N8F7AG Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

**Table 3. On/off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown voltage|ID= 250 μA, VGS= 0 V|80|||V|
|IDSS|Zero gate voltage drain current|VGS= 0 V, VDS= 80 V|||1|µA|
|IGSS|Gate-body leakage current|VGS= 20 V, VDS= 0 V|||100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 μA|2.5||4.5|V|
|RDS(on)|Static drain-source on-resistance|VGS= 10 V, ID= 25 A||5.6|6.5|mΩ|



**Table 4. Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 25 V, f = 1 MHz, VGS= 0 V|-|3475|-|pF|
|Coss|Output capacitance||-|904|-|pF|
|Crss|Reverse transfer capacitance||-|88|-|pF|
|Qg|Total gate charge|VDD= 40 V, ID= 95 A,<br>VGS= 0 to 10 V<br>(seeFigure 13. Test circuit for gate<br>charge behavior)|-|46|-|nC|
|Qgs|Gate-source charge||-|24|-|nC|
|Qgd|Gate-drain charge||-|10|-|nC|



**Table 5. Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 40 V, ID= 50 A,<br>RG= 4.7 Ω, VGS= 10 V<br>(seeFigure 12. Test circuit for<br>resistive load switching times<br>andFigure 17. Switching time<br>waveform)|-|19|-|ns|
|tr|Rise time||-|22|-|ns|
|td(off)|Turn-off delay time||-|31|-|ns|
|tf|Fall time||-|13|-|ns|



**Table 6. Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||||95|A|
|VSD(1)|Source-drain voltage|ISD= 95 A, VGS= 0 V|-||1.2|V|
|trr|Reverse recovery time|ISD= 50 A, di/dt = 100 A/µs,<br>VDD= 64 V<br>(seeFigure 14. Test circuit for<br>inductive load switching and diode<br>recovery times)|-|37||ns|
|Qrr|Reverse recovery charge||-|37||nC|
|IRRM|Reverse recovery current||-|1.5||A|



_1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%._ 

**DS13615** - **Rev 2** 

**page 3/14** 

**STL105N8F7AG Electrical characteristics (curves)** 

## **2.1 Electrical characteristics (curves)** 

**==> picture [513 x 195] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 1. Safe operating area Figure 2. Maximum transient thermal impedance<br>ID GADG211220201122SOA K  GADG211220201122ZTH<br>(A)<br>δ = 0.5<br>10  [2 ]<br>0.2<br>tp =10 µs 0.1<br>10  [1 ]<br>tp =100 µs 10  [-1 ]<br>0.02 0.05<br>10  [0 ]<br>tp =1 ms 0.01<br>10  [-1 ] TJ ≤ 175 °C tp =10 ms Single pulse<br>TC = 25°C<br>10  [-2 ] Single pulse 10  [-2 ]<br>10  [-1 ] 10  [0 ] 10  [1 ] VDS (V) 10  [-5 ] 10  [-4 ] 10  [-3 ] 10  [-2 ] 10  [-1 ] tp (s)<br>Operation in this area<br>is limited by R DS(on)<br>**----- End of picture text -----**<br>


**==> picture [513 x 194] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 3. Typical output characteristics Figure 4. Typical transfer characteristics<br>ID GADG211220201123OCH ID GADG211220201124TCH<br>(A)  (A)<br>160 VGS = 8, 9, 10 V<br>100<br>140 VDS = 6 V<br>7 V<br>120 80<br>100<br>60<br>80 TJ = 175 °C<br>60 40<br>6 V TJ = 25 °C<br>40<br>20<br>20 TJ = -55 °C<br>5 V<br>0 0<br>0 1 2 3 4 5 6 7 8 9 VDS (V) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VGS (V)<br>**----- End of picture text -----**<br>


**==> picture [513 x 195] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 5. Typical gate charge characteristics Figure 6. Typical drain-source on-resistance<br>VGS GADG040120210949QVG RDS(on) GADG040120210950RID<br>(V)  (mΩ)<br>6.6<br>12<br>6.4<br>10 VDS = 40 V<br>ID = 95 A 6.2<br>8 6.0<br>6 5.8 VGS = 10 V<br>5.6<br>4<br>5.4<br>2<br>5.2<br>0 5.0<br>0 10 20 30 40 50 Qg (nC) 0 10 20 30 40 50 60 70 80 90 ID (A)<br>**----- End of picture text -----**<br>


**DS13615** - **Rev 2** 

**page 4/14** 

**STL105N8F7AG Electrical characteristics (curves)** 

**==> picture [513 x 205] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 8. Normalized gate threshold voltage vs<br>Figure 7. Typical capacitance characteristics<br>temperature<br>C  GADG211220201127CVR<br>(pF)  VGS(th) GADG211220201139VTH<br>(norm.)<br>Ciss 1.15<br>1.05<br>10  [3 ] ID = 250 µA<br>0.95<br>Coss<br>0.85<br>f = 1 MHz<br>10  [2 ] 0.75<br>0.65<br>Crss<br>0.55<br>10  [1 ]<br>10 [-1] 10 [0] 10 [1] VDS (V) 0.45<br>-75 -25 25 75 125 175 TJ (°C)<br>**----- End of picture text -----**<br>


## **Figure 9. Normalized on-resistance vs temperature Figure 10. Normalized V(BR)DSS vs temperature** 

**==> picture [456 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
RDS(on) GADG211220201145RON V(BR)DSS GADG211220201145BDV<br>(norm.)  (norm.)<br>2.1<br>1.06<br>1.9 VGS = 10 V 1.04 ID = 250 µA<br>1.7 I D  = 25 A<br>1.02<br>1.5<br>1.3 1.00<br>1.1<br>0.98<br>0.9<br>0.96<br>0.7<br>0.94<br>0.5<br>0.3 0.92<br>-75 -25 25 75 125 175 TJ (°C) -75 -25 25 75 125 175 TJ (°C)<br>**----- End of picture text -----**<br>


## **Figure 11. Typical reverse diode forward characteristics** 

**==> picture [185 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
VSD GADG211220201146SDF<br>(V)<br>1.1<br>1.0<br>TJ = -55 °C<br>0.9 TJ = 25 °C<br>0.8<br>TJ = 175 °C<br>0.7<br>0.6<br>0.5<br>0.4<br>10 20 30 40 50 60 70 80 ISD (A)<br>**----- End of picture text -----**<br>


**DS13615** - **Rev 2** 

**page 5/14** 

**STL105N8F7AG Test circuits** 

## **3 Test circuits** 

**==> picture [513 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior<br>VDD<br>12 V 47 kΩ<br>1 kΩ<br>100 nF<br>RL 2200 3.3<br>+ μF μF VDD<br>VD VGS IG= CONST 100 Ω D.U.T.<br>VGS RG D.U.T. pulse width 2200 + 2.7 kΩ VG<br>pulse width μF<br>47 kΩ<br>1 kΩ<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


**==> picture [513 x 183] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 14. Test circuit for inductive load switching and<br>Figure 15. Unclamped inductive load test circuit<br>diode recovery times<br>A A A L<br>G D D.U.T. fastdiode 100 µH VD 2200 3.3<br>25 Ω S B B B D µF3.3 + 1000µF VDD ID + µF µF VDD<br>G D.U.T.<br>+ RG S Vi D.U.T.<br>_ pulse width<br>AM01471v1<br>AM01470v1<br>**----- End of picture text -----**<br>


**Figure 16. Unclamped inductive waveform** 

**==> picture [177 x 123] intentionally omitted <==**

**----- Start of picture text -----**<br>
V(BR)DSS<br>VD<br>IDM<br>ID<br>VDD VDD<br>AM01472v1<br>**----- End of picture text -----**<br>


**Figure 17. Switching time waveform** 

**==> picture [182 x 142] intentionally omitted <==**

**----- Start of picture text -----**<br>
ton toff<br>td(on) tr td(off) tf<br>90% 90%<br>0 10% VDS 10%<br>VGS 90%<br>0 10%<br>AM01473v1<br>**----- End of picture text -----**<br>


**DS13615** - **Rev 2** 

**page 6/14** 

**STL105N8F7AG Package information** 

## **4** 

## **Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 

## **4.1 PowerFLAT 5x6 WF type C package information** 

## **Figure 18. PowerFLAT 5x6 WF type C package outline** 

**==> picture [55 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
8231817_WF_typeC_r20<br>**----- End of picture text -----**<br>


**DS13615** - **Rev 2** 

**page 7/14** 

**STL105N8F7AG PowerFLAT 5x6 WF type C package information** 

**Table 7. PowerFLAT 5x6 WF type C mechanical data** 

|**Di**|**mm**|**mm**|**mm**|
|---|---|---|---|
|**m.**|**Min.**|**Typ.**|**Max.**|
|A|0.80||1.00|
|A1|0.00||0.05|
|A2||0.25||
|b|0.30||0.50|
|C|5.80|6.00|6.10|
|D|5.00|5.20|5.40|
|D2|4.15||4.45|
|D3|4.05|4.20|4.35|
|D4|4.80|5.00|5.10|
|D5|0.25|0.40|0.55|
|D6|0.15|0.30|0.45|
|e||1.27||
|E|6.20|6.40|6.60|
|E2|3.50||3.70|
|E3|2.35||2.55|
|E4|0.40||0.60|
|E5|0.08||0.28|
|E6|0.20|0.325|0.45|
|E7|0.85|1.00|1.15|
|E9|4.00|4.20|4.40|
|E10|3.55|3.70|3.85|
|K|1.05||1.35|
|L|0.90|1.00|1.10|
|L1|0.175|0.275|0.375|
|θ|0°||12°|



**DS13615** - **Rev 2** 

**page 8/14** 

**STL105N8F7AG PowerFLAT 5x6 WF type C package information** 

**Figure 19. PowerFLAT 5x6 recommended footprint (dimensions are in mm)** 

**==> picture [187 x 168] intentionally omitted <==**

8231817_FOOTPRINT_rev20 

**DS13615** - **Rev 2** 

**page 9/14** 

**STL105N8F7AG PowerFLAT 5x6 WF packing information** 

## **4.2 PowerFLAT 5x6 WF packing information** 

## **Figure 20. PowerFLAT 5x6 WF tape (dimensions are in mm)** 

**==> picture [384 x 133] intentionally omitted <==**

**----- Start of picture text -----**<br>
T0.30 0.05 Do1.50 +0.10.0 2.0P2 0.05(I) Po4.0 0.1(II) 1.75E1 0.1<br>Y<br>D1<br>1.50 MIN<br>R0.30<br>MAX<br>Y<br>Ko (1.20±0.1) P1(8.00±0.1) Ao(6.70±0.1)<br>SECTION Y-Y<br>F(5.50±0.0.05)(III)<br>W(12.00±0.1)<br>Bo (5.35±0.05)<br>**----- End of picture text -----**<br>


- (I) Measured from centreline of sprocket hole to centreline of pocket. 

- (II) Cumulative tolerance of 10 sprocket holes is ± 0.20 . Base and bulk qua ntity 3000 pcs 

- (III) Measured from centreline of sprocket hole to centreline of pocket. 

**==> picture [63 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
8234350_TapeWF_rev_C<br>**----- End of picture text -----**<br>


**Figure 21. PowerFLAT 5x6 package orientation in carrier tape** 

**==> picture [32 x 12] intentionally omitted <==**

**----- Start of picture text -----**<br>
Pin 1<br>identification<br>**----- End of picture text -----**<br>


**==> picture [338 x 126] intentionally omitted <==**

**DS13615** - **Rev 2** 

**page 10/14** 

**STL105N8F7AG PowerFLAT 5x6 WF packing information** 

## **Figure 22. PowerFLAT 5x6 reel (dimensions are in mm)** 

**==> picture [380 x 216] intentionally omitted <==**

**----- Start of picture text -----**<br>
R0.60<br>W3<br>PART NO. 11.9/15.4<br>1 .90<br>2.50<br>W2<br>18.4 (max)<br>R25.00<br>∅ 4.00    ØN 178(±2.0)    A330 (+0/-4.0)<br>∅ 2.50<br>ESD LOGO<br>W1<br>12.4 (+2/-0)<br>ØA<br>R1.10<br>Ø21.2<br>All dimensions are in millimeters<br>∅ 13.00<br>CORE DETAIL 8234350_Reel_rev_C<br>128<br>77<br>ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES<br>2.20<br>06PS<br>**----- End of picture text -----**<br>


**DS13615** - **Rev 2** 

**page 11/14** 

**STL105N8F7AG** 

## **Revision history** 

**Table 8. Document revision history** 

|**Date**|**Version**|**Changes**|
|---|---|---|
|04-Jan-2021|1|First release.|
|08-Mar-2021|2|UpdatedTable 1. Absolute maximum ratings.|



**DS13615** - **Rev 2** 

**page 12/14** 

**STL105N8F7AG Contents** 

## **Contents** 

|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2**|
|---|---|
|**2**|**Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3**|
||**2.1**<br>Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|**3**|**Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6**|
|**4**|**Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7**|
||**4.1**<br>PowerFLAT 5x6 WF type C package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
||**4.2**<br>PowerFLAT 5x6 WF packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10|
|**Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12**||



**DS13615** - **Rev 2** 

**page 13/14** 

**STL105N8F7AG** 

## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2021 STMicroelectronics – All rights reserved 

**DS13615** - **Rev 2** 

**page 14/14** 



## Links

- [View this product on Novapart](https://novapart.co/products/STL105N8F7AG/power-mosfet-n-channel-80-v-95-a-5600-ohm)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/stmicroelectronics/stl105n8f7ag/mosfet-n-ch-80v-95a-powrflat/dp/3775643)
---

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