# Intelligent Power Module (IPM), IGBT, 600 V, 15 A, 2000 Vrms, SIP

![Product image](https://novapart.co/image/farnell:2677190/)

**URL**: https://novapart.co/products/STK57FU394AG-E/intelligent-power-module-ipm-igbt-600-v-15-a-2000
**SKU**: STK57FU394AG-E
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || Intelligent Power Modules
**Price**: €9.8800
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| Current Rating (Ic / Id) | 15A |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2677190/)

## **STK57FU394AG-E** 

## **2-in-1 PFC and Inverter Intelligent Power Module (IPM), 600 V, 15 A** 

The STK57FU394AG-E is a fully-integrated PFC and inverter power stage consisting of a high-voltage driver, six motor drive IGBT’s, one PFC IGBT, one PFC rectifier and a thermistor, suitable for driving permanent magnet synchronous (PMSM) motors, brushless-DC (BLDC) motors and AC asynchronous motors. 

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## **PACKAGE PICTURE** 

The IGBT’s are configured in a 3-phase bridge with separate emitter connections for the lower legs for maximum flexibility in the choice of control algorithm. 

An internal comparator and reference connected to the over-current protection circuit allows the designer to set individual over-current protection levels for the PFC and the inverter stages. Additionally, the power stage has a full range of protection functions including crossconduction protection, external shutdown and under-voltage lockout functions. 

## **Features** 

- Simple thermal design with PFC and inverter stage in one package. 

- PFC operating frequency up to 40kHz 

SIP35 56x25.8 / SIP2A-3 

- Cross-conduction protection 

- Adjustable over-current protection level 

## **MARKING DIAGRAM** 

- Integrated bootstrap diodes and resistors 

## **Certification** 

- UL1557 (File Number : E339285) 

## **Typical Applications** 

- Heat Pumps 

- Home Appliances 

- Industrial Fans 

- Industrial Pumps 

**==> picture [265 x 139] intentionally omitted <==**

**----- Start of picture text -----**<br>
HINU HS1<br>LINU Three channel LS1<br>half-bridge HS1 HS2 HS3<br>HINV driver  HS2<br>+<br>LINV single-ended LS2<br>PFC driver<br>HINW HS3<br>with<br>LINW protection LS3<br>circuits LS1 LS2 LS3<br>PFCIN<br>VBU VBV VBW VDD GND TH PFCL VP U V W<br>ITRIP PTRIP FLTEN HVGND NU NV NW<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
A B C D D<br>STK5 7FU3 9 4AG<br>4 8 12 16 20 22 24 26 28 30 32 34<br>1 5 9 13 19 21 23 25 27 29 31 33 35<br>**----- End of picture text -----**<br>


STK57FU394AG = Specific Device Code A = Year 

B = Month 

C = Production Site DD = Factory Lot Code Device marking is on package top side 

## **ORDERING INFORMATION** 

|||Shipping|
|---|---|---|
|Device|Package|Shipping<br>(Qty/ Packing)|
|STK57FU394AG-E|SIP35 56x25.8<br>/ SIP2A-3<br>(Pb-Free)|8 / Tube|



**Figure 1. Functional Diagram** 

**1** 

Publication Order Number: **STK57FU394AG-E/D** 

© Semiconductor Components Industries, LLC, 2016 **June 2016 - Rev. 0** 

**STK57FU394AG-E** 

**==> picture [480 x 394] intentionally omitted <==**

**----- Start of picture text -----**<br>
STK57FU394<br>PFCL (1)<br>RC filtering for<br>VP (16) HINx, LINx and<br>+ From Op-amp  PFCIN not<br>C1 CS<br>circuit shown.<br>PTRIP (31) Recommended<br>RSPFC<br>in noisy<br>HVGND (19) ITRIP (32)<br>RSU environments.<br>From HV<br>NU (22)<br>Power<br>Source HINU (23)<br>RSV<br>To Op-amp  NV (21) HINV (24)<br>circuit HINW (25)<br>RSW<br>NW (20) LINU (26)<br>To Op-amp  LINV (27)<br>circuit LINW (28)<br>PFCIN (29)<br>VBU (12)<br>+<br>U (13) RP RTH Controller<br>VBV (8)<br>+ FLTEN (30)<br>Motor V (9) TH (33)<br>VDD Supply<br>VBW (4) VDD (34)<br>+ +<br>W (5) GND (35)<br>From 15V<br>Power<br>LV Ground Source<br>**----- End of picture text -----**<br>


**Figure 2. Application Schematic** 

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**2** 

**STK57FU394AG-E** 

**==> picture [481 x 516] intentionally omitted <==**

**----- Start of picture text -----**<br>
PFCL (1)<br>DB RBS<br>VBU (12)<br>DB RBS<br>VBV (8)<br>DB RBS<br>VBW (4)<br>RBC<br>VDD (34) VP (16)<br>GND (35)<br>W (5)<br>PFC V (9)<br>PFCIN(29) Driver U (13)<br>HVGND (19)<br>NU (22)<br>NV (21)<br>NW (20)<br>Level  Level  Level<br>Shifter Shifter Shifter<br>HINU (23)<br>HINV (24)<br>HINW (25)<br>Logic Logic Logic<br>LINU (26)<br>LINV (27)<br>LINW (28)<br>TH (33) VDD<br>VDD undervoltage<br>shutdown<br>FLTEN (30)<br>ITRIP (32)<br>VITRIP<br>Reset after<br>delay<br>PTRIP (31)<br>VPFCTRIP<br>**----- End of picture text -----**<br>


**Figure 3. Simplified Block Diagram** 

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**3** 

**STK57FU394AG-E** 

## **PIN FUNCTION DESCRIPTION** 

|Pin|Name|Description|
|---|---|---|
|1|PFCL|PFC Inductor Connection to IGBT and Rectifier node|
|4|VBW|High Side Floating Supply voltage for W phase|
|5|W|V phase output. Internally connected to W phase high side driver ground|
|8|VBV|High Side Floating Supply voltage for V phase|
|9|V|V phase output. Internally connected to V phase high side driver ground|
|12|VBU|High Side Floating Supply voltage for U phase|
|13|U|U phase output. Internally connected to U phase high side driver ground|
|16|VP|Positive PFC Output Voltage|
|19|HVGND|Negative PFC Output Voltage|
|20|NW|Low Side Emitter Connection - Phase W|
|21|NV|Low Side Emitter Connection - Phase V|
|22|NU|Low Side Emitter Connection - Phase U|
|23|HINU|Logic Input High Side Gate Driver - Phase U|
|24|HINV|Logic Input High Side Gate Driver - Phase V|
|25|HINW|Logic Input High Side Gate Driver - Phase W|
|26|LINU|Logic Input Low Side Gate Driver - Phase U|
|27|LINV|Logic Input Low Side Gate Driver - Phase V|
|28|LINW|Logic Input Low Side Gate Driver – Phase W|
|29|PFCIN|Logic Input PFC Gate Driver|
|30|FLTEN|Bidirectional FAULT output and ENABLE input|
|31|PTRIP|Current protection pin for PFC|
|32|ITRIP|Current protection pin for inverter|
|33|TH|Thermistor output|
|34|VDD|+15V Main Supply|
|35|GND|Negative Main Supply|



Note: Pins 2, 3, 6, 7, 10, 11, 14, 15, 17 and 18 are not present 

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**4** 

## **STK57FU394AG-E** 

**ABSOLUTE MAXIMUM RATINGS** (Notes 1, 2) Tc=25C unless otherwise noted. 

|**ABSOLUTE MAXIMUM RATINGS **(N<br>Tc=25C unless otherwise noted.|**ABSOLUTE MAXIMUM RATINGS **(N<br>Tc=25C unless otherwise noted.|otes 1, 2)||||
|---|---|---|---|---|---|
|**Rating**||**Symbol**|**Conditions**|**Value**|**Unit**|
|**PFC Section**||||||
|PFC<br>IGBT|Collector-emitter voltage|VCE|PFCL to HVGND|600|V|
||Repetitive peak collector current|ICP|Duty cycle 10%, pulse width 1ms|72|A|
||Collector current|IC||36|A|
||||Tc=100C|18|A|
||Maximum power dissipation|PC||73|W|
|PFC<br>Diode|Diode reverse voltage|VRM|VP to PFCL|600|V|
||Repetitive peak forward current|IFP1|Duty cycle 10%, pulse width 1ms|60|A|
||Diode forward current|IF1||30|A|
||||Tc=100C|15|A|
||Maximum power dissipation|PD1||56|W|
|Anti-<br>parallel<br>Diode|Repetitive peak forward current|IFP2|Duty cycle 10%, pulse width 1ms|11|A|
||Diode forward current|IF2||5|A|
||Maximum power dissipation|PD2||10|W|
|Maximum AC input voltage||VAC|Single-phase Full-rectified|264|V|
|Maximum output voltage||Vo|In the Application Circuit<br>(VAC=200V)|450|V|
|Input AC current (steady state)||Iin||15|Arms|
|**Inverter Section**||||||
|Supply voltage||VCC|VP to NU, NV, NW surge < 500V<br>(Note 3)|450|V|
|Collector-emitter voltage||VCE max|VP to U, V, W or U to NU, V to NV, W<br>to NW|600|V|
|Output current||Io|VP, U, V, W, NU, NV, NW terminal<br>current|±15|A|
||||VP, U, V, W, NU, NV, NW terminal<br>current at Tc=100C|±8|A|
|Output peak current||Iop|VP, U, V, W, NU, NV, NW terminal<br>current, pulse width 1ms|±30|A|
|Maximum power dissipation||Pd|IGBT per 1 channel|35|W|
|**Gate driver section**||||||
|Gate driver supply voltage||VBS, VDD|VBU to U, VBV to V, VBW to W, VDD<br>to GND(Note 4)|0.3 to +20.0|V|
|Input signal voltage||VIN|HINU, HINV, HINW, LINU, LINV,<br>LINW,PFCIN|0.3 to VDD|V|
|FLTEN terminal voltage||VFLTEN|FLTEN terminal|0.3 to VDD|V|
|ITRIP terminal voltage||VITRIP|ITRIP terminal|0.3 to +10.0|V|
|PFCTRIP terminal voltage||VPTRIP|PTRIP terminal|1.5 to +2.0|V|
|**Intelligent Power Module**||||||
|Junction temperature||Tj|IGBT, FRD, Gate driver IC|150|C|
|Storage temperature||Tstg||45 to +125|C|
|Operating case temperature||Tc|IPM case temperature|30 to +100|C|
|Tightening torque||MT|Case mounting screws|0.9|Nm|
|Isolation voltage||Vis|50Hz sine wave AC 1 minute<br>(Note 5)|2000|Vrms|



1. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 

3. This surge voltage developed by the switching operation due to the wiring inductance between VP and NU, NV, NW terminals. 4. VBS=VBU to U, VBV to V, VBW to W 

5. Test conditions : AC2500V, 1 s 

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**5** 

## **STK57FU394AG-E** 

## **RECOMMENDED OPERATING RANGES** (Note 6) 

|**Rating**|**Symbol**||**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Supply voltage|VCC|VP to HVGND, NU, NV, NW|0|280|400|V|
|Gate driver supply voltage|VBS|VBU to U, VBV to V, VBW to W|12.5|15|17.5|V|
||VDD|VDD to GND (Note 6)|13.5|15|16.5|V|
|ON-state input voltage|VIN(ON)|HINU, HINV, HINW, LINU, LINV, LINW,<br>PFCIN|2.5|-|5.0|V|
|OFF-state input voltage|VIN(OFF)||0|-|0.3|V|
|PWM frequency(PFC)|fPWMp||1|-|40|kHz|
|PWM frequency(Inverter)|fPWMi||1|-|20|kHz|
|Dead time|DT|Turn-off to Turn-on (external)|1.5|-|-|μs|
|Allowable input pulse width|PWIN|ON and OFF|1|-|-|μs|
|Tightening torque||‘M3’ type screw|0.6|-|0.9|Nm|



6. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 

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**6** 

## **STK57FU394AG-E** 

## **ELECTRICAL CHARACTERISTICS** (Note 7) 

Tc=25C, VBIAS (VBS, VDD)=15V unless otherwise noted. 

|**Parameter**|**Test Conditions**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**PFC Section**|||||||
|Collector-emitter cut-off current|VCE=600V|ICE|-|-|0.1|mA|
|Reverse leakage current (PFC Diode)|VR=600V|IR|-|-|0.1|mA|
|Collector-emitter saturation voltage|IC=30A, Tj=25°C|VCE(sat)|-|1.9|2.5|V|
||IC=15A, Tj=100°C||-|1.6|-|V|
|Diode forward voltage (PFC Diode)|IF=30A, Tj=25°C|VF1|-|2.0|2.6|V|
||IF=15A, Tj=100°C||-|1.5|-||
|Diode forward voltage  (Anti-parallel Diode)|IF=5A, Tj=25°C|VF2|-|1.7|2.3|V|
|Junction to case thermal resistance|IGBT|θj-c(T)|-|-|1.7|°C/W|
||PFC Diode|θj-c(D)|-|-|2.2|°C/W|
|Switching characteristics|||||||
|Switching time|IC=30A, VP=300V, Tj=25C|tON|0.1|0.3|0.8|μs|
|||tOFF|0.1|0.4|0.9|μs|
|Diode reverse recovery time||trr|-|60|-|ns|
|**Inverter section**|||||||
|Collector-emitter leakage current|VCE=600V|ICE|-|-|100|μA|
|Bootstrap diode reverse current|VR(DB)=600V|IR(BD)|-|-|100|μA|
|Collector to emitter saturation voltage|IC=15A, Tj=25C|VCE(SAT)|-|2.0|2.6|V|
||IC=8A, Tj=100C||-|1.7|-|V|
|Diode forward voltage|IF=15A, Tj=25C|VF|-|2.1|2.7|V|
||IF=8A, Tj=100C||-|1.7|-|V|
|Junction to case thermal resistance|IGBT|θj-c(T)|-|-|3.5|C/W|
|Junction to case thermal resistance|FRD|θj-c(D)|-|-|7.2|C/W|
|Switching time|IC = 15A, VCC=300V, Tj=25C|tON|0.1|0.5|1.0|μs|
|||tOFF|0.2|0.7|1.2|μs|
|Turn-on switching loss|IC = 15A, VCC=300V, Tj=25C|EON|-|200|-|μJ|
|Turn-off switching loss||EOFF|-|150|-|μJ|
|Total switching loss||ETOT|-|350|-|μJ|
|Turn-on switching loss|IC = 15A, VCC=300V, Tj=100C|EON|-|300|-|μJ|
|Turn-off switching loss||EOFF|-|200|-|μJ|
|Total switching loss||ETOT|-|500|-|μJ|
|Diode reverse recovery energy|IC = 15A, VCC=300V, Tj=100C<br>(di/dt set by internal driver)|EREC|-|100|-|μJ|
|Diode reverse recovery time||trr|-|200|-|ns|
|Reverse bias safe operating area|Ic=30A, VCE=450V|RBSOA|Full<br>Square|-|||
|Short circuit safe operating area|VCE=400V, Tj=100C|SCSOA|4|-|-|μs|
|Allowable offset voltage slew rate|U to NU, V to NV, W to NW|dv/dt|50|-|50|V/ns|



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**7** 

**STK57FU394AG-E** 

|**Parameter**|**Test Conditions**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**Driver Section**|||||||
|Gate driver consumption current|VBS=15V (Note 4), per driver|ID|-|0.08|0.4|mA|
||VDD=15V, total|ID|-|0.85|2.4|mA|
|High level Input voltage|HINU, HINV, HINW, LINU, LINV, LINW,<br>PFCIN to GND|VIN H|2.5|-|-|V|
|Low level Input voltage||VIN L|-|-|0.8|V|
|Logic 1 input current|VIN=+3.3V|IIN+|-|100|143|μA|
|Logic 0 input current|VIN=0V|IIN-|-|-|2|μA|
|Bootstrap diode forward voltage|IF=0.1A|VF(DB)|-|0.8|-|V|
|Bootstrap circuit resistance|Resistor value for common boot charge<br>line|RBC|-|22|-|Ω|
||Resister values for separate boot<br>charge lines|RBS|-|22|-|Ω|
|FLTEN terminal sink current|FLTEN  : ON / VFAULT=0.1V|IoSD|-|2|-|mA|
|FLTEN  clearance delay time||FLTCLR|1.3|1.65|2.0|ms|
|FLTEN Threshold|VEN ON-state voltage|VEN(ON)|2.5|-|-|V|
||VEN OFF-state voltage|VEN(OFF)|-|-|0.8|V|
|ITRIP threshold voltage|ITRIP to GND|VITRIP|0.44|0.49|0.54|V|
|PTRIP threshold voltage|PTRIP to GND|VPTRIP|0.37|0.31|0.25|V|
|ITRIP to shutdown propagation delay||tITRIP|490|600|850|ns|
|PTRIP to shutdown propagation delay||tPTRIP|440|550|800|ns|
|ITRIP and PTRIP blanking time||tITRIPBL<br>tPFCTRIPBL|290|350|-|ns|
|VDD and VBS supply undervoltage<br>positivegoinginput threshold||VDDUV+<br>VBSUV+|10.5|11.1|11.7|V|
|VDD and VBS supply undervoltage<br>negativegoinginput threshold||VDDUV-<br>VBSUV-|10.3|10.9|11.5|V|
|VDD and VBS supply undervoltage Iockout<br>hysteresis||VDDUVH<br>VBSUVH|0.14|0.2|-|V|



7. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

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**8** 

**STK57FU394AG-E** 

## **TYPICAL CHARACTERISTICS PFC SECTION** 

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**----- Start of picture text -----**<br>
60 60<br>50 50<br>40 40<br>30 30<br>TJ = 25°C<br>20 TJ = 100°C 20<br>TJ = 100°C<br>10 10<br>TJ = 25°C<br>0 0<br>0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4<br>VCE, COLLECTOR-EMITTER VOLTAGE (V) VF, FORWARD VOLTAGE (V)<br>Figure 4. VCE versus IC for different temperatures   Figure 5. PFC Diode VF versus IF for different<br>(VDD=15V) temperatures<br>2.5 1.2<br>2 VVCEDD = 300V = 15V VVCEDD = 300V = 15V<br>0.9<br>1.5<br>TJ = 100°C 0.6 TJ = 100°C<br>1<br>TJ = 25°C TJ = 25°C<br>0.3<br>0.5<br>0 0<br>0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70<br>IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A)<br>, COLLECTOR CURRENT (A)IC , FORWARD CURRENT (A)IF<br>, SWITCHING LOSS (mJ) , SWITCHING LOSS (mJ)<br>ON off<br>E E<br>**----- End of picture text -----**<br>


**Figure 6. EON versus IC for different temperatures** 

**Figure 7. EOFF versus IC for different temperatures** 

**==> picture [227 x 317] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.0<br>0.8<br>0.6<br>0.4<br>0.2<br>0.0<br>0.000001 0.0001 0.01 1 100<br>ON-PULSE WIDTH (S)<br>Figure 8. Thermal Impedance Plot<br>600 60<br>500 50<br>400 40<br>VCE<br>300 30<br>200 20<br>100 10<br>IC<br>0 0<br>-100 -10<br>-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1<br>Time (μs)<br>PEAK R(t)<br>STANDARDIZED SQUARE-WAVE<br>VOLTAGE (V)<br>VCE, COLLECTOR-EMITTER  IC, COLLECTOR CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 9. Turn-on waveform Tj=100°C, VCC=300V** 

**==> picture [222 x 140] intentionally omitted <==**

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600 60<br>500 50<br>400 40<br>IC<br>300 30<br>200 20<br>100 10<br>VCE<br>0 0<br>-100 -10<br>-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1<br>Time (μs)<br>VOLTAGE (V)<br>VCE, COLLECTOR-EMITTER  IC, COLLECTOR CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 10. Turn-off waveform Tj=100°C, VCC=300V** 

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**9** 

**STK57FU394AG-E** 

## **TYPICAL CHARACTERISTICS INVERTER SECTION** 

**==> picture [223 x 143] intentionally omitted <==**

**----- Start of picture text -----**<br>
30<br>25<br>20<br>15<br>TJ = 25°C TJ = 100°C<br>10<br>5<br>0<br>0 0.5 1 1.5 2 2.5 3 3.5 4<br>VCE, COLLECTOR-EMITTER VOLTAGE (V)<br>, COLLECTOR CURRENT (A)<br>IC<br>**----- End of picture text -----**<br>


**Figure 11. VCE versus ID for different temperatures (VDD=15V)** 

**==> picture [223 x 141] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.5<br>VCE = 300V<br>VDD = 15V<br>1<br>TJ = 100°C<br>0.5 TJ = 25°C<br>0<br>0 5 10 15 20 25 30 35<br>IC, COLLECTOR CURRENT (A)<br>, SWITCHING LOSS (mJ)<br>ON<br>E<br>**----- End of picture text -----**<br>


**Figure 13. EON versus ID for different temperatures** 

**==> picture [223 x 319] intentionally omitted <==**

**----- Start of picture text -----**<br>
30<br>25<br>TJ = 25°C<br>20<br>15 TJ = 100°C<br>10<br>5<br>0<br>0 0.5 1 1.5 2 2.5 3 3.5 4<br>VF, FORWARD VOLTAGE (V)<br>Figure 12. VF versus ID for different temperatures<br>0.8<br>VCE = 300V<br>VDD = 15V<br>0.6<br>0.4 TJ = 100°C<br>TJ = 25°C<br>0.2<br>0<br>0 5 10 15 20 25 30 35<br>IC, COLLECTOR CURRENT (A)<br>, FORWARD CURRENT (A)IF<br>, SWITCHING LOSS (mJ)<br>off<br>E<br>**----- End of picture text -----**<br>


**Figure 12. VF versus ID for different temperatures** 

**Figure 14. EOFF versus ID for different temperatures** 

**==> picture [223 x 317] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.0<br>0.8<br>0.6<br>0.4<br>0.2<br>0.0<br>0.000001 0.0001 0.01 1 100<br>ON-PULSE WIDTH (S)<br>Figure 15. Thermal Impedance Plot<br>600 60<br>500 50<br>400 40<br>VCE<br>300 30<br>200 20<br>100 10<br>IC<br>0 0<br>-100 -10<br>-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1<br>Time (μs)<br>PEAK R(t)<br>STANDARDIZED SQUARE-WAVE<br>VOLTAGE (V)<br>VCE, COLLECTOR-EMITTER  IC, COLLECTOR CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 16. Turn-on waveform Tj=100°C, VCC=300V** 

**==> picture [223 x 140] intentionally omitted <==**

**----- Start of picture text -----**<br>
600 60<br>500 50<br>400 40<br>300 30<br>200 IC 20<br>100 10<br>VCE<br>0 0<br>-100 -10<br>-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1<br>Time (μs)<br>VOLTAGE (V)<br>VCE, COLLECTOR-EMITTER  IC, COLLECTOR CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 17. Turn-off waveform Tj=100°C, VCC=300V** 

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**10** 

**STK57FU394AG-E** 

## **APPLICATIONS INFORMATION** 

## **Input / Output Timing Chart** 

**Figure 18. Input / Output Timing Chart** 

Notes 

1. This section of the timing diagram shows the effect of cross-conduction prevention. 

2. This section of the timing diagram shows that when the voltage on VDD decreases sufficiently all gate output signals will go low, switching off all six IGBTs. When the voltage on VDD rises sufficiently, normal operation will resume. 

3. This section shows that when the bootstrap voltage on VBU (VBV, VBW) drops, the corresponding high side output U (V, W) is switched off. When the voltage on VBU (VBV, VBW) rises sufficiently, normal operation will resume. 

4. This section shows that when the voltage on ITRIP exceeds the threshold, all IGBT’s are turned off. Normal operation resumes later after the over-current condition is removed. Similarly, when the voltage on PTRIP exceeds the threshold, all IGBT’s are turned off. Normal operation resumes later after the over-current condition is removed 

5.   After VDD has risen above the threshold to enable normal operation, the driver waits to receive an input signal on the LIN input before enabling the driver for the HIN signal. 

## **Input / Output Logic Table** 

|**Input / Output Logic Table**|**Input / Output Logic Table**|**Input / Output Logic Table**|**Input / Output Logic Table**|||||
|---|---|---|---|---|---|---|---|
|**INPUT **||||**OUTPUT **||||
|**HIN**|**LIN**|**ITRIP**|**PTRIP**|**High side IGBT**|**Low side IGBT**|**U,V,W **|**FAULT**|
|H|L|L|L|ON(Note 5)|OFF|VP|OFF|
|L|H|L|L|OFF|ON|NU,NV,NW|OFF|
|L|L|L|L|OFF|OFF|High Impedance|OFF|
|H|H|L|L|OFF|OFF|High Impedance|OFF|
|X|X|H|X|OFF|OFF|High Impedance|ON|
|X|X|X|H|OFF|OFF|High Impedance|ON|



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**11** 

**STK57FU394AG-E** 

## **Thermistor characteristics** 

|Parameter|Symbol|Condition|Min|Typ|Max|Unit|
|---|---|---|---|---|---|---|
|Resistance|R25|Tc=25℃|99|100|101|kΩ|
||R100|Tc=100℃|5.18|5.38|5.60|kΩ|
|B-Constant (25 to 50℃)|B||4208|4250|4293|K|
|Temperature Range|||40||+125|℃|



**==> picture [335 x 467] intentionally omitted <==**

**----- Start of picture text -----**<br>
Case Temperature(Tc) - Thermistor resistance(RTH)<br>10000<br>min<br>typ<br>1000 max<br>100<br>10<br>1<br>-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130<br>Tc, Case temperature (degC)<br>Figure 19. Thermistor Resistance versus Case Temperature<br>Case Temperature(Tc) - TH to VSS voltage characteristic<br>6.0<br>min<br>5.0<br>typ<br>max<br>4.0<br>3.0<br>2.0<br>1.0<br>0.0<br>-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130<br>Tc, Case temperature [degC]<br>RTH, Thermistor Resistance (kΩ)<br>VTH, TH-VSS terminal voltage [V]<br>**----- End of picture text -----**<br>


**Figure 20. Thermistor Voltage versus Case Temperature Conditions: RTH=39kΩ, pull-up voltage 5.0V (see Figure 2)** 

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**12** 

## **STK57FU394AG-E** 

## **Calculation of bootstrap capacitor value** 

## **Signal inputs** 

Each signal input has a pull-down resistor. An additional pull-down resistor of between 2.2kΩ and 3.3kΩ is recommended on each input to improve noise immunity. 

## **FLTEN pin** 

The FLTEN pin is connected to an open-drain FAULT output requiring a pull-up resistor and an ENABLE input. If the pull-up voltage is 5V, use a pull-up resistor with a value of 6.8kΩ or higher. If the pull-up voltage is 15V, use a pull-up resistor with a value of 20kΩ or higher. The pulled up voltage in normal operation for the FLTEN pin should be above 2.5V, noting that it is connected to an internal ENABLE input. The FAULT output is triggered if there is a VDD undervoltage or an overcurrent condition on either the PFC or inverter stages. 

Driving the FLTEN terminal pin is used to enable or shut down the built-in driver. If the voltage on the FLTEN pin rises above the positive going FLTEN threshold, the output drivers are enabled. If the voltage on the FLTEN pin falls below the negative going FLTEN threshold, the drivers are disabled. 

## **Undervoltage protection** 

If VDD goes below the VDD supply undervoltage lockout falling threshold, the FAULT output is switched on. The FAULT output stays on until VDD rises above the VDD supply undervoltage lockout rising threshold. The hysteresis is approximately 200mV. 

## **Overcurrent protection** 

An over-current condition is detected if the voltage on the ITRIP/PTRIP pin is larger than the reference voltage. There is a blanking time of typically 350ns to improve noise immunity. After a shutdown propagation delay of typically 0.6 us, the FAULT output is switched on. 

The over-current protection threshold should be set to be equal or lower to 2 times the module rated current (Io). 

The bootstrap capacitor value CB is calculated using the following approach. The following parameters influence the choice of bootstrap capacitor: 

- VBS: Bootstrap power supply. 15V is recommended. 

- QG: Total gate charge of IGBT at VBS=15V. 53nC 

- UVLO: Falling threshold for UVLO. Specified as 12V. 

- IDMAX: High side drive power dissipation. Specified as 0.4mA 

- TONMAX: Maximum ON pulse width of high side IGBT. 

Capacitance calculation formula: 

## CB = (QG + IDMAX * TONMAX)/(VBS - UVLO) 

CB is recommended to be approximately 3 times the value calculated above. The recommended value of CB is in the range of 1 to 47μF, however, the value needs to be verified prior to production. When not using the bootstrap circuit, each high side driver power supply requires an external independent power supply. If the capacitors selected are 47 μF or more, a series resistor of 20Ω should be added in series with the three capacitors to limit the current. The resistors should be inserted between VBU and U, VBV and V and VBW and W. 

**==> picture [212 x 123] intentionally omitted <==**

**----- Start of picture text -----**<br>
80<br>60<br>40<br>20<br>0<br>0.1 1 10 100 1000<br>Tonmax [ms]<br>Bootstrap Capacitance CB [uF]<br>**----- End of picture text -----**<br>


**Figure 21. Bootstrap capacitance versus Tonmax** 

An additional fuse is recommended to protect against system level or abnormal over-current fault conditions. 

## **Capacitors on High Voltage and VDD supplies** 

Both the high voltage and VDD supplies require an electrolytic capacitor and an additional high frequency capacitor. The recommended value of the high frequency capacitor is between 100nF and 10 μF. 

## **Minimum input pulse width** 

When input pulse width is less than 1μs, an output may not react to the pulse. (Both ON signal and OFF signal) 

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**STK57FU394AG-E** 

## **Mounting Instructions** 

|**Item**|**Recommended Condition**|
|---|---|
|Pitch|56.0±0.1mm (Please refer to Package Outline Diagram)|
|Screw|diameter : M3<br>Screw head types: pan head, truss head, binding head|
|Washer|Plane washer<br>The size is  D:7mm, d:3.2mm and t:0.5mm JIS B 1256|
|Heat sink|Material: Aluminum or Copper<br>Warpage (the surface that contacts IPM ) :50 to 100 μm<br>Screw holes must be countersunk.<br>No contamination on the heat sink surface that contacts IPM.|
|Torque|Temporary tightening : 20 to 30 % of final tightening on first screw<br>Temporary tightening : 20 to 30 % of final tightening on second screw<br>Final tightening : 0.6 to 0.9Nm on first screw<br>Final tightening: 0.6 to 0.9Nm on second screw|
|Grease|Silicone grease.<br>Thickness : 100 to 200 μm<br>Uniformly apply silicone grease to whole back.<br>Thermal foils are only recommended after careful evaluation. Thickness, stiffness and<br>compressibility parameters have a strong influence on performance.|



**Figure 22. Mount IPM on a Heat Sink** 

**Figure23. Size of Washer** 

**Figure24. Uniform Application of Grease Recommended** 

Steps to mount an IPM on a heat sink 1st: Temporarily tighten maintaining a left/right balance. 2nd: Finally tighten maintaining a left/right balance. 

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**14** 

**STK57FU394AG-E** 

## **TEST CIRCUITS** 

## ■ ICE, IR(DB) 

|ICE, IR(DB)||||||||
|---|---|---|---|---|---|---|---|
||U+|V+|W+|U-|V-|W-|PFC<br>IGBT|
|A|16|16|16|13|9|5|1|
|B|13|9|5|22|21|20|19|



U+,V+,W+ : High side phase 

U-,V-,W- : Low side phase 

||U(DB)|<br>V(DB)|W(DB)|PFC<br>Diode|
|---|---|---|---|---|
|A|12|8|4|16|
|B|35|35|35|1|



**==> picture [201 x 103] intentionally omitted <==**

**----- Start of picture text -----**<br>
VBS=15V  4  ICE<br>5                     A  A<br>VBS=15V  8<br>9  VCE,VR<br>VBS=15V  12<br>13<br>VDD=15 34                   B<br>35,19,20,21,22<br>**----- End of picture text -----**<br>


**Figure 25. Test Circuit for ICE** 

## ■ VCE(sat)  (Test by pulse) 

||U+|V+|W+|U-|V-|W-|PFC<br>IGBT|
|---|---|---|---|---|---|---|---|
|A|16|16|16|13|9|5|1|
|B|13|9|5|22|21|20|19|
|C|23|24|25|26|27|28|29|



**==> picture [213 x 138] intentionally omitted <==**

**----- Start of picture text -----**<br>
VBS=15V  4<br>5                      A<br>VBS=15V  8<br>9<br>VBS=15V  12<br>13  V<br>IC<br>34<br>VCE(sat)<br>VDD=15V<br>30<br>5V  C                      B<br>35,19,20,21,22<br>**----- End of picture text -----**<br>


**Figure 26. Test circuit for VCE(SAT)** 

## ■ VF  (Test by pulse) 

|VF  (Test by|pulse)|||||||||
|---|---|---|---|---|---|---|---|---|---|
||U+|V+||W+||U-|V-|W-||
|A|16||16|16||13|9|5||
|B|13||9|5||22|21|20||
|||||||||||
||U(DB)||V(DB)|||W(DB)|PFC<br>Diode||Anti-parallel<br>Diode|
|A|12||8|||4|16||1|
|B|34||34|||34|1||19|



## ■ ID 

|ID|||||
|---|---|---|---|---|
||VBS U+|VBS V+|VBS W+|VDD|
|A|12|8|4|34|
|B|13|9|5|35|



**==> picture [133 x 103] intentionally omitted <==**

**----- Start of picture text -----**<br>
A<br>V<br>IF<br>B<br>**----- End of picture text -----**<br>


**Figure 27. Test circuit for VF** 

**==> picture [140 x 103] intentionally omitted <==**

**----- Start of picture text -----**<br>
ID<br>A  A<br>VBS, VDD<br>B<br>**----- End of picture text -----**<br>


**Figure 28. Test circuit for ID** 

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**STK57FU394AG-E** 

## ■ VITRIP, VPTRIP 

||VITRIP(U-)|VPTRIP|
|---|---|---|
|A|13|1|
|B|22|19|
|C|26|29|
|D|32|31|



**==> picture [50 x 90] intentionally omitted <==**

**----- Start of picture text -----**<br>
Input signal<br>(0 to 5V)<br>ITRIP<br>/PFCTRIP<br>Io<br>**----- End of picture text -----**<br>


**==> picture [246 x 103] intentionally omitted <==**

**----- Start of picture text -----**<br>
A<br>34<br>VDD=15<br>V<br>30                    Io<br>Input Signal  C<br>VITRIP/VPFCTRIP  D                     B<br>35,19,20,21,22<br>**----- End of picture text -----**<br>


**Figure 29. Test circuit for ITRIP.PTRIP** 

## ■ Switching time (The circuit is a representative example of the lower side U phase.) 

||U+|V+|W+|U-|V-|W-|PFC<br>IGBT|
|---|---|---|---|---|---|---|---|
|A|16|16|16|16|16|16|16|
|B|22|21|20|22|21|20|19|
|C|13|9|5|13|9|5|1|
|D|22|21|20|16|16|16|16|
|E|23|24|25|26|27|28|29|



**==> picture [175 x 116] intentionally omitted <==**

**----- Start of picture text -----**<br>
Input signal<br>(0 to 5V)<br>Io<br>90%<br>10%<br>tON  tOFF<br>**----- End of picture text -----**<br>


**==> picture [223 x 139] intentionally omitted <==**

**----- Start of picture text -----**<br>
VBS=15V  4<br>5                      A<br>VBS=15V  8                      C<br>9<br>VBS=15V  12<br>CS  Vcc<br>13<br>34                    D<br>VDD=15<br>30<br>Input Signal  E                       B<br>35,19,20,21,22<br>Io<br>**----- End of picture text -----**<br>


**Figure 30. Test circuit for switching time** 

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**16** 

**STK57FU394AG-E** 

**Package Dimensions** unit : mm 

**SIP35 56x25.8 / SIP2A-3** CASE 127DY ISSUE O 

ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

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**17** 



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