# Intelligent Power Module (IPM), IGBT, 2 kV, SIP ![Product image](https://novapart.co/image/farnell:2728371/) **URL**: https://novapart.co/products/STK541UC60C-E/intelligent-power-module-ipm-igbt-2-kv-sip **SKU**: STK541UC60C-E **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || Intelligent Power Modules **Price**: €7.3900 **Stock**: 25+ **Lead Time**: 2 days (indicative) ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2728371/) ## **STK541UC60C-E** ## **Intelligent Power Module (IPM) 600 V, 10 A** ## **Overview** This “Inverter IPM” is highly integrated device containing all High Voltage (HV) control from HV-DC to 3-phase outputs in a single SIP module (Single-In line Package). Output stage uses IGBT / FRD technology and implements Under Voltage Protection (UVP) and Over Current Protection (OCP) with a Fault Detection output flag. Internal Boost diodes are provided for high side gate boost drive. www.onsemi.com ## **Function** - Single control power supply due to Internal bootstrap circuit for high side pre-driver circuit - All control input and status output are at low voltage levels directly compatible with microcontrollers - Built-in cross conduction prevention ## **Certification**  UL Recognized (File Number : E339285) ## **Specifications** ## **Absolute Maximum Ratings** at Tc = 25C ||~~ee~~|||| |---|---|---|---|---| |Parameter
~~rs~~|Symbol
~~rs~~
~~ee~~|Conditions
~~rs~~|Ratings
~~rs~~|Unit
~~rs~~| |Supplyvoltage
~~ee~~|VCC
~~ee~~
~~ee~~|P to N, surge < 500 V
*1
~~ee~~|450
~~ee~~|V
~~ee~~| |Collector-emitter voltage
~~Ge~~
~~ee~~|VCE
~~Ge~~|P to U,V,W or U,V,W to N
~~eG~~
~~_~~|600
~~eG~~
~~—~~|V| |Output current
~~ee~~|Io
~~ee~~|P, N, U,V,W terminal current
~~_~~|±10
~~—~~|A| |||P, N, U,V,W terminal current at Tc = 100C
~~_~~
~~ee~~|±5
~~—~~
~~ee~~|A
~~ee~~| |Outputpeak current
~~ee~~
~~es~~|Iop
~~es~~
~~ee~~|P, N, U,V,W terminal current for a Pulse width of 1ms
~~_ ~~
~~es~~|±20
~~—~~
~~es~~|A
~~es~~| |Pre-driver voltage
~~ee~~|VD1, 2, 3, 4 VB1 to U, VB2 to V, VB3 to W, V
~~ee~~
~~ee~~|VD1, 2, 3, 4 VB1 to U, VB2 to V, VB3 to W, VDDto VSS
*2
~~ee~~|20
~~ee~~|V
~~ee~~| |Input signal voltage
~~se~~|VIN
~~se~~|HIN1, 2, 3, LIN1, 2, 3
~~se~~|0.3 to 7
~~se~~|V
~~se~~| |FAULT terminal voltage
~~ee~~|VFAULT
~~ee~~
~~ee~~|FAULT terminal
~~ee~~|0.3 to VDD
~~ee~~|V
~~ee~~| |Maximumpower dissipation
~~es~~|Pd
~~es~~
~~ee~~
~~ee~~|IGBTper channel
~~es~~|22
~~es~~|W
~~es~~| |Junction temperature
~~es~~|Tj
~~ee~~
~~es~~
~~ee~~|IGBT,FRD
~~es~~|150
~~es~~|C
~~es~~| |Storage temperature
~~ee~~|Tstg
~~ee~~
~~ee~~|~~ee~~|40 to +125
~~ee~~|C
~~ee~~| |Operatingsubstrate temperature
~~se~~|Tc
~~se~~
~~ee~~|IPM case temperature
~~se~~|40 to +100
~~se~~|C
~~se~~| |Tighteningtorque
~~es~~|~~es~~
~~ee~~
~~ee~~|Case mountingscrews
*3
~~es~~
~~er~~|0.9
~~es~~|Nm
~~es~~| |Isolation Voltage
~~rs~~|Vis
~~ee~~
~~rs~~
~~ee~~|50 Hz sine wave AC 1 minute
*4
~~rs~~
~~er~~|2000
~~rs~~|VRMS
~~rs~~| Reference voltage is “VSS” terminal voltage unless otherwise specified. - *1 : Surge voltage developed by the switching operation due to the wiring inductance between “P” and “N” terminal. - *2 : VD1 = VB1 to U, VD2 = VB2 to V, VD3 = VB3 to W, VD4 = VDD to VSS terminal voltage. - *3 : Flatness of the heat-sink should be less than 0.15 mm. - *4 : Test conditions : AC 2500 V, 1 second. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ## **ORDERING INFORMATION** See detailed ordering and shipping information on page 12 of this data sheet. **1** Publication Order Number : **STK541UC60C-E/D** © Semiconductor Components Industries, LLC, 2016 **December 2016 - Rev. 2** **STK541UC60C-E** **Electrical Characteristics** at Tc  25C, VD1, VD2, VD3, VD4 = 15 V |**Electrical Characteristics **a|t Tc25C,|VD1,VD2,VD3,VD4 = 15 V|VD1,VD2,VD3,VD4 = 15 V|||||| |---|---|---|---|---|---|---|---|---| |Parameter|Symbol|Conditions||Test
circuit|min|typ|max|Unit| |**Power output section**||||||||| |Collector-emitter cut-off current|ICE|VCE = 600 V||Fig.1|-|-|0.1|mA| |Bootstrap diode reverse current|IR(BD)|VR(BD)|||-|-|0.1|mA| |Collector to emitter
saturation voltage|VCE(SAT)|Ic = 10 A
Tj = 25C|Upper side|Fig.2|-|1.4|2.3|V| ||||Lower side *1||-|1.7|2.6|| |||Ic = 5 A
Tj = 100C|Upper side||-|1.3|-|| ||||Lower side *1||-|1.5|-|| |Diode forward voltage|VF|IF = 10 A
Tj = 25C|Upper side|Fig.3|-|1.3|2.2|V| ||||Lower side *1||-|1.6|2.5|| |||IF = 5 A
Tj = 100C|Upper side||-|1.2|-|| ||||Lower side *1||-|1.4|-|| |Junction to case
thermal resistance|θj-c(T)|IGBT|||-|-|5.5|C/W| ||θj-c(D)|FRD|||-|-|6.5|| |**Control(Pre-driver) section**||||||||| |Pre-driver power dissipation|ID|VD1, 2, 3 =|15 V|Fig.4|-|0.08|0.4|mA| |||VD4 = 15 V|||-|1.6|4.0|| |High level Input voltage|Vin H|HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3 to VSS|||2.5|-|-|V| |Low level Input voltage|Vin L||||-|-|0.8|V| |Input threshold voltage hysteresis|Vinth(hys)||||0.5|0.8|-|V| |Logic 0 input leakage current|IIN+|VIN = +3.3 V|||76|118|160|A| |Logic 1 input leakage current|IIN-|VIN = 0 V|||97|150|203|A| |FAULT terminal sink current|IoSD|FAULT : ON/VFAULT = 0.1 V|||-|2|-|mA| |FAULT clear time|FLTCLR|Fault output latch time|||6|9|12|ms| |VCC and VS undervoltage
positivegoingthreshold|VCCUPVSUP||||10.5|11.1|11.7|V| |VCC and VS undervoltage
negativegoingthreshold|VCCUNVSUN||||10.3|10.9|11.5|V| |VCC and VS undervoltage
hysteresis|VCCUVH
VSUVH-||||0.14|0.2|-|V| |Over current protection level|ISD|PW = 100 μs||Fig.5|10|-|17|A| |Output level for current monitor|ISO|Io = 10 A|||0.30|0.33|0.36|V| Reference voltage is “VSS” terminal voltage unless otherwise specified. *1 : The lower side’s VCE(SAT) and VF include a loss by the shunt resistance ## **Electrical Characteristics** at Tc  25C, VD1, VD2, VD3, VD4 = 15 V, VCC = 300 V, L = 3.9 mH |Parameter|Symbol|Conditions|Test
circuit|min|typ|max|Unit| |---|---|---|---|---|---|---|---| |**Switching Character**|||||||| |Switching time|tON|Io = 10 A|Fig.6|0.3|0.6|1.3|s| ||tOFF|||-|1.0|1.8|| |Turn-on switching loss|Eon|Io = 5 A|Fig.6|-|240|-|J| |Turn-off switching loss|Eoff|||-|220|-|J| |Total switching loss|Etot|||-|460|-|J| |Turn-on switching loss|Eon|Io = 5 A, Tc = 100C|Fig.6|-|300|-|J| |Turn-off switching loss|Eoff|||-|260|-|J| |Total switching loss|Etot|||-|560|-|J| |Diode reverse recovery energy|Erec|IF= 5 A, P = 400 V,
Tc = 100C||-|17|-|J| |Diode reverse recovery time|trr|||-|62|-|ns| |Reverse bias safe operating area|RBSOA|Io = 20 A, VCE = 450 V|||Full square||| |Short circuit safe operating area|SCSOA|VCE = 400 V, Tc = 100C||4|-|-|s| Reference voltage is “VSS” terminal voltage unless otherwise specified. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. **www.onsemi.com** **2** **STK541UC60C-E** ## Notes 1. The pre-drive power supply low voltage protection has approximately 0.2 V of hysteresis and operates as follows. - Upper side : The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will continue till the input signal will turn ‘high’. - Lower side : The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input signal voltage. 2. The pre-drive low voltage protection is the feature to protect devices when the pre-driver supply voltage falls due to an operating malfunction. **www.onsemi.com** **3** **STK541UC60C-E** **Equivalent Block Diagram** **==> picture [427 x 516] intentionally omitted <==** **----- Start of picture text -----**
VB1(8)
U(9)
VB2(5)
V(6)
VB3(2)
W(3)
P(11)
U.V. U.V. U.V.
Shunt Resistor
N (13)
Level Level Level
Shifter Shifter Shifter
HIN1(14)
HIN2(15)
HIN3(16) Logic Logic Logic
LIN1(17)
LIN2(18)
LIN3(19)
FAULT(20)
ISO(21) Latch Time About 9ms
Latch ( Automatic Reset )
VDD(22)
Over-Current
VSS(23)
VDD-Under Voltage
**----- End of picture text -----**
**www.onsemi.com** **4** **STK541UC60C-E** ## **Module Pin-Out Description** |**Pin**|**Name**|**Description**| |---|---|---| |1||Without Pin| |2|VB3|High Side Floating Supply Voltage 3| |3|W,VS3|Output 3 - High Side Floating Supply Offset Voltage| |4||Without Pin| |5|VB2|High Side Floating Supply voltage 2| |6|V,VS2|Output 2 - High Side Floating Supply Offset Voltage| |7||Without Pin| |8|VB1|High Side Floating Supply voltage 1| |9|U,VS1|Output 1 - High Side Floating Supply Offset Voltage| |10||Without Pin| |11|P|Positive Bus Input Voltage| |12||Without Pin| |13|N|Negative Bus Input Voltage| |14|HIN1|Logic Input High Side Gate Driver - Phase U| |15|HIN2|Logic Input High Side Gate Driver - Phase V| |16|HIN3|Logic Input High Side Gate Driver - Phase W| |17|LIN1|Logic Input Low Side Gate Driver - Phase U| |18|LIN2|Logic Input Low Side Gate Driver - Phase V| |19|LIN3|Logic Input Low Side Gate Driver - Phase W| |20|FAULT|Fault output| |21|ISO|Current monitor output| |22|VDD|+15 V Main Supply| |23|VSS|Negative Main Supply| **www.onsemi.com** **5** **STK541UC60C-E** ## **Test Circuit**  The tested phase U+ shows the upper side of the U phase and U shows the lower side of the U phase. ## ■ ICE / IR(BD) ||U+|V+|V+|W+|U-|V-|W-| |---|---|---|---|---|---|---|---| |M|11|11||11|9|6|3| |N|9|6||3|13|13|13| ||||||||| ||U(BD)||V(BD)||W(BD)||| |M|8||5||2||| |N|23||23||23||| **==> picture [202 x 132] intentionally omitted <==** **----- Start of picture text -----**
ICE
8 M A
VD1=15V
9
5
VD2=15V
6 VCE
2
VD3=15V
3
22
VD4=15V
23 N
**----- End of picture text -----**
Fig.1 ## ■ VCE(SAT) (test by pulse) ||U+|V+|W+|U-|V-|W-| |---|---|---|---|---|---|---| |M|11|11|11|9|6|3| |N|9|6|3|13|13|13| |m|14|15|16|17|18|19| **==> picture [199 x 138] intentionally omitted <==** **----- Start of picture text -----**
8 M
VD1=15V
9
5
VD2=15V
6
V Ic
2
VD3=15V VCE(SAT)
3
22
VD4=15V
m N
23
**----- End of picture text -----**
Fig.2 **==> picture [171 x 211] intentionally omitted <==** **----- Start of picture text -----**
M
V VF IF
N
ID
A M
VD*
N
**----- End of picture text -----**
## ■ VF (test by pulse) ||U+|V+|W+|U-|V-|W-| |---|---|---|---|---|---|---| |M|11|11|11|9|6|3| |N|9|6|3|13|13|13| Fig.3 ## ■ ID ||VD1|VD2|VD3|VD4| |---|---|---|---|---| |M|8|5|2|22| |N|9|6|3|23| Fig.4 **www.onsemi.com** **6** **STK541UC60C-E** ## ■ ISD **==> picture [414 x 180] intentionally omitted <==** **----- Start of picture text -----**
8 9
VD1=15V
9
Input signal
(0 to 5 V) 5
VD2=15V
6
Io
2
VD3=15V
3
22
Io ISD VD4=15V
Input signal 17 13
100 μs 23
Fig.5
**----- End of picture text -----**
■ Switching time (The circuit is a representative example of the lower side U phase.) **==> picture [485 x 158] intentionally omitted <==** **----- Start of picture text -----**
8 11
VD1=15V
9
Input signal 5
(0 to 5 V) VD2=15V
6 9 VCC
2 CS
90% VD3=15V
3
Io 22
VD4=15V Io
10%
Input signal 17 13
23
tON tOFF
**----- End of picture text -----**
Fig.6 **www.onsemi.com** **7** **STK541UC60C-E** **Input / Output Timing Chart** **==> picture [489 x 572] intentionally omitted <==** **----- Start of picture text -----**
VBS undervoltage protection reset signal
OFF
HIN1,2,3
ON
LIN1,2,3
VDD undervoltage protection reset voltage
*2
VDD
VBS undervoltage protection reset voltage
*3
VB1,2,3
*4
-------------------------------------------------------ISD operation current level-------------------------------------------------------
N terminal
(BUS line)
Current
FAULT terminal
Voltage
(at pulled-up)
ON
*1
Upper
U, V, W
OFF
*1
Lower
U ,V, W
Automatically reset after protection
(typ.9ms)
Fig.7
**----- End of picture text -----**
## Notes - *1 : Diagram shows the prevention of shoot-through via control logic. More deadtime to account for switching delay needs to be added externally. - *2 : If lower VDD drops all gate output signals will go low and cut off all of 6 IGBT outputs. part. When VDD rises the operation will resume immediately. - *3 : When the upper side gate voltage at VB1, VB2 and VB3 drops only the corresponding upper side output is turned off. The outputs return to normal operation immediately after the upper side gat voltage rises. - *4 : In case of over current detection all IGBT’s are turned off and the FAULT output is asserted. Normal operation resumes in 6 to 12 ms after the over current condition is removed. **www.onsemi.com** **8** **STK541UC60C-E** ## **Logic level table** ## P(11) |||||||||||||||| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| ||||Upper
IGBT||||HIN|INPUT
LIN|
OCP|Upper
IGBT|Lower
IGBT|OUTPUT

U,V,W||FAULT| |HIN1,2,3
(14,15,16)
LIN1,2,3
(17,18,19)||IC
Driver|Lower|||U,V,W
(9,6,3)|H
L
L
H|L
H
L
H|OFF
OFF
OFF
OFF|OFF
ON
OFF
OFF|ON
OFF
OFF
OFF||N
P
High
Impedance
High
Impedance|OFF
OFF
OFF
OFF| ||||IGBT||||X|X|ON|OFF|OFF||High
Impedance|ON| ||||N(13)|||||||||||| Fig. 8 ## **Sample Application Circuit** **==> picture [447 x 213] intentionally omitted <==** **----- Start of picture text -----**
STK541UC60C-E
2 3 5 6 8 9 11 13 14 15 16 17 18 19 20 21 22 23
CB CB CB
CS
CD
Control Logic VDD=15V
VCC CI
VB3 W VB2 V VB1 U P N HIN1 HIN2 HIN3 LIN1 LIN2 LIN3 FAULT ISO VDD VSS
**----- End of picture text -----**
Fig. 9 **Recommended Operating Conditions** at Ta = 25C |Item|Symbol|Conditions|Conditions|min|typ|max|Unit| |---|---|---|---|---|---|---|---| |Supplyvoltage|VCC|P to N||0|280|450|V| |Pre-driver supply voltage|VD1,2,3|VB1 to U,VB2 to V,VB3 to W||12.5|15|17.5|V| ||VD4|VDDto VSS|*1|13.5|15|16.5|| |PWM frequency|fPWM|||1|-|20|kHz| |Dead time|DT|Turn-off to turn-on||2|-|-|μs| |Allowable inputpulse width|PWIN|ON and OFF||1|-|-|μs| |Tighteningtorque||‘M3’ type screw||0.6|-|0.9|Nm| |*1 : Pre-drive power supply (VD4 = 15 ±1.5 V) must have the capacity of Io = 20 mA (DC), 0.5A (Peak).|||||||| Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. **www.onsemi.com** **9** **STK541UC60C-E** ## **Usage Precaution** 1. This IPM includes bootstrap diode and resistors. Therefore, by adding a capacitor “CB”, a high side drive voltage is generated; each phase requires an individual bootstrap capacitor. The recommended value of CB is in the range of 1 to 47 μF, however this value needs to be verified prior to production. If selecting the capacitance more than 47 μF (±20%), connect a resistor (about 20 Ω) in series between each 3-phase upper side power supply terminals (VB1, 2, 3) and each bootstrap capacitor. When not using the bootstrap circuit, each upper side pre-drive power supply requires an external independent power supply. 2. It is essential that wiring length between terminals in the snubber circuit be kept as short as possible to reduce the effect of surge voltages. Recommended value of “CS” is in the range of 0.1 to 10 μF. 3. “ISO” (pin 21) is terminal for current monitor. High current may flow into that course when short-circuiting the “ISO” terminal and “VSS” terminal. Please do not connect them. 4. “FAULT” (pin 20) is open DRAIN output terminal (Active Low). Pull up resistor is recommended more than 6.8 kΩ. 5. Pull up resistor of 100 kΩ is provided internally at the signal input terminals. 6. The over-current protection feature is not intended to protect in exceptional fault condition. An external fuse is recommended for safety. 7. When input pulse width is less than 1.0 μs, an output may not react to the pulse (Both ON signal and OFF signal). This data shows the example of the application circuit, does not guarantee a design as the mass production set. ## **The characteristic of PWM switching frequency** **==> picture [394 x 238] intentionally omitted <==** **----- Start of picture text -----**
14
12
10
8
6
4
2
0
0 2 4 6 8 10 12 14 16 18 20
PWM Switching Frequency (kHz)
Maximum RMS Output Current / Phase (A)
**----- End of picture text -----**
Fig. 10 Maximum sinusoidal phase current as function of switching frequency at Tc = 100C, VCC = 400 V **www.onsemi.com** **10** **STK541UC60C-E** ## **CB capacitor value calculation for bootstrap circuit** ## **Calculate conditions** |**alculate conditions**|||| |---|---|---|---| |Parameter|Symbol|Value|Unit| |Upper side power supply|VBS|15|V| |Total gate charge of output power IGBT at 15 V|QG|89|nC| |Upper limit power supply low voltage protection|UVLO|12|V| |Upper side power dissipation|IDMAX|400|μA| |ON time required for CB voltage to fall from 15V to UVLO|TONMAX|-|s| ## **Capacitance calculation formula** Thus, the following formula are true VBS  CB  QG  IDMAX  TONMAX = UVLO  CB therefore, CB = (QG + IDMAX  TONMAX) / (VBS  UVLO) The relationship between TONMAX and CB becomes as follows. CB is recommended to be approximately 3 times the value calculated above. The recommended value of CB is in the range of 1 to 47 μF, however, this value needs to be verified prior to production. **==> picture [402 x 256] intentionally omitted <==** **----- Start of picture text -----**
CB vs Tonmax
100
10
1
0.1
0.01
0.1 1 10 100 1000
Tonmax [ms]
Bootstrap Capacitance CB [uF]
**----- End of picture text -----**
Fig. 11 Tonmax - CB characteristic **www.onsemi.com** **11** **STK541UC60C-E** ## **PACKAGE DIMENSIONS** unit : mm  The tolerances of length are +/ 0.5 mm unless otherwise specified. **==> picture [234 x 196] intentionally omitted <==** **----- Start of picture text -----**
note2
note3
4DB00
note1 1 23
**----- End of picture text -----**
missing pin : 1, 4, 7, 10, 12 - note 1 : Mark for No.1 pin identification. note 2 : The form of a character in this drawing differs from that of IPM. note 3 : This indicates the lot code. - The form of a character in this drawing differs from that of IPM. ## **ORDERING INFORMATION** |**ORDERING INFORMATION**|| |---|---| |Device|Package| |STK541UC60C-E|SIP23 56x21.8
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