# Power MOSFET, N Channel, 40 V, 100 A, 1200 µohm, LFPAK, Surface Mount

![Product image](https://novapart.co/image/farnell:3106037RL/)

**URL**: https://novapart.co/products/STK224N4F7AG/power-mosfet-n-channel-40-v-100-a-1200-ohm-lfpak
**SKU**: STK224N4F7AG
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.8900
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (17-Dec-2015) |
| No. Of Pins | 4Pins |
| Channel Type | N Channel |
| Product Range | STripFET F7 |
| Qualification | AEC-Q101 |
| Power Dissipation | 150W |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 150W |
| Rds(On) Test Voltage | 10V |
| On Resistance Rds(On) | 0.0012ohm |
| Transistor Case Style | LFPAK |
| Drain Source Voltage Vds | 40V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 100A |
| Drain Source On State Resistance | 1200µohm |
| Automotive Qualification Standard | AEC-Q101 |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3106037RL/)

**STK224N4F7AG** 

Datasheet 

Automotive-grade N-channel 40 V, 1.2 mΩ typ., 100 A STripFET™ F7 Power MOSFET in a LFPAK 5x6 package 

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TAB<br>4<br>3<br>2<br>,<br>1<br>**----- End of picture text -----**<br>


## **Features** 

|**Features**<br>**Order code**<br>STK224N4F7AG<br>AEC-Q101 qualified|**VDS**<br>40 V<br>on|**RDS(on) max**<br>1.5 mΩ|**ID**<br>100 A|
|---|---|---|---|



- AEC-Q101 qualified 

- Among the lowest RDS(on) on the market 

- Excellent FoM (figure of merit) 

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LFPAK 5x6<br>**----- End of picture text -----**<br>


- Low Crss/Ciss ratio for EMI immunity 

- High avalanche ruggedness 

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D(TAB)<br>G(4)<br>S(1, 2, 3)<br>G4S123DTAB_LFPAK<br>**----- End of picture text -----**<br>


## **Applications** 

- Switching applications 

## **Description** 

This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. 

|**Product summary**<br>~~ee~~|**Product summary**<br>~~ee~~|
|---|---|
|**Order code**|STK224N4F7AG|
|**Marking**|224N4F7|
|**Package**|LFPAK 5x6|
|**Packing**|Tape and reel|



**DS12550** - **Rev 2** - **January 2019** For further information contact your local STMicroelectronics sales office. 

www.st.com 

**STK224N4F7AG Electrical ratings** 

## **1 Electrical ratings** 

## **Table 1. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|40|V|
|VGS|Gate-source voltage|±20|V|
|ID (1)|Drain current (continuous) at TC= 25 °C|100|A|
|ID (1)|Drain current (continuous) at TC= 100 °C|100|A|
|IDM (2)|Drain current (pulsed)|400|A|
|PTOT|Total dissipation at TC= 25 °C|150|W|
|IAV|Avalanche current, repetitive or not repetitive (pulse width limited by maximum junction<br>temperature)|56|A|
|EAS|Single pulse avalanche energy<br>(starting TJ= 25 °C, ID= IAV, VDD= 25 V)|470|mJ|
|Tj|Operating junction temperature range|-55 to 175|°C|
|Tstg|Storage temperature range|||



_1. Drain current is limited by package, the current capability of the silicon is 224 A at 25 °C._ 

_2. Pulse width limited by safe operating area_ 

**Table 2. Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-pcb (1)|Thermal resistance junction-pcb.|31.3|°C/W|
|Rthj-case|Thermal resistance junction-case.|1.0|°C/W|



_1. When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s._ 

**DS12550** - **Rev 2** 

**page 2/13** 

**STK224N4F7AG Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

**Table 3. On /off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 1 mA|40|||V|
|IDSS|Zero gate voltagedrain<br>current|VGS= 0 V, VDS= 40 V|||1|µA|
|IGSS|Gate-body leakage current|VGS= 20 V, VDS= 0 V|||100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 μA|2||4|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 50 A||1.2|1.5|mΩ|



**Table 4. Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 25 V, f = 1 MHz,<br>VGS= 0 V|-|4060|-|pF|
|Coss|Output capacitance||-|1100|-|pF|
|Crss|Reverse transfer capacitance||-|300|-|pF|
|Qg|Total gate charge|VDD= 20 V, ID= 100 A,<br>VGS= 0 to 10 V(seeFigure 13. Test<br>circuit for gate charge behavior)|-|50|-|nC|
|Qgs|Gate-source charge||-|23|-|nC|
|Qgd|Gate-drain charge||-|9.8|-|nC|



**Table 5. Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 20 V, ID= 50 A,<br>RG= 4.7 Ω, VGS= 10 V<br>(seeFigure 12. Test circuit for<br>resistive load switching timesand<br>Figure 17. Switching time waveform)|-|25|-|ns|
|tr|Rise time||-|20|-|ns|
|td(off)|Turn-off delay time||-|48|-|ns|
|tf|Fall time||-|31|-|ns|



**Table 6. Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VSD (1)|Forward on voltage|ISD= 100 A, VGS= 0 V|-||1.1|V|
|trr|Reverse recovery time|ID= 100 A, di/dt = 100 A/µs<br>VDD= 20 V (seeFigure 14. Test<br>circuit for inductive load switching and<br>diode recovery times)|-|41||ns|
|Qrr|Reverse recovery charge||-|32||nC|
|IRRM|Reverse recovery current||-|1.6||A|



_1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%_ 

**DS12550** - **Rev 2** 

**page 3/13** 

**STK224N4F7AG Electrical characteristics curves** 

## **2.1 Electrical characteristics curves** 

**Figure 1. Safe operating area** 

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ID ADG191220181216SOA<br>(A)<br>10  [2 ] tp = 10µs<br>10  [1 ] tp = 100µs<br>Tj = 175 °C<br>10  [0 ] Tc = 25 °C<br>single pulse tp = 1ms<br>10  [-1 ] tp = 10ms<br>10  [-1 ] 10  [0 ] 10  [1 ] VDS (V)<br>DS(on)<br>Operation in this area is<br>limited by max. R<br>**----- End of picture text -----**<br>


**Figure 2. Thermal impedance** 

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K  ADG191220181217ZTH<br>δ = 0.5<br>0.2<br>0.1<br>10  [-1 ]<br>0.05<br>0.02<br>0.01<br>Single pulse<br>10  [-2 ]<br>10  [-5 ] 10  [-4 ] 10  [-3 ] 10  [-2 ] 10  [-1 ] tp (s)<br>**----- End of picture text -----**<br>


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Figure 3. Output characterisics Figure 4. Transfer characteristics<br>ID ADG191220181217OCH ID ADG191220181218TCH<br>(A)  VGS = 9, 10V (A)<br>VGS = 7, 8 V 60<br>125<br>VGS = 6 V 50<br>100<br>40<br>75<br>VDS = 5 V<br>30<br>50<br>20<br>25 VGS = 5 V 10<br>0 0<br>0 1 2 3 4 5 VDS (V) 0 2 4 6 8 VGS (V)<br>**----- End of picture text -----**<br>


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Figure 5. Static drain-source on resistance Figure 6. Gate charge vs gate-source voltage<br>RDS(on) [mΩ] ADG191220181218RID VGS ADG191220181219QVG<br>(V)<br>12<br>1.30<br>VGS = 10 V 10 VDS = 20 V<br>ID = 100 A<br>8<br>1.10 6<br>4<br>2<br>1 0<br>0 20 40 60 80 ID [A] 0 10 20 30 40 50 Qg (nC)<br>**----- End of picture text -----**<br>


**DS12550** - **Rev 2** 

**page 4/13** 

**STK224N4F7AG Electrical characteristics curves** 

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Figure 7. Capacitance variations<br>C  ADG191220181219CVR<br>(pF)<br>10  [4 ]<br>CISS<br>10  [3 ]<br>COSS<br>CRSS<br>10  [2 ]<br>10  [1 ]<br>0 10 20 30 40 VDS (V)<br>**----- End of picture text -----**<br>


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Figure 8. Normalized gate threshold voltage vs<br>temperature<br>VGS(th) ADG191220181220VTH<br>(norm.)<br>1.20<br>1.00<br>0.80<br>ID = 250 µA<br>0.60<br>0.40<br>0.20<br>-75 -25 25 75 125 175 Tj (°C)<br>**----- End of picture text -----**<br>


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Figure 9. Normalized on resistance vs temperature Figure 10. Source-drain diode forward characteristic<br>RDS(on) ADG191220181220RON VSD ADG191220181221SDF<br>(norm.)  (V)<br>1.8 1.0<br>Tj = -55 °C<br>1.6 0.9<br>VGS = 10 V  Tj = 25°C<br>1.4 0.8<br>ID = 50 A<br>1.2 0.7<br>Tj = 175°C<br>1 0.6<br>0.8 0.5<br>0.6 0.4<br>-75 -25 25 75 125 175 Tj (°C) 10 30 50 70 90 ISD (A)<br>**----- End of picture text -----**<br>


## **Figure 11. Normalized V(BR)DSS vs temperature** 

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V(BR)DSS ADG191220181222BDV<br>(norm.)<br>1.06<br>1.04<br>1.02 ID = 1 mA<br>1.00<br>0.98<br>0.96<br>0.94<br>-75 -25 25 75 125 175 Tj (°C)<br>**----- End of picture text -----**<br>


**DS12550** - **Rev 2** 

**page 5/13** 

**STK224N4F7AG Test circuits** 

**3 Test circuits** 

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Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior<br>VDD<br>12 V 47 kΩ<br>1 kΩ<br>100 nF<br>RL 2200 3.3<br>+ μF μF VDD<br>VD VGS IG= CONST 100 Ω D.U.T.<br>VGS RG D.U.T. pulse width 2200 + 2.7 kΩ VG<br>pulse width μF<br>47 kΩ<br>1 kΩ<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


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Figure 14. Test circuit for inductive load switching and<br>Figure 15. Unclamped inductive load test circuit<br>diode recovery times<br>A A A L<br>G D D.U.T. fastdiode 100 µH VD 2200 3.3<br>25 Ω S B B B D µF3.3 + 1000µF VDD ID + µF µF VDD<br>G D.U.T.<br>+ RG S Vi D.U.T.<br>_ pulse width<br>AM01471v1<br>AM01470v1<br>**----- End of picture text -----**<br>


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Figure 17. Switching time waveform<br>Figure 16. Unclamped inductive waveform<br>ton toff<br>V(BR)DSS<br>td(on) tr td(off) tf<br>VD<br>90% 90%<br>IDM<br>ID 0 10% VDS 10%<br>VDD VDD VGS 90%<br>AM01472v1 0 10%<br>AM01473v1<br>**----- End of picture text -----**<br>


**DS12550** - **Rev 2** 

**page 6/13** 

**STK224N4F7AG Package information** 

**4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: www.st.com. ECOPACK[®] is an ST trademark. 

**DS12550** - **Rev 2** 

**page 7/13** 

**STK224N4F7AG LFPAK 5x6 package information** 

## **4.1 LFPAK 5x6 package information** 

**Figure 18. LFPAK 5x6 package outline** 

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00299525_A<br>**----- End of picture text -----**<br>


**DS12550** - **Rev 2** 

**page 8/13** 

**STK224N4F7AG LFPAK 5x6 package information** 

**Table 7. LFPAK 5x6 package mechanical data** 

|**Di**|**mm**|**mm**|**mm**|
|---|---|---|---|
|**m.**|**Min.**|**Typ.**|**Max.**|
|A|1.01||1.20|
|A1|0.00||0.15|
|A2|0.95||1.10|
|A3||0.25||
|A4|0.50|0.55|0.65|
|b|0.35||0.50|
|b2|3.62||4.41|
|b3|2.0||2.20|
|b4|0.70||0.90|
|b5|||0.7|
|c|0.19|0.20(1)|0.25|
|c2|0.24||0.30|
|D|3.80||4.10|
|D1|3.80|4.00|4.20|
|E|4.8||5.0|
|E1|3.1||3.3|
|e||1.27||
|H|5.8||6.2|
|L|0.40||0.85|
|L1|0.80||1.30|
|L2|0.80||1.3|
|w||0.25||
|y||0.10||
|ϴ|0°||8°|



_1. Dimension without plating_ 

**DS12550** - **Rev 2** 

**page 9/13** 

**STK224N4F7AG LFPAK 5x6 package information** 

**Figure 19. LFPAK 5x6 recommended footprint** 

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00299525_FP_A 

**DS12550** - **Rev 2** 

**page 10/13** 

**STK224N4F7AG** 

## **Revision history** 

**Table 8. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|09-Apr-2018|1|First release.|
|14-Jan-2019|2|Updated title in cover page,Section 1 Electrical ratingsandSection 2 Electrical characteristics.<br>AddedSection 2.1 Electrical characteristics curves<br>Minor text changes.|



**DS12550** - **Rev 2** 

**page 11/13** 

**STK224N4F7AG Contents** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2**|
|**2**|**Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3**|
||**2.1**<br>Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3|
|**3**|**Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6**|
|**4**|**Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7**|
||**4.1**<br>LFPAK 5x6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|**Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11**||



**DS12550** - **Rev 2** 

**page 12/13** 

**STK224N4F7AG** 

## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2019 STMicroelectronics – All rights reserved 

**DS12550** - **Rev 2** 

**page 13/13** 



## Links

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- [Supplier page](https://es.farnell.com/stmicroelectronics/stk224n4f7ag/mosfet-aec-q101-n-ch-40v-100a/dp/3106037RL)
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