# Intelligent Power Module (IPM), MOSFET, 500 V, 2 A, 1 kV, NSDIP, SLLIMM-nano
**URL**: https://novapart.co/products/STIPNS2M50T-H/intelligent-power-module-ipm-mosfet-500-v-2-a-1-kv
**SKU**: STIPNS2M50T-H
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || Intelligent Power Modules
**Price**: €3.9200
**Stock**: 10+
**Lead Time**: 127 days (indicative)
## Description
IPM Power Device:MOSFET; Voltage Rating (Vces / Vdss):500V; Current Rating (Ic / Id):2A; Isolation Voltage:1kV; IPM Case Style:NSDIP; IPM Series:SLLIMM-nano; Product Range:-; SVHC:N
## Specifications
| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| Ipm Series | SLLIMM-nano |
| Product Range | - |
| Ipm Case Style | NSDIP |
| Ipm Power Device | MOSFET |
| Isolation Voltage | 1kV |
| Current Rating (Ic / Id) | 2A |
| Voltage Rating (Vces / Vdss) | 500V |
## Datasheet
📄 [Download PDF](https://novapart.co/datasheet/farnell:2980953/)
## **STIPNS2M50T-H**
## SLLIMM™-nano small low-loss intelligent molded module IPM, 3-phase inverter, 2 A, 1.7 Ω max., 500 V MOSFET
Datasheet - production data
## **Applications**
**==> picture [138 x 122] intentionally omitted <==**
**----- Start of picture text -----**
16
17
1
26
NSDIP-26L
**----- End of picture text -----**
## **Features**
- IPM 2 A, 500 V, RDS(on) = 1.7 Ω, 3-phase MOSFET inverter bridge including control ICs for gate driving
- Optimized for low electromagnetic interference
- 3.3 V, 5 V, 15 V CMOS/TTL input comparators with hysteresis and pulldown/pull-up resistors
- 3-phase inverters for small power motor drives
- Dish washers, refrigerator compressors, heating systems, air-conditioning fans, draining and recirculation pumps
## **Description**
This SLLIMM (small low-loss intelligent molded module) nano provides a compact, high performance AC motor drive in a simple, rugged design. It is composed of six MOSFETs and three half-bridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed. The package is optimized for thermal performance and compactness in built-in motor applications, or other low power applications where assembly space is limited. This IPM includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. SLLIMM™ is a trademark of STMicroelectronics.
- Undervoltage lockout
- Internal bootstrap diode
- Interlocking function
- Comparator for fault protection against overtemperature and overcurrent
- Op-amp for advanced current sensing
- Optimized pinout for easy board layout
- NTC for temperature control (UL 1434 CA 2 and 4)
- Moisture sensitivity level (MSL) 3
**Table 1: Device summary**
- **Order code Marking Package Packing**
- ~~_—~~ STIPNS2M50T-H IPNS2M50T-H NSDIP-26L Tape and reel
This is information on a product in full production.
_www.st.com_
January 2018 DocID030525 Rev 2
1/24
|**Contents**
**STIPNS2M50T-H**|**Contents**
**STIPNS2M50T-H**|
|---|---|
|**Contents**||
|**1**|**Internal schematic diagram and pin configuration ....................... 3**|
|**2**|**Electrical ratings ............................................................................. 6**|
||2.1
Absolute maximum ratings ................................................................ 6|
||2.2
Thermal data ..................................................................................... 6|
|**3**|**Electrical characteristics ................................................................ 7**|
||3.1
Inverter part ....................................................................................... 7|
||3.2
Control part ....................................................................................... 9|
||3.2.1
NTC thermistor ................................................................................. 11|
||3.3
Waveform definitions ....................................................................... 14|
|**4**|**Smart shutdown function ............................................................. 15**|
|**5**|**Application circuit example .......................................................... 17**|
||5.1
Guidelines ....................................................................................... 18|
|**6**|**Package information ..................................................................... 20**|
||6.1
NSDIP-26L package information ..................................................... 20|
|**7**|**Revision history ............................................................................ 23**|
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**Internal schematic diagram and pin configuration**
## **1 Internal schematic diagram and pin configuration**
**Figure 1: Internal schematic diagram**
**==> picture [463 x 485] intentionally omitted <==**
**----- Start of picture text -----**
GND(1) (26)NW
T/SD/OD(2) NTC
GND (25)W,OUTW
VccW(3) HVG
OUT (24)VbootW
HinW(4) VCC
HIN LVG
SD/OD
LinW(5) LIN Vboot
OP+(6)
(23)NV
OPOUT(7) GND OP+
OPOUT
OP- HVG (22)V,OUTV
OP-(8)
OUT
VCC
VccV(9) HIN LVG
SD/OD
HinV(10) LIN Vboot
(21)VbootV
LinV(11)
GND (20)NU
Cin(12) CIN
HVG
VccU(13)
OUT (19)U,OUTU
VCC
HinU(14) HIN LVG
SD/OD
LIN Vboot (18)P
T/SD/OD(15)
LinU(16) (17)VbootU
GIPD120120170806S A
**----- End of picture text -----**
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**STIPNS2M50T-H**
## **Internal schematic diagram and pin configuration**
**Table 2: Pin description**
|**Pin**|**Symbol**|**Description**|
|---|---|---|
|1|GND|Ground|
|2|T/SD
̅̅̅̅/OD|NTC thermistor terminal / shutdown logic input (active low) / open-drain
(comparator output)|
|3|VCCW|Low-voltagepower supplyWphase|
|4|HIN W|High-side logic input for Wphase|
|5|LIN W|Low-side logic input for Wphase|
|6|OP+|Op-ampnon invertinginput|
|7|OPOUT|Op-ampoutput|
|8|OP-|Op-ampinvertinginput|
|9|VCCV|Low-voltage power supply V phase|
|10|HIN V|High-side logic input for Vphase|
|11|LIN V|Low-side logic input for Vphase|
|12|CIN|Comparator input|
|13|VCCU|Low-voltagepower supplyfor Uphase|
|14|HIN U|High-side logic input for Uphase|
|15|T/SD
̅̅̅̅/OD|NTC thermistor terminal / shutdown logic input (active low) / open-drain
(comparator output)|
|16|LIN U|Low-side logic input for Uphase|
|17|VBOOTU|Bootstrapvoltage for Uphase|
|18|P|Positive DC input|
|19|U, OUTU|Uphase output|
|20|NU|Negative DC input for Uphase|
|21|VBOOTV|Bootstrapvoltage for Vphase|
|22|V, OUTV|Vphase output|
|23|NV|Negative DC input for Vphase|
|24|VBOOTW|Bootstrapvoltage for Wphase|
|25|W, OUTW|Wphase output|
|26|NW|Negative DC input for Wphase|
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**Internal schematic diagram and pin configuration**
**Figure 2: Pin layout (top view)**
**==> picture [406 x 209] intentionally omitted <==**
**----- Start of picture text -----**
(*) (*)
PIN #1 ID
(*) Dummy pin internally connected to P (positive DC input).
**----- End of picture text -----**
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**Electrical ratings**
## **2 Electrical ratings**
## **2.1 Absolute maximum ratings**
**Table 3: Inverter part**
|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDSS|MOSFET blocking voltage (or drain-source voltage) for each MOSFET
(VIN_(1)_= 0)|500|V|
|± ID|Continuous current each MOSFET|2|A|
|± IDP_(2)_|Peak drain current each MOSFET (less than 1 ms)|4|A|
|PTOT|Each MOSFET total dissipation at TC= 25 °C|10.4|W|
## **Notes:**
- (1)Applied among HINi, LINi and GND for i = U, V, W.
- (2)Pulse width limited by max. junction temperature.
**Table 4: Control part**
|**Symbol**|**Parameter**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|---|
|VOUT|Output voltage applied amongOUTU, OUTV, OUTW- GND|Vboot- 21|Vboot+ 0.3|V|
|VCC|Low voltagepower supply|- 0.3|21|V|
|VCIN|Comparator input voltage|- 0.3|VCC+ 0.3|V|
|Vop+|Op-ampnon-invertinginput|- 0.3|VCC+ 0.3|V|
|Vop-|Op-ampinvertinginput|- 0.3|VCC+ 0.3|V|
|Vboot|Bootstrapvoltage|- 0.3|620|V|
|VIN|Logic input voltage applied amongHIN, LIN and GND|- 0.3|15|V|
|𝑉𝑇/𝑆𝐷
̅̅̅̅/𝑂𝐷|Open-drain voltage|- 0.3|15|V|
|∆VOUT/dT|Allowed output slew rate||50|V/ns|
**Table 5: Total system**
|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VISO|Isolation withstand voltage applied between each pin and heatsink
plate (AC voltage, t = 60 s)|1000|V|
|Tj|Power chipoperating junction temperature|-40 to 150|°C|
|TC|Module case operation temperature|-40 to 125|°C|
## **2.2 Thermal data**
**Table 6: Thermal data**
|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rth(j-c)|Thermal resistancejunction-case|12|°C/W|
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**Electrical characteristics**
## **3 Electrical characteristics**
## **3.1 Inverter part**
TJ = 25 °C unless otherwise specified
**Table 7: Static**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|IDSS|Zero-gate voltage drain current|VDS= 500 V, VCC= 15 V,
VBoot= 15 V|||1|mA|
|V(BR)DSS|Drain-source breakdown
voltage|VCC= Vboot= 15 V,
VIN_(1)_= 0 V, ID= 1 mA|500|||V|
|RDS(on)|Static drain-source turn-on
resistance|VCC= Vboot= 15 V,
VIN_(1)_= 0 - 5 V, ID= 1.2 A||1.5|1.7|Ω|
|VSD|Drain-source diode forward
voltage|VIN_(1)_= 0 “logic state”,
ID= 2 A||0.9|1.6|V|
## **Notes:**
(1)Applied among HINx, LINx and GND for x = U, V, W.
**Table 8: Inductive load switching time and energy**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ton_(1)_|Turn-on time|VDD= 300 V,
VCC= Vboot= 15 V,
VIN_(2)_= 0 - 5 V, IC= 1.2 A
(see_Figure 4: "Switching time_
_definition"_)|-|267|-|ns|
|tc(on)_(1)_|Crossover time (on)||-|153|-||
|toff_(1)_|Turn-off time||-|265|-||
|tc(off)_(1)_|Crossover time (off)||-|46|-||
|trr|Reverse recoverytime||-|192|-||
|Eon|Turn-on switchingenergy||-|61|-|µJ|
|Eoff|Turn-off switching energy||-|4|-||
## **Notes:**
(1)tON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of MOSFET itself under the internally given gate driving conditions.
(2)Applied among HINx, LINx and GND for x = U, V, W.
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**Electrical characteristics**
**Figure 3: Switching time test circuit**
**==> picture [406 x 509] intentionally omitted <==**
**----- Start of picture text -----**
5V
Input
0V
Ic
+Vcc LIN Vboo t Vboot>Vcc
RSD
+5V SD/OD +
HIN HVG -
VCC L
OUT
+
LVG Vds +
- C Vdd
-
GND
GIPD161120151702RV
Figure 4: Switching time definition
100% ID 100%ID
t rr
VDS ID ID VDS
VIN VIN
t ON t OFF
t C(ON) t C(OFF)
VIN(ON) 10% ID 90%ID 10%VDS VIN(OFF) 10%VDS 10%ID
(a) turn-on (b) turn-off AM09223V2
**----- End of picture text -----**
_Figure 4: "Switching time definition"_ refers to HIN, LIN inputs (active high).
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**Electrical characteristics**
## **3.2 Control part**
VCC = 15 V unless otherwise specified
**Table 9: Low voltage power supply**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VCC_hys|VCCUV hysteresis||1.2|1.5|1.8|V|
|VCC_thON|VCCUV turn-ON threshold||11.5|12|12.5|V|
|VCC_thOFF|VCCUV turn-OFF threshold||10|10.5|11|V|
|Iqccu|Undervoltage quiescent
supplycurrent|VCC= 10 V, T/SD
̅̅̅̅/OD = 5 V;
LIN = 0 V; HIN= 0, CIN= 0|||150|µA|
|Iqcc|Quiescent current|Vcc= 15 V, T/SD
̅̅̅̅/OD = 5 V;
LIN = 0 V; HIN= 0, CIN= 0|||1|mA|
|Vref|Internal comparator (CIN)
reference voltage||0.5|0.54|0.58|V|
**Table 10: Bootstrapped voltage**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VBS_hys|VBSUV hysteresis||1.2|1.5|1.8|V|
|VBS_thON|VBSUV turn-ON threshold||11.1|11.5|12.1|V|
|VBS_thOFF|VBSUV turn-OFF threshold||9.8|10|10.6|V|
|IQBSU|Undervoltage VBSquiescent
current|VBS< 9 V T/SD
̅̅̅̅/OD = 5 V;
LIN = 0 V and HIN = 5 V;
CIN= 0||70|110|µA|
|IQBS|VBSquiescent current|VBS= 15 V T/SD
̅̅̅̅/OD = 5 V;
LIN = 0 V and HIN = 5 V;
CIN= 0||200|300|µA|
|RDS(on)|Bootstrap driver on-
resistance|LVG ON||120||Ω|
## **Table 11: Logic inputs**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vil|Low logic level voltage||||0.8|V|
|Vih|High logic level voltage||2.25|||V|
|IHINh|HIN logic “1” input bias current|HIN = 15 V|20|40|100|µA|
|IHINI|HIN logic “0” input bias current|HIN = 0 V|||1|µA|
|ILINI|LIN logic “1” input bias current|LIN = 15 V|20|40|100|µA|
|ILINh|LIN logic “0” input bias current|LIN = 0 V|||1|µA|
|ISDh|SD
logic “0” input bias
current|SD
̅̅̅̅= 15 V|220|295|370|µA|
|ISDI|SD
logic “1” input bias
current|SD
̅̅̅̅= 0 V|||3|µA|
|Dt|Dead time|See_Figure 9: "Dead time_
_and interlocking_
_waveform definitions"_||180||ns|
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**STIPNS2M50T-H**
**Electrical characteristics**
**Table 12: Op-amp characteristics**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vio|Input offset voltage|Vic= 0 V, Vo= 7.5 V|||6|mV|
|Iio|Input offset current|Vic= 0 V, Vo= 7.5 V||4|40|nA|
|Iib|Input bias current_(1)_|||100|200|nA|
|VOL|Low level output voltage|RL= 10 kΩ to VCC||75|150|mV|
|VOH|High level output voltage|RL= 10 kΩ to GND|14|14.7||V|
|Io|Output short-circuit current|Source, Vid= +1 V;
Vo= 0 V|16|30||mA|
|||Sink, Vid= -1 V; Vo= VCC|50|80||mA|
|SR|Slew rate|Vi= 1 - 4 V; CL= 100 pF;
unity gain|2.5|3.8||V/µs|
|GBWP|Gain bandwidthproduct|Vo= 7.5 V|8|12||MHz|
|Avd|Large signal voltagegain|RL= 2 kΩ|70|85||dB|
|SVR|Supplyvoltage rejection ratio|vs. VCC|60|75||dB|
|CMRR|Common mode rejection
ratio||55|70||dB|
## **Notes:**
- (1)The direction of the input current is out of the IC.
**Table 13: Sense comparator characteristics**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Iib|Input bias current|VCIN= 1 V|||1|µA|
|Vod|Open-drain low level output
voltage|Iod= 3 mA|||0.5|V|
|RON_OD|Open-drain low level output
resistance|Iod= 3 mA||166||Ω|
|RPD_SD|SD
̅̅̅̅pull-down resistor_(1)_|||125||kΩ|
|td_comp|Comparator delay|T/SD
̅̅̅̅/OD pulled to 5 V
through 100 kΩ resistor||90|130|ns|
|SR|Slew rate|CL= 180pF; Rpu= 5 kΩ||60||V/µs|
|tsd|Shutdown to high- / low-side
driverpropagation delay|VOUT= 0, Vboot= VCC,
VIN= 0 to 3.3 V|50|125|200|ns|
|tisd|Comparator triggering to high-
/ low-side driver turn-off
propagation delay|Measured applying a
voltage step from 0 V to
3.3 V to pin CIN|50|200|250||
## **Notes:**
- (1)Equivalent values are as a result of the resistances of three drivers in parallel.
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**Electrical characteristics**
|**50T-H**
**Electrical **|**50T-H**
**Electrical **|**50T-H**
**Electrical **|**50T-H**
**Electrical **|**characteristics**|**characteristics**|
|---|---|---|---|---|---|
|**Table 14: Truth table**||||||
|**Conditions**|**Logic input (VI) **|||**Output**||
||**T/**𝐒𝐃
̅̅̅̅**/OD**|**LIN**|**HIN**|**LVG**|**HVG**|
|Shutdown enable half-bridge tri-state|L|X_(1)_|X_(1)_|L|L|
|Interlockinghalf-bridge tri-state|H|H|H|L|L|
|0 “logic state” half-bridge tri-state|H|L|L|L|L|
|1 “logic state” low-side direct driving|H|H|L|H|L|
|1 “logic state” high-side direct driving|H|L|H|L|H|
## **Notes:**
(1)X: do not care.
## **3.2.1 NTC thermistor**
**==> picture [182 x 11] intentionally omitted <==**
**----- Start of picture text -----**
Figure 5: Internal structure of ̅̅̅̅̅𝐒𝐃 and NTC
**----- End of picture text -----**
**==> picture [406 x 183] intentionally omitted <==**
**----- Start of picture text -----**
Vbias
R SD
VT/SD/OD LIN Vboot
SD/OD
C SD NTC HIN HVG
VCC
OUT
RPD_SD
LVG
GND CIN
**----- End of picture text -----**
RPD_SD: equivalent value as result of resistances of three drivers in parallel.
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**STIPNS2M50T-H**
**Electrical characteristics**
**Figure 6: Equivalent resistance (NTC//RPD_SD)**
**Figure 7: Equivalent resistance (NTC//RPD_SD) zoom**
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**Electrical characteristics**
**Figure 8: Voltage of T/** 𝐒𝐃̅̅̅̅ **/OD pin according to NTC temperature**
**==> picture [407 x 295] intentionally omitted <==**
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**Electrical characteristics**
## **3.3 Waveform definitions**
**Figure 9: Dead time and interlocking waveform definitions**
**==> picture [406 x 349] intentionally omitted <==**
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**Smart shutdown function**
## **4 Smart shutdown function**
The device integrates a comparator for fault sensing purposes. The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting input on pin (CIN) can be connected to an external shunt resistor for the overcurrent protection.
When the comparator triggers, the device is set to the shutdown state and both of its outputs are set to low level, causing the half-bridge to enter a tri-state.
In common overcurrent protection architectures, the comparator output is usually connected to the shutdown input through an RC network so to provide a mono-stable circuit which implements a protection time following to a fault condition.
Our smart shutdown architecture immediately turns off the output gate driver in case of overcurrent through a preferential path for the fault signal which directly switches off the outputs. The time delay between the fault and output shutdown no longer depends on the RC values of the external network connected to the shutdown pin. At the same time, the DMOS connected to the open-drain output (pin T/ ̅̅̅̅SD /OD) is turned on by the internal logic, which holds it on until the shutdown voltage is well below the minimum value of logic input threshold (Vil).
Besides, the smart shutdown function allows the real disable time to be increased without rising the constant time of the external RC network.
An NTC thermistor for temperature monitoring is internally connected in parallel to the ̅̅̅̅SD pin. To avoid undesired shutdown, keep the voltage 𝑉𝑇/𝑆𝐷̅̅̅̅/𝑂𝐷 higher than the high-level ̅̅̅̅ logic threshold by setting the pull-up resistor 𝑅𝑆𝐷 to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU power supplies respectively.
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**Smart shutdown function**
**STIPNS2M50T-H**
**Figure 10: Smart shutdown timing waveforms**
**==> picture [253 x 281] intentionally omitted <==**
**----- Start of picture text -----**
comp Vref
CP+
HIN/LIN
PROTECTION
HVG/LVG
SD/OD
open-drain gate
(internal)
disable time
Fast shutdown:
the driver outputs are set to the SD state as soon as the comparator
triggers even if the SD signal hasn’t reached the lowest input threshold
**----- End of picture text -----**
**==> picture [396 x 162] intentionally omitted <==**
**----- Start of picture text -----**
An approximation of the disable time is given by:
Vbias SHUTDOWN CIRCUIT
R SD
VT/SD/OD T/SD/ OD
SMART SD
C SD
LOGIC
NTC RPD_SD RON_OD
**----- End of picture text -----**
**==> picture [67 x 6] intentionally omitted <==**
**----- Start of picture text -----**
GIPG080920140931FSR
**----- End of picture text -----**
Please refer to _Table 13: "Sense comparator characteristics"_ for internal propagation delay time details.
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**Application circuit example**
## **5 Application circuit example**
**Figure 11: Application circuit example**
**==> picture [406 x 523] intentionally omitted <==**
**----- Start of picture text -----**
MICROCONTROLLER
GADG100620160912FSR
PWR_GND
+ -
VDC
Cvdc
C4
M
Rshun t
DZ2 DZ2 DZ2
C3 C3 C3
Cboot U
Cboot V Cboot W
VbootU)(17 (18)P (19)U,OUT U NU)(20 VbootV)(21 (22)V,OUT V NV)(23 (24)VbootW (25)W,OUT W (26)NW
HVG Vboot HVG OUT LVG OP+ Vboot HVG OUT LVG
LIN HIN VCC GND LIN HIN OP- GND LIN HIN VCC GND
NTC
LinU(16) HinU(14) VccU(13) Cin(12) CSF LinV(11) HinV(10) VccV(9) OP-(8) OPC OPOUT(7) OP+)(6 LinW(5) HinW(4 ) VccW(3) GND)(1
C1 T/SD/OD(15 ) C1 C1 C1 C1 C1 T/SD/OD(2 ) SGN_GND DZ1
RSF R4 R5 C AD C2
R1 R1 R1
RS R1 R1 R1 Cvcc
R2 R3 RSD CSD
Vcc
+ -
5V/3.3V R1 5V/3.3V
RS
LIN U HIN U LIN V HIN V
SD Temp.Monitoring
RS
Vboot OUT LVG CIN
SD/OD SD/OD VCC OPOUT SD/OD
ADC LIN W HIN W
**----- End of picture text -----**
Application designers are free to use a different scheme according to the device specifications.
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**STIPNS2M50T-H**
**Application circuit example**
## **5.1 Guidelines**
- Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is builtin for each input. To prevent input signal oscillations, the wiring of each input should be as short as possible and the use of RC filters (R1, C1) on each input signal is suggested. The filters should be within a time constant of about 100 ns and placed as close as possible to the IPM input pins.
- The use of a bypass capacitor CVCC (aluminum or tantalum) can help to reduce the transient circuit demand on the power supply. Besides, to reduce high frequency switching noise distributed on the power lines, a decoupling capacitor C2 (100 to 220 nF, with low ESR and low ESL) should be placed as close as possible to the Vcc pin and in parallel with the bypass capacitor.
- The use of an RC filter (RSF, CSF) for circuit malfunction protection is recommended. The time constant (RSF x CSF) should be set to 1 μs and the filter must be placed as close as possible to the CIN pin.
- The ̅̅̅̅ SD is an input/output pin (open-drain type if used as output). A built-in thermistor NTC is internally connected between the ̅̅̅̅ SD pin and GND. The VSD-GND voltage decreases as the temperature increases, due to the RSD pull-up resistor. In order to keep the voltage always higher than the high level logic threshold, the pull-up resistor is suggested to be set to 1 kΩ or 2.2 kΩ for an MCU power supply of 3.3 V or 5 V respectively. The CSD capacitor of the filter on ̅̅̅̅SD should be fixed no higher than 3.3 nF in order to assure an ̅̅̅̅ SD activation time of τ1 ≤ 500 ns and the filter should be placed as close as possible to the ̅̅̅̅ SD pin.
- The decoupling capacitor C3 (from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with each Cboot, filters high frequency disturbance. Both Cboot and C3 (if present) should be placed as close as possible to the U, V, W and Vboot pins. Bootstrap negative electrodes should be connected to the U, V, W terminals directly and separated from the main output wires.
- To prevent overvoltage on the Vcc pin, a Zener diode (Dz1) can be used. Similarly, a Zener diode (Dz2) can be placed on the Vboot pin in parallel with each Cboot.
- The use of decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor Cvdc is useful to prevent surge destruction. Both capacitors C4 and Cvdc should be placed as close as possible to the IPM (C4 has priority over Cvdc).
- By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an optocoupler is possible.
- Use low inductance shunt resistors for phase leg current sensing.
- In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND should be as short as possible.
- The connection of SGN_GND to PWR_GND to one point only (close to the shunt resistor terminal) can help to reduce the impact of power ground fluctuation.
These guidelines ensure the device specifications for application designs. For further details, please refer to the relevant application note.
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**Application circuit example**
**Table 15: Recommended operating conditions**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VPN|Supply voltage|Applied among P-Nu, Nv,
Nw||300|400|V|
|VCC|Control supplyvoltage|Applied to VCC-GND|13.5|15|18|V|
|VBS|High-side bias voltage|Applied to VBOOTi-OUTifor
i = U, V, W|13||18|V|
|tdead|Blanking time to prevent
arm-short|For each input signal|1|||µs|
|fPWM|PWM input signal|-40 °C < Tc< 100 °C
-40 °C < Tj< 125 °C|||25|kHz|
|TC|Case operation temperature||||100|°C|
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**Package information**
## **6 Package information**
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark.
## **6.1 NSDIP-26L package information**
**Figure 12: NSDIP-26L package outline**
**==> picture [408 x 457] intentionally omitted <==**
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**Package information**
**Table 16: NSDIP-26L package mechanical data**
|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|||3.45|
|A1|0.10||0.25|
|A2|3.00|3.10|3.20|
|A3|1.70|1.80|1.90|
|b|0.47||0.57|
|b1|0.45|0.50|0.55|
|b2|0.63||0.67|
|c|0.47||0.57|
|c1|0.45|0.50|0.55|
|D|29.05|29.15|29.25|
|D1|0.70|||
|D2|0.45|||
|D3|0.90|||
|D4|||29.65|
|E|12.35|12.45|12.55|
|E1|16.70|17.00|17.30|
|E2|0.35|||
|e|1.70|1.80|1.90|
|e1|2.40|2.50|2.60|
|L|1.24|1.39|1.54|
|L1|1.00|1.15|1.30|
|L2||0.25 BSC||
|L3||2.275 REF||
|R1|0.25|0.40|0.55|
|R2|0.25|0.40|0.55|
|S||0.39|0.55|
|ϴ|0°||8°|
|ϴ1||3° BSC||
|ϴ2|10°|12°|14°|
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**Package information**
**Figure 13: NSDIP-26L recommended footprint (dimensions are in mm)**
**==> picture [408 x 247] intentionally omitted <==**
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**Revision history**
## **7 Revision history**
**Table 17: Document revision history**
|**Date**|**Revision**|**Changes**|
|---|---|---|
|19-Apr-2017|1|Initial release|
|04-Jan-2018|2|Datasheet status promoted from preliminary to production data.
Updated features on cover page.
Updated_Table 3: "Inverter part"_,_Table 5: "Total system"_,_Table 6:_
_"Thermal data"_and_Table 13: "Sense comparator characteristics"_.
Updated_Section 6.1: "NSDIP-26L package information"_.|
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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY**
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
- © 2018 STMicroelectronics – All rights reserved
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## Links
- [View this product on Novapart](https://novapart.co/products/STIPNS2M50T-H/intelligent-power-module-ipm-mosfet-500-v-2-a-1-kv)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/stmicroelectronics/stipns2m50t-h/power-module-mosfet-2a-500v-nsdip/dp/2980953)
---
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