# Power MOSFET, N Channel, 40 V, 200 A, 800 µohm, H2PAK-2, Surface Mount

![Product image](https://novapart.co/image/farnell:2532275/)

**URL**: https://novapart.co/products/STH410N4F7-2AG/power-mosfet-n-channel-40-v-200-a-800-ohm-h2pak-2
**SKU**: STH410N4F7-2AG
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €2.1400
**Stock**: 10+
**Lead Time**: 308 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:200A; Drain Source Voltage Vds:40V; On Resistance Rds(on):800µohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4.5V; Powe

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | AEC-Q101 |
| Power Dissipation | 365W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | H2PAK-2 |
| Drain Source Voltage Vds | 40V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 200A |
| Drain Source On State Resistance | 800µohm |
| Gate Source Threshold Voltage Max | 4.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2532275/)

## **STH410N4F7-2AG, STH410N4F7-6AG** 

Automotive-grade N-channel 40 V, 0.8 mΩ typ., 200 A STripFET™ F7 Power MOSFETs in H²PAK-2 and H²PAK-6 packages 

Datasheet - production data 

## **Features** 

|**Order code**<br>**VDS**<br>**RDS(on)**<br>**max.**<br>**ID**<br>**PTOT**<br>STH410N4F7-2AG<br>40 V<br>1.1 mΩ<br>200 A<br>365 W<br>STH410N4F7-6AG<br><br>Designed for automotive applications and<br>~~—s~~|**Order code**<br>**VDS**<br>**RDS(on)**<br>**max.**<br>**ID**<br>**PTOT**<br>STH410N4F7-2AG<br>40 V<br>1.1 mΩ<br>200 A<br>365 W<br>STH410N4F7-6AG<br><br>Designed for automotive applications and<br>~~—s~~|
|---|---|
|AEC-Q101 qualified||



- Among the lowest RDS(on) on the market 

- Excellent figure of merit (FoM) 

- Low Crss/Ciss ratio for EMI immunity 

- High avalanche ruggedness 

**Figure 1: Internal schematic diagram** 

## **Applications** 

- Switching applications 

## **Description** 

This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STH410N4F7-2AG<br>STH410N4F7-6AG|410N4F7|H²PAK-2|Tape And Reel|
|||H²PAK-6||



This is information on a product in full production. 

_www.st.com_ 

February 2016 

DocID027734 Rev 4 

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|**Contents**<br>**STH410N4F7-2AG, STH410N4F7-6AG**|**Contents**<br>**STH410N4F7-2AG, STH410N4F7-6AG**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>H²PAK-2 package information ......................................................... 10|
||4.2<br>H²PAK-6 package information ......................................................... 13|
||4.3<br>H²PAK packing information ............................................................. 16|
|**5**|**Revision history ............................................................................ 18**|



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**STH410N4F7-2AG, STH410N4F7-6AG** 

**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|40|V|
|VGS|Gate-source voltage|±20|V|
|ID<br>_(1)_|Drain current (continuous) at Tcase= 25 °C|200|A|
||Drain current (continuous) at Tcase= 100 °C|200||
|IDM<br>_(2)_|Drain current (pulsed)|800|A|
|PTOT|Total dissipation at Tcase= 25 °C|365|W|
|EAS<br>_(3)_|Singlepulse avalanche energy|1.9|J|
|Tstg|Storage temperature range|-55 to 175|°C|
|Tj|Operating junction temperature range|||



## **Notes:** 

(1) Current is limited by package, the current capability of the silicon is 420 A at 25 °C. 

(2) Pulse width is limited by safe operating area. 

(3) Tj ≤ 175 °C, Iav=80A 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|0.41|°C/W|
|Rthj-pcb<br>_(1)_|Thermal resistancejunction-pcb|35||



## **Notes:** 

(1) When mounted on a 1-inch² FR-4 board, 2oz Cu. 

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**STH410N4F7-2AG, STH410N4F7-6AG** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(Tcase = 25 °C unless otherwise specified) 

**Table 4: Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 250 µA|40|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= 40 V|||10|µA|
|||VGS= 0 V, VDS= 40 V,<br>Tcase= 125 °C|||100||
|IGSS|Gate-bodyleakage current|VDS= 0 V, VGS=  20 V|||200|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|2.5||4.5|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID= 90 A||0.8|1.1|mΩ|



**Table 5: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 25 V, f = 1 MHz,<br>VGS= 0 V|-|11500|-|pF|
|Coss|Output capacitance||-|3500|-||
|Crss|Reverse transfer<br>capacitance||-|390|-||
|Qg|Totalgate charge|VDD= 20 V, ID= 180 A,<br>VGS= 10 V (see_Figure 14:_<br>_"Test circuit for gate charge_<br>_behavior"_)|-|141|-|nC|
|Qgs|Gate-source charge||-|65|-||
|Qgd|Gate-drain charge||-|27|-||



**Table 6: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 20 V, ID= 90 A<br>RG= 4.7 Ω, VGS= 10 V (see<br>_Figure 13: "Test circuit for_<br>_resistive load switching times"_<br>and_Figure 18: "Switching time_<br>_waveform"_)|-|35|-|ns|
|tr|Rise time||-|198|-||
|td(off)|Turn-off delaytime||-|108|-||
|tf|Fall time||-|44.2|-||



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**STH410N4F7-2AG, STH410N4F7-6AG** 

**Electrical characteristics** 

## **Table 7: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD<br>_(1)_|Source-drain current||-||200|A|
|VSD<br>_(2)_|Forward on voltage|VGS= 0 V, ISD= 90 A|-||1.3|V|
|trr|Reverse recoverytime|ISD= 180 A, di/dt = 100 A/µs,<br>VDD= 32 V, Tj= 25 °C (see_Figure_<br>_15: "Test circuit for inductive load_<br>_switching and diode recovery_<br>_times"_)|-|74.4||ns|
|Qrr|Reverse recovery<br>charge||-|115||nC|
|IRRM|Reverse recovery<br>current||-|3.1||A|



## **Notes:** 

(1) Limited by package, 420 A current allowed by silicon. 

(2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. 

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## **Electrical characteristics** 

## **2.2 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

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Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


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**Figure 4: Output characteristics Figure 5: Transfer characteristics** 

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**Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance** 

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**----- Start of picture text -----**<br>
STH410N4F7-2AG, STH410N4F7-6AG Electrical characteristics<br>Figure 8: Capacitance variations  Figure 9: Normalized gate threshold voltage<br>vs temperature<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Figure 10: Normalized on-resistance vs  Figure 11: Normalized V(BR)DSS vs temperature<br>temperature<br>**----- End of picture text -----**<br>


**Figure 12: Source-drain diode forward characteristics** 

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 393] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Test circuit for resistive load  Figure 14: Test circuit for gate charge<br>switching times  behavior<br>Figure 15: Test circuit for inductive load<br>Figure 16: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>**----- End of picture text -----**<br>


**==> picture [403 x 177] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 18: Switching time waveform<br>Figure 17: Unclamped inductive waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package information** 

## **4.1 H²PAK-2 package information** 

**Figure 19: H²PAK-2 package outline** 

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**----- Start of picture text -----**<br>
8159712_D<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 8: H²PAK-2 package mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.30|-|4.80|
|A1|0.03||0.20|
|C|1.17||1.37|
|e|4.98||5.18|
|E|0.50||0.90|
|F|0.78||0.85|
|H|10.00||10.40|
|H1|7.40||7.80|
|L|15.30||15.80|
|L1|1.27||1.40|
|L2|4.93||5.23|
|L3|6.85||7.25|
|L4|1.5||1.7|
|M|2.6||2.9|
|R|0.20||0.60|
|V|0°||8°|



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**Package information** 

**Figure 20: H²PAK-2 recommended footprint** 

**==> picture [406 x 389] intentionally omitted <==**

**----- Start of picture text -----**<br>
8159712_D<br>**----- End of picture text -----**<br>


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**Package information** 

## **4.2 H²PAK-6 package information** 

**Figure 21: H²PAK-6 package outline** 

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**Package information** 

**Table 9: H²PAK-6 package mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.30|-|4.80|
|A1|0.03||0.20|
|C|1.17||1.37|
|e|2.34||2.74|
|e1|4.88||5.28|
|e2|7.42||7.82|
|E|0.45||0.60|
|F|0.50||0.70|
|H|10.00||10.40|
|H1|7.40||7.80|
|L|14.75||15.25|
|L1|1.27||1.40|
|L2|4.35||4.95|
|L3|6.85||7.25|
|L4|1.5||1.75|
|M|1.90||2.50|
|R|0.20||0.60|
|V|0°||8°|



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**Package information** 

**Figure 22: H²PAK-6 recommended footprint** 

Dimensions are in mm. 

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**Package information** 

## **4.3 H²PAK packing information** 

**Figure 23: Tape outline** 

**==> picture [407 x 338] intentionally omitted <==**

**Figure 24: Reel outline** 

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**----- Start of picture text -----**<br>
T<br>REE L DIMENS IONS<br>40 mm min.<br>Access hole<br>At slot location<br>B<br>D<br>C<br>N<br>A<br>G measured<br>Tape slot<br>In core for<br>Full radius At hub<br>Tape start<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 10: Tape and reel mechanical data** 

||**Tape**|||**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**m**|**m**|**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|10.5|10.7|A||330|
|B0|15.7|15.9|B|1.5||
|D|1.5|1.6|C|12.8|13.2|
|D1|1.59|1.61|D|20.2||
|E|1.65|1.85|G|24.4|26.4|
|F|11.4|11.6|N|100||
|K0|4.8|5.0|T||30.4|
|P0|3.9|4.1||||
|P1|11.9|12.1|Basequantity||1000|
|P2|1.9|2.1|Bulkquantity||1000|
|R|50|||||
|T|0.25|0.35||||
|W|23.7|24.3||||



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**STH410N4F7-2AG, STH410N4F7-6AG** 

**Revision history** 

## **5 Revision history** 

**Table 11: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|10-Apr-2015|1|First release.|
|13-May-2015|2|Updated Static.|
|04-Dec-2015|3|Updated note 1 in Table 2: "Absolute maximum ratings",<br>Figure 2: "Safe operating area" and Figure 3: "Thermal impedance".|
|17-Feb-2016|4|Modified:_Table 2: "Absolute maximum ratings"_,_Table 4: "Static"_<br>Modified:_Figure 2: "Safe operating area"_<br>Minor text changes|



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## **STH410N4F7-2AG, STH410N4F7-6AG** 

## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

DocID027734 Rev 4 

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## Links

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- [Supplier page](https://es.farnell.com/stmicroelectronics/sth410n4f7-2ag/mosfet-n-ch-40v-200a-h2pak/dp/2532275)
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