# Power MOSFET, N Channel, 100 V, 180 A, 3900 µohm, H2PAK-2, Surface Mount

![Product image](https://novapart.co/image/farnell:2098248/)

**URL**: https://novapart.co/products/STH180N10F3-2/power-mosfet-n-channel-100-v-180-a-3900-ohm-h2pak
**SKU**: STH180N10F3-2
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.6500
**Stock**: 500+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:180A; Drain Source Voltage Vds:100V; On Resistance Rds(on):0.0039ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:2V; Po

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 4Pins |
| Channel Type | N Channel |
| Product Range | StripFET F3 |
| Qualification | - |
| Power Dissipation | 315W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | H2PAK-2 |
| Drain Source Voltage Vds | 100V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 180A |
| Drain Source On State Resistance | 3900µohm |
| Gate Source Threshold Voltage Max | 2V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2098248/)

**STH180N10F3-2** 

Datasheet 

‑ N channel 100 V, 3.9 mΩ typ., 180 A STripFET F3 ‑ Power MOSFET in H²PAK 2 package 

**==> picture [157 x 117] intentionally omitted <==**

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TAB<br>2<br>3<br>1<br>H [2] PAK-2<br>**----- End of picture text -----**<br>


## **Features** 

|**Order code**|**VDS**|**RDS(on) max.**|**ID**|
|---|---|---|---|
|STH180N10F3-2|100 V|4.5 mΩ|180 A|



- Ultra low on-resistence 

- 100% avalanche tested 

## **Applications** 

- Switching applications 

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D(TAB)<br>G(1)<br>S(2,3)<br>NCHG1DTABS23<br>Product status link<br>STH180N10F3-2<br>**----- End of picture text -----**<br>


## **Description** 

This device is an N-channel Power MOSFET developed using STripFET F3 technology. It is designed to minimize on-resistance and gate charge to provide superior switching performance. 

|**Product summary**|**Product summary**|
|---|---|
|**Order code**<br>ST|H180N10F3-2|
|**Marking**|180N10F3|
|**Package**|H2PAK-2|
|**Packing**<br>T|ape and reel|



**DS7317** - **Rev 3** - **March 2022** For further information contact your local STMicroelectronics sales office. 

www.st.com 

**STH180N10F3-2 Electrical ratings** 

## **1** 

## **Electrical ratings** 

**Table 1. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|100|V|
|VGS|Gate-source voltage|± 20|V|
|ID (1)|Drain current (continuous) at TC= 25 °C|180|A|
|ID (1)|Drain current (continuous) at TC= 100 °C|120|A|
|IDM (2)|Drain current (pulsed)|720|A|
|PTOT|Total power dissipation at TC= 25 °C|315|W|
||Derating factor|2.1|W/ºC|
|dv/dt|Peak diode recovery voltage slope|20|V/ns|
|EAS (3)|Single pulse avalanche energy|350|mJ|
|TJ|Operating junction temperature|-55 to 175|°C|
|Tstg|Storage temperature||°C|



_1. Current limited by package_ 

_2. Pulse width limited by safe operating area_ 

_3. Starting TJ = 25 °C, ID = 80, VDD = 50 V_ 

## **Table 2. Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|RthJC|Thermal resistance, junction-to-case|0.48|°C/W|
|RthJB (1)|Thermal resistance, junction-to-board|35|°C/W|



_1. When mounted on FR-4 board of 1 inch², 2 oz Cu_ 

**DS7317** - **Rev 3** 

**page 2/13** 

**STH180N10F3-2 Electrical characteristics** 

## **2 Electrical characteristics** 

TC= 25 °C unless otherwise specified. 

## **Table 3. On/off-state** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown voltage<br>(VGS= 0 V)|ID= 250 µA|100|||V|
|IDSS|Zero gate voltage drain current<br>(VGS= 0 V)|VDS= 100 V|||10|µA|
|||VDS= 100 V; TC= 125 °C|||100|µA|
|IGSS|Gate body leakage current<br>(VDS= 0 V)|VGS= ±20 V|||±200|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 µA|2||4|V|
|RDS(on)|Static drain-source on- resistance|VGS= 10 V, ID= 60 A||3.9|4.5|mΩ|



**Table 4. Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 25 V, f = 1 MHz,<br>VGS= 0 V|-|6665|-|pF|
|Coss|Output capacitance|||786||pF|
|Crss|Reverse transfer capacitance|||49||pF|
|Qg|Total gate charge|VDD= 50 V, ID= 120 A<br>VGS= 10 V<br>SeeFigure 13. Test circuit for gate charge<br>behavior||114.6||nC|
|Qgs|Gate-source charge|||38.8||nC|
|Qgd|Gate-drain charge|||31.9||nC|



**Table 5. Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 50 V, ID= 60 A,<br>RG= 4.7 Ω, VGS= 10 V<br>SeeFigure 12. Test circuit for resistive<br>load switching times|-|25.6|-|ns|
|tr|Rise time|||97.1||ns|
|td(off)|Turn-off delay time|||99.9||ns|
|tf|Fall time|||6.9||ns|



**DS7317** - **Rev 3** 

**page 3/13** 

**STH180N10F3-2 Electrical characteristics** 

## **Table 6. Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||180|A|
|ISDM (1)|Source-drain current (pulsed)||||720|A|
|VSD (2)|Forward on voltage|ISD= 120 A, VGS= 0 V|||1.5|V|
|trr|Reverse recovery time|ISD= 120 A,<br>di/dt = 100 A/µs,<br>VDD= 80 V, TJ= 150 °C||83.4||ns|
|Qrr|Reverse recovery charge|||295.7||nC|
|IRRM|Reverse recovery current|||7.1||A|



_1. Pulse width limited by safe operating area_ 

_2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%_ 

**DS7317** - **Rev 3** 

**page 4/13** 

**STH180N10F3-2 Electrical characteristics (curves)** 

## **2.1 Electrical characteristics (curves)** 

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Figure 1. Safe operating area Figure 2. Thermal impedance<br>ID GIPG110620141143SA 280tok<br>K<br>(A)<br>ᵟ [=][0.5]<br>100 0.2<br>0.1<br>0.05<br>10 100µs 10-1<br>0.02<br>Z th = k*R thJC<br>0.01 δ = t / Ƭ<br>1 p<br>1ms<br>Tc=25°CTj=175°C Single pulse t<br>0.1 Single pulse 10ms 10-2 p Ƭ<br>0.1 1 10 VDS(V) 10-5 10-4 10-3 10-2 10-1 tp [(s)]<br>DS(on)<br>Operation in this area is<br>Limited by max R<br>**----- End of picture text -----**<br>


**Figure 3. Output characteristics** 

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AM08616v1<br>ID(A)<br>VGS=10V<br>350<br>7V<br>300<br>250<br>200<br>150<br>6V<br>100<br>50<br>5V<br>0<br>0 1 2 3 4 5 6 7 8 VDS(V)<br>**----- End of picture text -----**<br>


**Figure 4. Transfer characteristics** 

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AM08617v1<br>ID(A)<br>350 VDS=2V<br>300<br>250<br>200<br>150<br>100<br>50<br>0<br>0 1 2 3 4 5 6 7 8 9 VGS(V)<br>**----- End of picture text -----**<br>


**Figure 5. Normalized V(BR)DSS vs temperature** 

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V(BR)DSS AM08618v1<br>(norm)<br>ID=1mA<br>1.10<br>1.05<br>1.00<br>0.95<br>0.90<br>-75 -25 25 75 125 175 TJ(°C)<br>**----- End of picture text -----**<br>


**Figure 6. Static drain-source on-resistance** 

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AM08626v1<br>RDS(on)<br>(mΩ)<br>VGS=10V<br>4.3<br>4.1<br>3.9<br>3.7<br>3.5<br>0 20 40 60 80 100 120 140 160 180 ID(A)<br>**----- End of picture text -----**<br>


**DS7317** - **Rev 3** 

**page 5/13** 

**STH180N10F3-2 Electrical characteristics (curves)** 

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Figure 7. Gate charge vs gate-source voltage Figure 8. Capacitance variations<br>VGS AM08620v1 C AM08621v1<br>(V) (pF)<br>VDD=50V<br>12<br>ID=120A<br>20000<br>10<br>8 15000<br>6<br>10000<br>4 Ciss<br>5000<br>2<br>Crss<br>0 Coss<br>0<br>0 20 40 60 80 100 120 140 Qg(nC)<br>0 20 40 60 80 100 VDS(V)<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Figure 9. Normalized gate threshold voltage vs<br>Figure 10. Normalized on-resistance vs temperature<br>temperature<br>VGS(th) AM08622v1 RDS(on)(norm) AM08623v1<br>(norm) ID=250µA 2.1 ID=60A<br>VGS=10V<br>1.3<br>1.9<br>1.1 1.7<br>1.5<br>0.9<br>1.3<br>1.1<br>0.7<br>0.9<br>0.5<br>0.7<br>0.5<br>0.3<br>-75 -25 25 75 125 175 TJ(°C)<br>-75 -25 25 75 125 175 TJ(°C)<br>**----- End of picture text -----**<br>


**Figure 11. Source-drain diode forward characteristics** 

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VSD AM08624v1<br>(V)<br>1.0 TJ=-55°C<br>0.9<br>0.8<br>0.7 TJ=25°C<br>0.6<br>0.5 TJ=175°C<br>0.4<br>0 20 40 60 80 100 120 ISD(A)<br>**----- End of picture text -----**<br>


**DS7317** - **Rev 3** 

**page 6/13** 

**STH180N10F3-2 Test circuits** 

## **3 Test circuits** 

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Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior<br>VDD<br>12 V 47 kΩ<br>1 kΩ<br>100 nF<br>RL 2200 3.3<br>+ μF μF VDD<br>VD VGS IG= CONST 100 Ω D.U.T.<br>VGS RG D.U.T. pulse width + 2.7 kΩ<br>2200 VG<br>pulse width μF<br>47 kΩ<br>1 kΩ<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Figure 14. Test circuit for inductive load switching and Figure 15. Unclamped inductive load test circuit<br>diode recovery times<br>A A A<br>D L<br>G D.U.T. fastdiode 100 µH VD<br>25 Ω S B B B D µF3.3 + 1000µF VDD + 2200µF 3.3µF VDD<br>G D.U.T. ID<br>+ RG S<br>_ Vi D.U.T.<br>pulse width<br>AM01470v1<br>AM01471v1<br>**----- End of picture text -----**<br>


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Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform<br>ton toff<br>V(BR)DSS td(on) tr td(off) tf<br>VD<br>90% 90%<br>IDM<br>ID 0 10% VDS 10%<br>VDD VDD VGS 90%<br>0 10%<br>AM01472v1 AM01473v1<br>**----- End of picture text -----**<br>


**DS7317** - **Rev 3** 

**page 7/13** 

**STH180N10F3-2 Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 

## **4.1 H²PAK-2 package information** 

**Figure 18. H²PAK-2 package outline** 

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8159712_9<br>**----- End of picture text -----**<br>


**DS7317** - **Rev 3** 

**page 8/13** 

**STH180N10F3-2 H²PAK-2 package information** 

**Table 7. H²PAK-2 package mechanical data** 

|**Di**|**mm**|**mm**||
|---|---|---|---|
|**m.**|**Min.**|**Typ.**|**Max.**|
|A|4.30|-|4.70|
|A1|0.03||0.20|
|C|1.17||1.37|
|D|8.95||9.35|
|e|4.98||5.18|
|E|0.50||0.90|
|F|0.78||0.85|
|F2|1.14||1.70|
|H|10.00||10.40|
|H1|7.40||7.80|
|J1|2.49||2.69|
|L|15.30||15.80|
|L1|1.27||1.40|
|L2|4.93||5.23|
|L3|6.85||7.25|
|L4|1.50||1.70|
|M|2.60||2.90|
|R|0.20||0.60|
|V|0°||8°|



**Figure 19. H²PAK-2 recommended footprint** 

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8159712_9<br>**----- End of picture text -----**<br>


_Note: Dimensions are in mm._ 

**DS7317** - **Rev 3** 

**page 9/13** 

**STH180N10F3-2 Packing information** 

## **4.2 Packing information** 

**Figure 20. Tape outline** 

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10 pitches cumulative<br>tolerance on tape +/- 0.2 mm<br>Top cover P0 D P2<br>T tape<br>E<br>F<br>K0 W<br>B0<br>HE LI<br>Bilal<br>A0 P1 D1<br>User direction of feed<br>**----- End of picture text -----**<br>


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R<br>Bending radius<br>User direction of feed<br>AM08852v2<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Figure 21. Reel outline<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
T<br>REEL DIMENSIONS<br>40 mm min.<br>Access hole<br>At slot location<br>B<br>D<br>C<br>N<br>A<br>G measured<br>Tape slot<br>In core for<br>Full radius At hub<br>Tape start<br>**----- End of picture text -----**<br>


**DS7317** - **Rev 3** 

**page 10/13** 

**STH180N10F3-2 Packing information** 

**Table 8. Tape and reel mechanical data** 

||**Tape**|**Tape**||**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Di**|**mm**||**Di**|**mm**||
|**m.**|**Min.**|**Max.**|**m.**|**Min.**|**Max.**|
|A0|10.5|10.7|A||330|
|B0|15.7|15.9|B|1.5||
|D|1.5|1.6|C|12.8|13.2|
|D1|1.59|1.61|D|20.2||
|E|1.65|1.85|G|24.4|26.4|
|F|11.4|11.6|N|100||
|K0|4.8|5.0|T||30.4|
|P0|3.9|4.1||||
|P1|11.9|12.1|Base quantity||1000|
|P2|1.9|2.1|Bulk quantity||1000|
|R|50|||||
|T|0.25|0.35||||
|W|23.7|24.3||||



**DS7317** - **Rev 3** 

**page 11/13** 

**STH180N10F3-2** 

## **Revision history** 

**Table 9. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|18-Jul-2011|1|First version|
|26-Nov-2014|2|•<br>Modified fig 2.<br>•<br>Updated package mechanical data.<br>•<br>Updated the title, features and description.|
|02-Mar-2022|3|UpdatedFigure 1. Safe operating area.<br>Minor text changes.|



**DS7317** - **Rev 3** 

**page 12/13** 

**STH180N10F3-2** 

## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2022 STMicroelectronics – All rights reserved 

**DS7317** - **Rev 3** 

**page 13/13** 



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- [Supplier page](https://es.farnell.com/stmicroelectronics/sth180n10f3-2/mosfet-n-ch-100v-120a-h2pak/dp/2098248)
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