# Intelligent Power Module (IPM), IGBT, 600 V, 30 A, 2.5 kV, SDIP, SLLIMM

![Product image](https://novapart.co/image/farnell:2807479/)

**URL**: https://novapart.co/products/STGIPS30C60-H/intelligent-power-module-ipm-igbt-600-v-30-a-25-kv
**SKU**: STGIPS30C60-H
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || Intelligent Power Modules
**Price**: €12.1400
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| Ipm Series | SLLIMM |
| Ipm Case Style | SDIP |
| Isolation Voltage | 2.5kV |
| Current Rating (Ic / Id) | 30A |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2807479/)

## **STGIPS30C60-H** ~~a~~ ~ SLLIMM™ small low-loss intelligent molded module IPM, 3-phase inverter - 30 A, 600 V short-circuit rugged IGBT 

**Datasheet** - **production data** 

## **Applications** 

- 3-phase inverters for motor drives 

- Air conditioners 

## **Description** 

**==> picture [40 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDIP-25L<br>**----- End of picture text -----**<br>


This intelligent power module provides a compact, high performance AC motor drive in a simple, rugged design. Combining ST proprietary control ICs with the most advanced short-circuitrugged IGBT system technology, this device is ideal for 3-phase inverters in applications such as motor drives and air conditioners. SLLIMM™ is a trademark of STMicroelectronics. 

## **Features** 

- IPM 30 A, 600 V 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes 

- Short-circuit rugged IGBTs 

- 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull-down / pull-up resistors 

- Undervoltage lockout 

- Internal bootstrap diode 

- Interlocking function 

- Smart shutdown function 

- Comparator for fault protection against over temperature and overcurrent 

- DBC leading to low thermal resistance 

- Isolation rating of 2500 Vrms/min 

- UL recognized: UL1557 file E81734 

**Table 1. Device summary** 

|||**Order code**|**Marking**|**Package**|**Packing**||
|---|---|---|---|---|---|---|
|||STGIPS30C60-H|GIPS30C60-H|SDIP-25L|Tube||
|April 2015||ril 2015|DocID024473 Rev 5|||1/20|



_www.st.com_ 

This is information on a product in full production. 

**Contents** 

**STGIPS30C60-H** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Internal block diagram and pin configuration  . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5**|
||2.1<br>Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
||2.2<br>Thermal data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7**|
||3.1<br>Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
||3.2<br>Waveform definitions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11|
|**4**|**Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12**|
|**5**|**Applications information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14**|
||5.1<br>Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|**6**|**Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16**|
||6.1<br>SDIP-25L package information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
||6.2<br>Packing information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|**7**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19**|



2/20 

DocID024473 Rev 5 

**STGIPS30C60-H** 

**Internal block diagram and pin configuration** 

## **1 Internal block diagram and pin configuration** 

## **Figure 1. Internal block diagram** 

**==> picture [405 x 610] intentionally omitted <==**

**----- Start of picture text -----**<br>
Pin 1<br>Pin 25<br>OUT U<br>VBOOT U P<br>LIN Vboot<br>LIN-U SD/OD HVG<br>HIN-U HIN OUT<br>U<br>VCC VCC<br>DT<br>LVG<br>CP+<br>NU<br>GND<br>OUT V<br>VBOOT V<br>P<br>LIN Vboot<br>GND SD/OD HVG<br>LIN-V HIN OUT<br>V<br>HIN-V VCC<br>DT<br>LVG<br>CP+<br>NV<br>GND<br>OUT W<br>VBOOT W<br>P<br>LIN Vboot<br>LIN-W SD/OD HVG<br>HIN-W HIN OUT<br>W<br>SD/OD VCC<br>CIN DT<br>LVG<br>Pin 16 CP+<br>NW<br>GND<br>Pin 17<br>AM05002v2<br>DocID024473 Rev 5 3/20<br>**----- End of picture text -----**<br>


**STGIPS30C60-H** 

**Internal block diagram and pin configuration** 

**Table 2. Pin description** 

|||**Table 2. Pin description**|**Table 2. Pin description**|**Table 2. Pin description**|**Table 2. Pin description**|
|---|---|---|---|---|---|
|**Pin n°**|**Symbol**|**Description**||||
|1|OUTU|High-side reference output for U phase||||
|2|VbootU|Bootstrap voltage for U phase||||
|3|LINU|Low-side logic input for U phase||||
|4|HINU|High-side logic input for U phase||||
|5|VCC|Low voltage power supply||||
|6|OUTV|High-side reference output for V phase||||
|7|Vboot V|Bootstrap voltage for V phase||||
|8|GND|Ground||||
|9|LINV|Low-side logic input for V phase||||
|10|HINV|High-side logic input for V phase||||
|11|OUTW|High-side reference output for W phase||||
|12|Vboot W|Bootstrap voltage for W phase||||
|13|LINW|Low-side logic input for W phase||||
|14|HINW|High-side logic input for W phase||||
|15|SD<br>/ OD|Shutdown logic input (active low) / open-drain (comparator output)||||
|16|CIN|Comparator input||||
|17|NW|Negative DC input for W phase||||
|18|W|W phase output||||
|19|P|Positive DC input||||
|20|NV|Negative DC input for V phase||||
|21|V|V phase output||||
|22|P|Positive DC input||||
|23|NU|Negative DC input for U phase||||
|24|U|U phase output||||
|25|P|Positive DC input||||
|**F**||**igure**|**2. Pin layout(bottom view)**|||
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4/20 

DocID024473 Rev 5 

**STGIPS30C60-H** 

**Electrical ratings** 

## **2 Electrical ratings** 

## **2.1 Absolute maximum ratings** 

**Table 3. Inverter part** 

||**Table 3. Inverterpart**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|VPN|Supply voltage applied between P - NU, NV, NW|450|V|
|VPN(surge)|Supply voltage (surge) applied between P - NU,<br>NV, NW|500|V|
|VCES|Each IGBT collector emitter voltage (VIN<br>(1)= 0)|600|V|
|± IC|Each IGBT continuous collector current<br>at TC= 25°C|30|A|
|± ICP<br>(2)|Each IGBT pulsed collector current|60|A|
|PTOT|Each IGBT total dissipation at TC= 25°C|52|W|
|tscw|Short circuit withstand time, VCE= 0.5 V(BR)CES<br>TJ= 125 °C, VCC= Vboot= 15 V, VIN (1)= 0 - 5 V|5|µs|



1. Applied between HINi, LINi and GND for i = U, V, W 

2. Pulse width limited by max junction temperature 

**Table 4. Control part** 

||**Table 4. Controlpart**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|VOUT|Output voltage applied between<br>OUTU,OUTV,OUTW- GND|Vboot- 21 to Vboot+ 0.3|V|
|VCC|Low voltage power supply|-0.3 to +21|V|
|VCIN|Comparator input voltage|-0.3 to VCC+0.3|V|
|Vboot|Bootstrap voltage applied between<br>Vboot i- OUTifor i = U, V, W|-0.3 to 620|V|
|VIN|Logic input voltage applied between HIN, LIN and<br>GND|-0.3 to 15|V|
|VSD<br>/OD|Open drain voltage|-0.3 to 15|V|
|dVOUT/dt|Allowed output slew rate|50|V/ns|



**Table 5. Total system** 

||**Table 5. Total system**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|VISO|Isolation withstand voltage applied between each<br>pin and heatsink plate (AC voltage, t = 60 sec.)|2500|V|
|Tj|Power chips operating junction temperature|-40 to 150|°C|
|TC|Module case operation temperature|-40 to 125|°C|



DocID024473 Rev 5 

5/20 

**STGIPS30C60-H** 

**Electrical ratings** 

## **2.2 Thermal data** 

**Table 6. Thermal data** 

||**Table 6. Thermal data**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|RthJC|Thermal resistance junction-case single IGBT|2.4|°C/W|
||Thermal resistance junction-case single diode|5|°C/W|



**==> picture [462 x 25] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 3. Maximum IC(RMS) current vs. switching  Figure 4. Maximum IC(RMS) current vs. fsine(1)<br>frequency  [(1)]<br>**----- End of picture text -----**<br>


**==> picture [435 x 165] intentionally omitted <==**

**----- Start of picture text -----**<br>
Ic(RMS) AM17110v1 Ic(RMS)  AM17111v1<br>    (A)   (A) 3 -phase sinusoidal PWM<br>3230 V PF = 0.6, T PN = 300 V, Modulation Index = 0.8,3-phasej  = 150  sinusoidal PWM° C, fsine  = 60 Hz 20 V PF = 0.6, T PN = 300 V, Modulation Index = 0.8,j  = 150  ° C, Tc = 100  ° C<br>28 18 fsw = 16 kHz<br>fsw = 12 kHz<br>26 Tc = 80 °C<br>16<br>24<br>22<br>14<br>20<br>fsw = 20 kHz<br>18 12<br>Tc = 100 °C<br>16<br>10<br>14<br>12 8<br>4 8 12 16 fsw (kHz) 1 10 100 fsine (Hz)<br>**----- End of picture text -----**<br>


1. Simulated curves refer to typical IGBT parameters and maximum Rthj-c. 

6/20 

DocID024473 Rev 5 

**STGIPS30C60-H** 

**Electrical characteristics** 

## **3 Electrical characteristics** 

TJ = 25 °C unless otherwise specified. 

**Table 7. Inverter part** 

|||**Table 7. Inverterpart**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Value**|||**Unit**|
||||**Min.**|**Typ.**|**Max.**||
|VCE(sat)|Collector-emitter<br>saturation voltage|VCC= Vboot= 15 V, VIN<br>(1)= 0 ÷ 5 V,<br>IC= 30 A|-|1.9|2.4|V|
|||VCC= Vboot= 15 V, VIN<br>(1)= 0 ÷ 5 V,<br>IC= 30 A, TJ= 125 °C|-|2.2|||
|ICES|Collector-cut off current<br>(VIN<br>(1)= 0 “logic state”)|VCE= 550 V, VCC= VBoot= 15 V|-||100|µA|
|VF|Diode forward voltage|VIN<br>(1)= 0 “logic state”, IC= 30 A|-||2.35|V|
|**Inductive load switching time and**||**energy**|||||
|ton|Turn-on time|VPN= 300 V,<br>VCC= Vboot= 15 V,<br>VIN<br>(1)= 0 ÷ 5 V,<br>IC= 30 A<br>(see_Figure 5_)|-|440|-|ns|
|tc(on)|Crossover time (on)||-|190|-||
|toff|Turn-off time||-|780|-||
|tc(off)|Crossover time (off)||-|135|-||
|trr|Reverse recovery time||-|505|-||
|Eon|Turn-on switching losses||-|870|-|µJ|
|Eoff|Turn-off switching losses||-|740|-||



1. Applied between HINi, LINi and GND for i = U, V, W. 

_Note:_ 

_tON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of IGBT itself under the internally given gate driving condition._ 

DocID024473 Rev 5 

7/20 

**STGIPS30C60-H** 

**Electrical characteristics** 

**==> picture [169 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 5. Switching time test circuit<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
AM06019v2<br>**----- End of picture text -----**<br>


**==> picture [405 x 304] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 6. Switching time definition<br>100% IC   100% IC<br>t rr<br>VCE IC IC VCE<br>VIN VIN<br>t ON t OFF<br>t t<br> C(ON)  C(OFF)<br>VIN(ON) 10% IC 90% IC 10% VCE VIN(OFF) 10% VCE 10% IC<br>(a) turn-on (b) turn-off AM09223V1<br>**----- End of picture text -----**<br>


_Note: Figure 4 "Switching time definition" refers to HIN, LIN inputs (active high)._ 

8/20 

DocID024473 Rev 5 

**STGIPS30C60-H** 

**Electrical characteristics** 

## **3.1 Control part** 

**Table 8. Low voltage power supply (VCC = 15 V unless otherwise specified)** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VCC_hys|VCCUV hysteresis||1.2|1.5|1.8|V|
|VCC_thON|VCCUV turn ON threshold||11.5|12|12.5|V|
|VCC_thOFF|VCCUV turn OFF threshold||10|10.5|11|V|
|Iqccu|Undervoltage quiescent<br>supply current|VCC= 10 V<br>SD<br>/OD = 5 V; LIN = 0; HIN = 0,<br>CIN= 0|||450|µA|
|Iqcc|Quiescent current|VCC= 15 V<br>SD<br>/OD = 5 V; LIN = 0; HIN = 0,<br>CIN= 0|||3.5|mA|
|Vref|Internal comparator (CIN)<br>reference voltage||0.5|0.54|0.58|V|



**Table 9. Bootstrapped voltage (VCC = 15 V unless otherwise specified)** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VBS_hys|VBS UV hysteresis||1.2|1.5|1.8|V|
|VBS_thON|VBS UV turn ON threshold||11.1|11.5|12.1|V|
|VBS_thOFF|VBS UV turn OFF threshold||9.8|10|10.6|V|
|IQBSU|Undervoltage VBSquiescent<br>current|VBS< 9 V<br>SD<br>/OD = 5 V; LIN = 0,<br>HIN = 5 V; CIN= 0||70|110|µA|
|IQBS|VBSquiescent current|VBS= 15 V<br>SD<br>/OD = 5 V; LIN = 0<br>HIN = 5 V; CIN= 0||200|300|µA|
|RDS(on)|Bootstrap driver on resistance|LIN= 5 V; HIN= 0 V||120||Ω|
|**Table 10. Logic inputs(VCC = 15 V unless otherwise specified)**|||||||
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|Vil|Low logic level voltage||0.8||1.1|V|
|Vih|High logic level voltage||1.9||2.25|V|
|IHINh|HIN logic “1” input bias current|HIN = 15 V|20|40|100|µA|
|IHINi|HIN logic “0” input bias current|HIN = 0 V|||1|µA|
|ILINh|LIN logic “1” input bias current|LIN = 15 V|20|40|100|µA|
|ILINi|LIN logic “0” input bias current|LIN = 0 V|||1|µA|
|ISDh|SD<br>logic “0” input bias current|SD<br>= 15 V|30|120|300|µA|
|ISDl|SD<br>logic “1” input bias current|SD<br>= 0 V|||3|µA|
|Dt|Dead time|see_Figure 7_and_Table 13_||1.2||µs|



DocID024473 Rev 5 9/20 

**STGIPS30C60-H** 

**Electrical characteristics** 

**Table 11. Sense comparator characteristics (VCC = 15 V unless otherwise specified)** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Iib|Input bias current|VCIN(i)= 1 V|||3|µA|
|Vol|Open-drain low-level output<br>voltage|Iod= 3 mA|||0.5|V|
|td_comp|Comparator delay|SD<br>/OD pulled to 5 V through<br>100 kΩresistor||90|130|ns|
|SR|Slew rate|CL= 180 pF; Rpu= 5 kΩ||60||V/µsec|
|tsd|Shut down to high / low side<br>driver propagation delay|VOUT = 0, Vboot = VCC,<br>VIN = 0 to 3.3 V|50|125|200|ns|
|tisd|Comparator triggering to high /<br>low side driver turn-off<br>propagation delay|Measured applying a voltage<br>step from 0 V to 3.3 V to pin<br>CIN|50|200|250||



**Table 12. Truth table** 

||**Table 12. Truth table**|**Table 12. Truth table**|**Table 12. Truth table**|||
|---|---|---|---|---|---|
|**Condition**|**Logic input (VI)**|||**Output**||
||**SD**|**LIN**|**HIN**|**LVG**|**HVG**|
|Shutdown enable<br>half-bridge tri-state|L|X|X|L|L|
|Interlocking<br>half-bridge tri-state|H|H|H|L|L|
|0 ‘’logic state”<br>half-bridge tri-state|H|L|L|L|L|
|1 “logic state”<br>low side direct driving|H|H|L|H|L|
|1 “logic state”<br>high side direct driving|H|L|H|L|H|



_Note: X: don’t care_ 

10/20 

DocID024473 Rev 5 

**STGIPS30C60-H** 

**Electrical characteristics** 

## **3.2 Waveform definitions** 

**==> picture [276 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 7. Dead time and interlocking waveform definitions<br>**----- End of picture text -----**<br>


**==> picture [401 x 345] intentionally omitted <==**

**----- Start of picture text -----**<br>
INTERLOCKING INTERLOCKING<br>**----- End of picture text -----**<br>


DocID024473 Rev 5 

11/20 

**Smart shutdown function** 

**STGIPS30C60-H** 

## **4 Smart shutdown function** 

The STGIPS30C60-H integrates a comparator for fault sensing purposes. The comparator has an internal voltage reference Vref connected to the inverting input, while the noninverting input, available on pin (CIN), can be connected to an external shunt resistor in order to implement a simple over-current protection function. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the halfbridge in tri-state. In the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a RC network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. The time delay between the fault and the outputs turn-off is no more dependent on the RC values of the external network connected to the shutdown pin. At the same time the DMOS connected to the open-drain output (pin SD/OD) is turned on by the internal logic which holds it on until the shutdown voltage is lower than the logic input lower threshold (Vil). Finally the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external RC network. 

12/20 

DocID024473 Rev 5 

**STGIPS30C60-H** 

**Smart shutdown function** 

**==> picture [405 x 486] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 8. Smart shutdown timing waveforms<br>comp Vref<br>CP+<br>HIN/LIN<br>PROTECTION<br>HVG/LVG<br>SD/OD<br>open drain gate<br>(internal)<br>disable time<br>Fast shut down:<br>the driver outputs are set in SD state immediately after the comparator<br>triggering even if the SD signal  has not yet reach the lower input threshold<br>An approximation of the disable time is given by:<br>SHUT DOWN CIRCUIT<br>VBIAS<br>RSD  where:<br>SD/OD<br>FROM/TO SMART<br>CONTROLLER SD<br>CSD RON_OD LOGIC<br>RPD_SD<br>AM12947v1<br>**----- End of picture text -----**<br>


_Note: Please refer to Table 11 for internal propagation delay time details._ 

DocID024473 Rev 5 

13/20 

**STGIPS30C60-H** 

**Applications information** 

## **5 Applications information** 

**==> picture [168 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 9. Typical application circuit<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
CONTROLLER<br>AM05001v3<br>VDC +<br>M<br>Rshunt<br>P U Nu V Nv W Nw<br>R<br>D1 D2 D3 D4 D5 D6 C<br>T1 T2 T3 T4 T5 T6<br>Rg Rg Rg Rg Rg Rg<br>Vboot HVG OUT LVG CP+ Vboot HVG OUT LVG CP+ Vboot HVG OUT LVG CP+<br>LIN SD/OD HIN VCC DT GND LIN SD/OD HIN VCC DT GND LIN SD/OD HIN VCC DT GND<br>Cdt Cdt Cdt<br>Cvcc Rdt Cvcc Rdt Cvcc Rdt<br>OUT U VBOOT U LIN-U HIN-U VCC OUT V VBOOT V GND LIN-V HIN-V OUT W VBOOT W LIN-W HIN-W SD/OD CIN<br>Cbu Cbv Cbw<br>VCC Rsd Csd<br>3.3V/5V Line<br>**----- End of picture text -----**<br>


14/20 

DocID024473 Rev 5 

**STGIPS30C60-H** 

**Applications information** 

## **5.1 Recommendations** 

- Input signals HIN, LIN are active high logic. A 375 k Ω (typ.) pull down resistor is built-in for each input. If an external RC filter is used, for noise immunity, pay attention to the variation of the input signal level. 

- To prevent the input signals oscillation, the wiring of each input should be as short as possible. 

- By integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler is possible. 

- Each capacitor should be located as nearby the pins of IPM as possible. 

- Low inductance shunt resistors should be used for phase leg current sensing. 

- Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. 

- The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see _Section 4: Smart shutdown function_ for detailed info). 

**Table 13. Recommended operating conditions** 

|**Symbol**|**Parameter**|**Conditions**|**Value**|**Value**|**Value**|**Unit**|
|---|---|---|---|---|---|---|
||||**Min.**|**Typ.**|**Max.**||
|VPN|Supply Voltage|Applied between P-Nu,Nv,Nw||300|400|V|
|VCC|Control supply voltage|Applied between VCC-GND|13.5|15|18|V|
|VBS|High side bias voltage|Applied between VBOOTi-OUTifor<br>i=U,V,W|13||18|V|
|tdead|Blanking time to<br>prevent Arm-short|For each input signal|1.5|||µs|
|fPWM|PWM input signal|-40°C < Tc< 100°C<br>-40°C < Tj< 125°C|||20|kHz|
|TC|Case operation<br>temperature||||100|°C|



_Note: For further details refer to AN3338._ 

DocID024473 Rev 5 

15/20 

**STGIPS30C60-H** 

**Package information** 

## **6 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _www.st.com_ . ECOPACK[®] is an ST trademark. 

Please refer to dedicated technical note TN0107 for mounting instructions. 

## **6.1 SDIP-25L package information** 

## **Figure 10. SDIP-25L package outline** 

**==> picture [342 x 426] intentionally omitted <==**

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16/20 

DocID024473 Rev 5 

**STGIPS30C60-H** 

**Package information** 

**Table 14. SDIP-25L mechanical data** 

||**Table 14. SDIP-25L mechanical data**|**Table 14. SDIP-25L mechanical data**|**Table 14. SDIP-25L mechanical data**|
|---|---|---|---|
|**Dim.**|**mm**|||
||**Min.**|**Typ.**|**Max.**|
|A|43.90|44.40|44.90|
|A1|1.15|1.35|1.55|
|A2|1.40|1.60|1.80|
|A3|38.90|39.40|39.90|
|B|21.50|22.00|22.50|
|B1|11.25|11.85|12.45|
|B2|24.83|25.23|25.63|
|C|5.00|5.40|6.00|
|C1|6.50|7.00|7.50|
|C2|11.20|11.70|12.20|
|C3|2.90|3.00|3.10|
|e|2.15|2.35|2.55|
|e1|3.40|3.60|3.80|
|e2|4.50|4.70|4.90|
|e3|6.30|6.50|6.70|
|D||33.30||
|D1||5.55||
|E||11.20||
|E1||1.40||
|F|0.85|1.00|1.15|
|F1|0.35|0.50|0.65|
|R|1.55|1.75|1.95|
|T|0.45|0.55|0.65|
|V|0°||6°|



DocID024473 Rev 5 

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**STGIPS30C60-H** 

**Package information** 

## **6.2 Packing information** 

**==> picture [192 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 11. SDIP-25L packing information<br>**----- End of picture text -----**<br>


**==> picture [342 x 568] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM10488v1<br>8123127_E<br>Base quantity: 11 pcs Bulk quantity: 132 pcs<br>**----- End of picture text -----**<br>


18/20 

DocID024473 Rev 5 

**STGIPS30C60-H** 

**Revision history** 

## **7 Revision history** 

**Table 15. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|08-Apr-2013|1|Initial release|
|08-Jul-2013|2|Updated Dt value in_Table 10: Logic inputs (VCC = 15 V unless_<br>_otherwise specified)_.|
|12-Jul-2013|3|Document status promoted from preliminary to production data.|
|14-May-2014|4|Updated_Table 3: Inverter part_,_Table 6: Thermal data_,_Table 7:_<br>_Inverter part_and_Section 6.2: Packing information_.<br>Minor text changes.|
|10-Apr-2015|5|Text edits and formatting changes throughout document<br>Updated_Figure 2: Pin layout (bottom view)_<br>Updated_Section 6: Package information_|



DocID024473 Rev 5 

19/20 

**STGIPS30C60-H** 

## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2015 STMicroelectronics – All rights reserved 

20/20 DocID024473 Rev 5 



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