# Intelligent Power Module (IPM), IGBT, 600 V, 6 A, 1.5 kV, N2DIP, SLLIMM-nano

![Product image](https://novapart.co/image/farnell:3678914/)

**URL**: https://novapart.co/products/STGIPQ4C60T-HZ/intelligent-power-module-ipm-igbt-600-v-6-a-15-kv
**SKU**: STGIPQ4C60T-HZ
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || Intelligent Power Modules
**Price**: €3.4300
**Stock**: 200+
**Lead Time**: 127 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| Ipm Series | SLLIMM-nano |
| Product Range | SLLIMM nano 2nd Series |
| Ipm Case Style | N2DIP |
| Ipm Power Device | IGBT |
| Isolation Voltage | 1.5kV |
| Current Rating (Ic / Id) | 6A |
| Voltage Rating (Vces / Vdss) | 600V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3678914/)

**STGIPQ4C60T-HZ** 

Datasheet 

SLLIMM nano - 2[nd] series IPM, 3-phase inverter, 6 A, 600 V ‑ short circuit rugged IGBT 

## **Features** 

- IPM 6 A, 600 V, 3-phase IGBT inverter bridge including 3 control ICs for gate driving and freewheeling diodes 

- 3.3 V, 5 V, 15 V TTL/CMOS input comparators with hysteresis and pull-down/ pull-up resistors 

- Internal bootstrap diode 

- Optimized for low electromagnetic interference 

**==> picture [67 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
N2DIP-26L type Z<br>**----- End of picture text -----**<br>


- Undervoltage lockout 

- Short-circuit rugged TFS IGBT 

- Shutdown function 

- Interlocking function 

- Op-amp for advanced current sensing 

- Comparator for fault protection against overcurrent 

- Isolation ratings of 1500 Vrms/min. 

- NTC (UL 1434 CA 2 and 4) 

- Up to ±2 kV ESD protection (HBM C = 100 pF, R = 1.5 kΩ) 

- UL recognition: UL 1557, file E81734 

## **Applications** 

- 3-phase inverters for motor drives 

- Dish washers 

- Washing machines 

- Refrigerator compressors 

- Fans 

## **Description** 

## **Product status link** ~~ea~~ STGIPQ4C60T-HZ 

|**Product summary**<br>~~ea~~|**Product summary**<br>~~ea~~|
|---|---|
|**Order code**|STGIPQ4C60T-HZ|
|**Marking**|GIPQ4C60T-HZ|
|**Package**|N2DIP-26L type Z|
|**Packing**|Tube|



This second series of SLLIMM (small low-loss intelligent molded module) nano provides a compact, high-performance AC motor drive in a simple, rugged design. It is composed of six improved short-circuit rugged trench gate fieldstop IGBTs with freewheeling diodes and three half-bridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed. The package is designed to allow a better and more easily screwed-on heat sink, and is optimized for thermal performance and compactness in built-in motor applications or other low power applications where assembly space is limited. This IPM includes a completely uncommitted operational amplifier and a comparator that can be used to design a fast and efficient protection circuit. SLLIMM is a trademark of STMicroelectronics. 

**DS13553** - **Rev 2** - **January 2021** For further information contact your local STMicroelectronics sales office. 

www.st.com 

**STGIPQ4C60T-HZ Internal schematic diagram and pin configuration** 

## **1 Internal schematic diagram and pin configuration** 

**Figure 1. Internal schematic diagram** 

|OP- (8)<br>Vcc W (3)<br>HIN W (4)<br>T / SD / OD (15)<br>HIN V (10)<br>Vcc V (9)<br>HIN U (14)<br>Vcc U (13)<br>LIN W ( 5)<br>LIN U (16)<br>OPOUT (7)<br>T/ SD / OD (2)<br>GND (1)<br>CIN (12)<br>OP+ (6)<br>LIN V (11)||||||||||||||||||V, OUT V (22)<br>W, OUT W (25)<br>U, OUT U (19)<br>P (18)<br>N W (26)<br>N V (23)<br>N U (20)<br>Vboot U (17)<br>Vboot V (21)<br>Vboot W (24)|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|||||||NT|C||||||||||||
|||||||||||GND<br><br>VCC<br>HVG<br>SD/OD<br>OUT<br>LVG<br><br>HIN|||||||||
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|||||||||||GND<br>OPOUT<br>LIN<br>VCC<br>HVG<br>OP+<br>OP-<br>SD/OD<br>OUT<br>LVG<br>Vboot<br>HIN|||||||||
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||||||||||GND||||||||||
|||||||||||LIN<br>VCC<br>HVG<br>CIN<br>SD/OD<br>OUT<br>LVG<br>Vboot<br>HIN|||||||||
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GIPG300720141542SMD 

**DS13553** - **Rev 2** 

**page 2/24** 

**STGIPQ4C60T-HZ Internal schematic diagram and pin configuration** 

**Table 1. Pin description** 

|**Pin**|**Symbol**|**Description**|
|---|---|---|
|1|GND|Ground|
|2|T/<br>SD/ OD|NTC thermistor terminal/shutdown logic input (active low)/open-drain<br>(comparator output)|
|3|VCCW|Low-voltage power supply W phase|
|4|HIN W|High-side logic input for W phase|
|5|LIN W|Low-side logic input for W phase|
|6|OP+|Op-amp non-inverting input|
|7|OPOUT|Op-amp output|
|8|OP-|Op-amp inverting input|
|9|VCCV|Low-voltage power supply V phase|
|10|HIN V|High-side logic input for V phase|
|11|LIN V|Low-side logic input for V phase|
|12|CIN|Comparator input|
|13|VCCU|Low-voltage power supply for V phase|
|14|HIN U|High-side logic input for V phase|
|15|T/<br>SD/ OD|NTC thermistor terminal/shutdown logic input (active low)/open-drain<br>(comparator output)|
|16|LIN U|Low-side logic input for U phase|
|17|VbootU|Bootstrap voltage for U phase|
|18|P|Positive DC input|
|19|U, OUTU|U phase output|
|20|NU|Negative DC input for U phase|
|21|VbootV|Bootstrap voltage for V phase|
|22|V, OUTV|V phase output|
|23|NV|Negative DC input for V phase|
|24|VbootW|Bootstrap voltage for W phase|
|25|W, OUTW|W phase output|
|26|NW|Negative DC input for W phase|



**DS13553** - **Rev 2** 

**page 3/24** 

**STGIPQ4C60T-HZ Internal schematic diagram and pin configuration** 

**Figure 2. Pin layout (top view) - N2DIP-26L type Z** 

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**----- Start of picture text -----**<br>
* *<br>PIN 26 PIN 17<br>Exposed pin<br>not connected<br>Exposed pin internally<br>connected to GND<br>isolated by<br>glue spot adding<br>PIN 1 PIN 16<br>**----- End of picture text -----**<br>


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* Dummy pins internally connected to P (positive DC input)<br>**----- End of picture text -----**<br>


GADG181220181216IG 

**DS13553** - **Rev 2** 

**page 4/24** 

**STGIPQ4C60T-HZ Electrical ratings** 

## **2 Electrical ratings** 

TJ = 25 °C unless otherwise specified. 

## **2.1 Absolute maximum ratings** 

## **Table 2. Inverter part** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VCES|Collector-emitter voltage for each IGBT (VIN(1)= 0)|600|V|
|IC|Continuous collector current for each IGBT (TC= 25 °C)|6|A|
|ICP(2)|Peak collector current for each IGBT (less than 1 ms)|9|A|
|PTOT|Total power dissipation for each IGBT (TC= 25 °C)|12.5|W|
|tSCW|Short-circuit withstand time<br>(VCE= 300 V, TJ= 125 °C, VCC= Vboot= 15 V, VIN(1)= 0 to 5 V)|5|µs|



_1. Applied among HINx, LINx and GND for x = U, V, W_ 

_2. Pulse width limited by maximum junction temperature._ 

**Table 3. Control part** 

|**Symbol**|**Parameter**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|---|
|VCC|Low voltage power supply|-0.3|21|V|
|Vboot|Bootstrap voltage|-0.3|620|V|
|VOUT|Output voltage applied among OUTU, OUTV, OUTW- GND|Vboot- 21|Vboot+ 0.3|V|
|VCIN|Comparator input voltage|-0.3|VCC+ 0.3|V|
|Vop+|Op-amp non-inverting input|-0.3|VCC+ 0.3|V|
|Vop-|Op-amp inverting input|-0.3|VCC+ 0.3|V|
|VIN|Logic input voltage applied among HINx, LINx and GND|-0.3|15|V|
|VT/<br>SD/OD|Open-drain voltage|-0.3|15|V|
|dVout/dt|Allowed output slew rate||50|V/ns|



**Table 4. Total system** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VISO|Isolation withstand voltage applied to each pin and heat sink plate<br>(AC voltage, t = 60 s)|1500|Vrms|
|TJ|Power chip operating junction temperature range|-40 to 150|°C|
|TC|Module case operation temperature range|-40 to 125|°C|



**DS13553** - **Rev 2** 

**page 5/24** 

**STGIPQ4C60T-HZ Absolute maximum ratings** 

## **2.1.1 Thermal data** 

## **Table 5. Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|RthJC|Thermal resistance, junction-to-case single IGBT|10|°C/W|
||Thermal resistance, junction-to-case single diode|15||



**DS13553** - **Rev 2** 

**page 6/24** 

**STGIPQ4C60T-HZ Electrical characteristics** 

## **3 Electrical characteristics** 

TJ = 25 °C unless otherwise specified. 

## **3.1 Inverter part** 

**Table 6. Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ICES|Collector cut-off current<br>(VIN(1)= 0 “logic state”)|VCE= 550 V, VCC= VBoot= 15 V|-||250|μA|
|VCE(sat)|Collector-emitter saturation<br>voltage|VCC= Vboot= 15 V, VIN(1)= 0 to 5 V,<br>IC= 1 A|-|1.20|1.36|V|
|||VCC= Vboot= 15 V, VIN(1)= 0 to 5 V,<br>IC= 3 A|-|1.6|1.8||
|||VCC= Vboot= 15 V, VIN(1)= 0 to 5 V,<br>IC= 4 A|-|1.79|2.00||
|VF|Diode forward voltage|VIN(1)= 0 “logic state”, IC= 3 A|-|1.70|1.95|V|



_1. Applied among HINx, LINx and GND for x = U, V, W_ 

**Table 7. Inductive load switching time and energy** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ton(1)|Turn-on time|VDD= 300 V,VCC= Vboot= 15 V,<br>VIN(2)= 0 to 5 V, IC= 4 A<br>(seeFigure 4. Switching time definition)|-|238|-|ns|
|tc(on)(1)|Crossover time (on)||-|102|-|ns|
|toff(1)|Turn-off time||-|736|-|ns|
|tc(off)(1)|Crossover time (off)||-|133|-|ns|
|trr|Reverse recovery time||-|320|-|ns|
|Eon|Turn-on switching energy||-|78|-|µJ|
|Eoff|Turn-off switching energy||-|67|-|µJ|



_1. ton and toff include the propagation delay times of the internal drive. tc(on) and tc(off) are the switching times of IGBT itself under the internally given gate driving conditions._ 

_2. Applied among HINx, LINx and GND for x = U, V, W._ 

**DS13553** - **Rev 2** 

**page 7/24** 

**STGIPQ4C60T-HZ Inverter part** 

**Figure 3. Switching time test circuit** 

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AM06019v2<br>**----- End of picture text -----**<br>


**Figure 4. Switching time definition** 

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**----- Start of picture text -----**<br>
100% IC 100% IC<br>t rr<br>VCE IC IC VCE<br>VIN VIN<br>t ON t OFF<br>t C(ON) t C(OFF)<br>VIN(ON) 10% IC 90% IC 10% VCE VIN(OFF) 10% VCE 10% IC<br>(a) turn-on (b) turn-off<br>AM09223V1<br>**----- End of picture text -----**<br>


**DS13553** - **Rev 2** 

**page 8/24** 

**STGIPQ4C60T-HZ Control part** 

## **3.2 Control part** 

(VCC = 15 V unless otherwise specified) 

**Table 8. Low-voltage power supply** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VCC_hys|VCCUV hysteresis||1.2|1.5|1.8|V|
|VCC_thON|VCCUV turn-ON threshold||11.5|12|12.5|V|
|VCC_thOFF|VCCUV turn-OFF threshold||10|10.5|11|V|
|Iqccu|Undervoltage quiescent supply<br>current|VCC= 10 V, VT/<br>SD/OD= 5 V,<br>LIN = HIN = CIN = 0 V|||150|µA|
|Iqcc|Quiescent current|VCC= 10 V, VT/<br>SD/OD= 5 V,<br>LIN = HIN = CIN = 0 V|||1|mA|
|Vref|Internal comparator (CIN)<br>reference voltage||0.51|0.54|0.56|V|



**Table 9. Bootstrapped voltage** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VBS_hys|VBSUV hysteresis||1.2|1.5|1.8|V|
|VBS_thON|VBSUV turn-ON threshold||11.1|11.5|12.1|V|
|VBS_thOFF|VBSUV turn-OFF threshold||9.8|10|10.6|V|
|IQBSU|Undervoltage VBSquiescent<br>current|VBS< 9 V, VT/<br>SD/OD= 5 V,<br>LIN = 0 V and HIN = 5 V,<br>CIN = 0 V||70|110|µA|
|IQBS|VBSquiescent current|VBS= 15 V, VT/<br>SD/OD= 5 V,<br>LIN = 0 V and HIN = 5 V,<br>CIN = 0 V||150|210|µA|
|RDS(on)|Bootstrap driver on-resistance|LVG ON||120||Ω|



**Table 10. Logic inputs** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vil|Low logic level voltage||||0.8|V|
|Vih|High logic level voltage||2.25|||V|
|IHINh|HIN logic “1” input bias current|HIN = 15 V|20|40|100|µA|
|IHINl|HIN logic “0” input bias current|HIN = 0 V|||1|µA|
|ILINl|LIN logic “0” input bias current|LIN = 0 V|||1|µA|
|ILINh|LIN logic “1” input bias current|LIN = 15 V|20|40|100|µA|
|ISDh|SD logic “0” input bias current|SD = 15 V|210|350|477|µA|
|ISDl|SD logic “1” input bias current|SD = 0 V|||3|µA|
|Dt|Dead time|SeeFigure 9. Dead time and interlocking<br>waveform definitions||180||ns|



**DS13553** - **Rev 2** 

**page 9/24** 

**STGIPQ4C60T-HZ Control part** 

**Table 11. Op-amp characteristics** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vio|Input offset voltage|Vic= 0 V, Vo= 7.5 V|||6|mV|
|Iio|Input offset current|||4|40|nA|
|Iib|Input bias current(1)|||100|200|nA|
|VOL|Low level output voltage|RL= 10 kΩ to VCC||75|150|mV|
|VOH|High level output voltage|RL= 10 kΩ to GND|14|14.7||V|
|Io|Output short-circuit current|Source, Vid= + 1 V; Vo= 0 V|16|30||mA|
|||Sink, Vid= -1 V; Vo= VCC|50|80||mA|
|SR|Slew rate|Vi= 1 - 4 V; CL= 100 pF; unity gain|2.5|3.8||V/µs|
|GBWP|Gain bandwidth product|Vo= 7.5 V|8|12||MHz|
|Avd|Large signal voltage gain|RL= 2 kΩ|70|85||dB|
|SVR|Supply voltage rejection ratio|vs VCC|60|75||dB|
|CMRR|Common mode rejection ratio||55|70||dB|



_1. The direction of input current is out of the IC._ 

**Table 12. Sense comparator characteristics** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Iib|Input bias current|VCIN= 1 V|-||1|µA|
|Vod|Open-drain low level output<br>voltage|Iod= 3 mA|-||0.5|V|
|RON_OD|Open-drain low level output|Iod= 3 mA|-|166||Ω|
|RPD_SD|SD pull-down resistor(1)||-|125||kΩ|
|td_comp|Comparator delay|VT/<br>SD/ODpulled to 5 V through 100 kΩ<br>resistor|-|90|130|ns|
|SR|Slew rate|CL= 180 pF, Rpu= 5 kΩ|-|60||V/µs|
|tsd|Shutdown to high-/low-side driver<br>propagation delay|VOUT= 0, Vboot= VCC,<br>VIN= 0 to 3.3 V|50|125|200|ns|
|tisd|Comparator triggering to<br>high-/ low-side driver turn-off<br>propagation delay|Measured applying a voltage step from 0<br>V to 3.3 V to pin CIN|50|200|250||



_1. Equivalent values as a result of the resistances of three drivers in parallel._ 

**Table 13. Truth table** 

|**Conditions**|**Logic input (VI)**|**Logic input (VI)**|**Logic input (VI)**|**Output**|**Output**|
|---|---|---|---|---|---|
||**T/**<br>**SD/OD**|**LIN**|**HIN**|**LVG**|**HVG**|
|Shutdown enable half-bridge tri-state|L|X(1)|X(1)|L|L|
|Interlocking half-bridge tri-state|H|H|H|L|L|
|0 “logic state” half-bridge tri-state|H|L|L|L|L|
|1 “logic state” low-side direct driving|H|H|L|H|L|
|1 “logic state” high-side direct driving|H|L|H|L|H|



_1. X: don’t care._ 

**DS13553** - **Rev 2** 

**page 10/24** 

**STGIPQ4C60T-HZ Control part** 

## **3.2.1 NTC thermistor** 

**Figure 5. Internal structure of SD and NTC** 

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**----- Start of picture text -----**<br>
Vbias<br>R SD<br>LIN Vboot<br>V<br>T/SD/OD<br>SD/OD<br>C SD NTC HIN HVG<br>VCC<br>OUT<br>RPD_SD<br>LVG<br>GND CIN<br>**----- End of picture text -----**<br>


RPD_SD: equivalent value as result of resistances of three drivers in parallel. 

**Figure 6. Equivalent resistance (NTC//RPD_SD)** 

**==> picture [270 x 177] intentionally omitted <==**

**----- Start of picture text -----**<br>
140<br>120<br>100<br>80<br>60<br>40<br>20<br>0<br>-40 -20 0 20 40 60 80 100 120<br>Temperature (°C)<br>Equivalent Resistance (kΩ)<br>**----- End of picture text -----**<br>


**DS13553** - **Rev 2** 

**page 11/24** 

**STGIPQ4C60T-HZ Control part** 

**Figure 7. Equivalent resistance (NTC//RPD_SD) zoom** 

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**----- Start of picture text -----**<br>
14<br>12<br>10<br>8<br>6<br>4<br>2<br>0<br>70 80 90 100 110 120<br>Temperature (°C)<br>Equivalent Resistance (kΩ)<br>**----- End of picture text -----**<br>


**Figure 8. Voltage of T/SD/OD pin according to NTC temperature** 

**==> picture [265 x 189] intentionally omitted <==**

**----- Start of picture text -----**<br>
5.0<br>SD/OD: high<br>4.5<br>V Bias = 5 V<br>R SD = 2.2 kΩ<br>4.0<br>3.5<br>3.0 V Bias = 3.3 V<br>R SD = 1.0 kΩ<br>2.5<br>2.0<br>25 50 75 100 125<br>Temperature (°C)<br>(V)<br>SD<br>V<br>**----- End of picture text -----**<br>


**DS13553** - **Rev 2** 

**page 12/24** 

**STGIPQ4C60T-HZ Waveform definitions** 

## **3.3 Waveform definitions** 

**Figure 9. Dead time and interlocking waveform definitions** 

**==> picture [454 x 390] intentionally omitted <==**

**----- Start of picture text -----**<br>
INTERLOCKING INTERLOCKING G<br>**----- End of picture text -----**<br>


**DS13553** - **Rev 2** 

**page 13/24** 

**STGIPQ4C60T-HZ Shutdown function** 

**4 Shutdown function** 

The device is equipped with three half-bridge IC gate drivers and integrates a comparator for fault detection. The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting input pin (CIN) can be connected to an external shunt resistor for current monitoring. 

Since the comparator is embedded in the U IC gate driver, in case of fault it disables directly the U outputs, whereas the shutdown of V and W IC gate drivers depends on the RC value of the external SD circuitry, which fixes the disabling time. 

For an effective design of the shutdown circuit, please refer to Application note AN4966. 

**Figure 10. Shutdown timing waveforms** 

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GADG250120171515FSR<br>V REF a ' Oe'<br>/” f1<br>'<br>i<br>CI N<br>1<br>''<br>'1 1<br>HIN or LIN<br>|'<br>i '<br>U q V, W i]<br>PROTECT ION<br>HVG or  LVG<br>SD/OD — or iVoss 1i ; :4<br>T/SD/OD — 4,I<br>‘ '<br>Vin-------+-5 ee nee ——_.-<br>Vi -----s 4pomemameme initia liek 1 anienenaenes<br>L) i)<br>T A '4 B<br>open -drain gate<br>(internal)<br>t 7-_ t A ' t B i<br>**----- End of picture text -----**<br>


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T= (Ron_ov//Rsp//Rpp_sv// [∗] Ryrc) Csp = Ron_op Csp<br>Te = (Rsp//Rpp_sv// [∗] Ryrc)* €sp<br>ieut v==  7.Ron_ov//Rep_sp//yh PRD [∗] RyrcNO Vvbi<br>[∗]<br>RPO_so i§ *RuTC §i ne om (Row op//Rpp_ ≅ sv//RonRyrc) op +  RspV, ns<br>=- + = Row.ov+Rsp 7%<br>Via°F =Rep_spo// ∗ [∗] RureAT “Y,Vp<br>(Rep _ sv// Bure)+ Rsv<br>RSD and CSD external circuitry must be designed to ensure  Von <Vir & Voge> Vin<br>Please refer to AN4966 for further details.<br>**----- End of picture text -----**<br>


* RNTC to be considered only when the NTC is internally connected to the T/SD/OD pin. 

**DS13553** - **Rev 2** 

**page 14/24** 

**STGIPQ4C60T-HZ Application circuit example** 

## **5 Application circuit example** 

## **Figure 11. Application circuit example** 

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**----- Start of picture text -----**<br>
MICROCONTROLLER<br>VDC<br>+ -<br>Cvdc<br>C4<br>M PWR_GN D<br>Rshunt<br>DZ2 DZ2 DZ2<br>C3 C3 C3<br>Cboot U Cboot V Cboot W<br>RS<br>Vboot U (17) P (18) U, OUT U (19) N U (20) Vboot V (21) V, OUT V (22) N V (23) Vboot W (24) W, OUT W (25) N W (26)<br>Vboot HVG OUT LVG CIN Vboot HVG OUT LVG OP+ Vboot HVG OUT LVG<br>LIN SD/OD HIN VCC GND LIN SD/OD HIN VCC OP- OPOUT GND LIN SD/OD HIN VCC GND<br>NTC<br>LIN U (16) T / SD / OD (15) HIN U (14) Vcc U (13) CIN (12) C SF LIN V (11) HIN V (10) Vcc V (9) OP- (8) C OP OPOUT (7) OP+ (6) LINW (5) HIN W (4) Vcc W (3) T / SD / OD (2) GND (1)<br>C1 C1 C1 C1 C1 C1 SGN_GN D DZ1<br>R SF R5<br>R1 R1 RS R1 R1 R4 C AD R1 R1 C2<br>Cvc c<br>R2 R3 R SD C SD<br>5V / 3.3V 5V / 3.3V<br>R1 + VCC -<br>RS<br>LIN U HIN U LIN V HIN V ADC LIN W HIN W<br>SD Temp. Monitoring<br>**----- End of picture text -----**<br>


**==> picture [47 x 4] intentionally omitted <==**

**----- Start of picture text -----**<br>
GAD250720161156FSR<br>**----- End of picture text -----**<br>


Application designers are free to use a different scheme according to the specifications of the device. 

**DS13553** - **Rev 2** 

**page 15/24** 

**STGIPQ4C60T-HZ Guidelines** 

## **5.1 Guidelines** 

- Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-in for each input. To avoid input signal oscillation, the wiring of each input should be as short as possible, and the use of RC filters (R1, C1) on each input signal is suggested. The filters should be with a time constant of about 100 ns and placed as close as possible to the IPM input pins. 

- The use of a bypass capacitor CVCC (aluminum or tantalum) can reduce the transient circuit demand on the power supply. Also, to reduce any high-frequency switching noise distributed on the power lines, a decoupling capacitor C2 (100 to 220 nF, with low ESR and low ESL) should be placed as close as possible to the Vcc pin and in parallel with the bypass capacitor. 

- The use of an RC filter (RSF, CSF) is recommended to prevent protection circuit malfunction. The time constant (RSF x CSF) should be set to 1 μs and the filter must be placed as close as possible to the CIN pin. 

- The SD is an input/output pin (open-drain type if it is used as output). A built-in thermistor NTC is internally connected between the SD pin and GND. The voltage VSD-GND decreases as the temperature increases, due to the pull-up resistor RSD. In order to keep the voltage always higher than the high-level logic threshold, the pull-up resistor should be set to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU power supply, respectively. The capacitor CSD of the filter on SD should be fixed no higher than 3.3 nF in order to assure the SD activation time τA ≤ 500 ns. Besides, the filter should be placed as close as possible to the SD pin. 

- The decoupling capacitor C3 (from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with each Cboot, filters high-frequency disturbance. Both Cboot and C3 (if present) should be placed as close as possible to the U, V, W and Vboot pins. Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires. 

- To avoid overvoltage on the Vcc pin, a Zener diode (Dz1) can be used. Similarly on the Vboot pin, a Zener diode (Dz2) can be placed in parallel with each Cboot. 

- The use of the decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor Cvdc is useful to prevent surge destruction. Both capacitors C4 and Cvdc should be placed as close as possible to the IPM (C4 has priority over Cvdc). 

- By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an opto-couplers is possible. 

- Low-inductance shunt resistors have to be used for phase leg current sensing. 

- In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND should be as short as possible. 

- The connection of SGN_GND to PWR_GND on one point only (close to the shunt resistor terminal) can reduce the impact of power ground fluctuation. 

These guidelines ensure the specifications of the device for application designs. For further details, please refer to the relevant application note. 

**Table 14. Recommended operating conditions** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VPN|Supply voltage|Applied among P-Nu, Nv, Nw||300|500|V|
|VCC|Control supply voltage|Applied to VCC-GND|13.5|15|18|V|
|VBS|High-side bias voltage|Applied to VBOOTx-OUT for x = U,<br>V, W|13||18|V|
|tdead|Blanking time to prevent arm-short|For each input signal|1.5|||µs|
|fPWM|PWM input signal|-40 °C < TC< 100 °C<br>-40 °C < TJ< 125 °C|||25|kHz|
|TC|Case operation temperature||||100|°C|



**DS13553** - **Rev 2** 

**page 16/24** 

**STGIPQ4C60T-HZ Electrical characteristics (curves)** 

## **6 Electrical characteristics (curves)** 

**==> picture [513 x 196] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 12. Output characteristics Figure 13. VCE(sat) vs collector current<br>IC GADG210120210826OC25 VCE(sat) GADG210120210827VCEC<br>(A)  (V)<br>7 2.8 VCC = 15 V<br>6 2.4<br>5 2.0<br>VGE = 13-18 V TJ = 150 °C<br>4 1.6<br>TJ = 25 °C<br>3 1.2<br>2 0.8<br>1 0.4<br>0 0.0<br>0.0 0.4 0.8 1.2 1.6 2.0 2.4 VCE (V) 0 1 2 3 4 5 6 7 IC (A)<br>**----- End of picture text -----**<br>


**==> picture [513 x 411] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 14. Diode VF vs forward current Figure 15. IC vs case temperature<br>VF GADG210120210827DVF IC GADG210120210832CCT<br>(V)  (A)<br>6<br>2.0<br>VCC ≥ 15 V, TJ ≤ 150 °C<br>TJ = 25 °C 5<br>1.6<br>4<br>TJ = 150 °C<br>1.2<br>3<br>0.8<br>2<br>0.4<br>1<br>0.0 0<br>0 1 2 3 4 5 6 7 IF (A) 0 25 50 75 100 125 150 TC (°C)<br>Figure 16. Eon switching energy vs collector current Figure 17. Eoff switching energy vs collector current<br>Eon GADG210120210828SLC_on Eoff GADG210120210830SLC_off<br>(mJ) (mJ)<br>0.28 VDD = 300 V, VCC = Vboot = 15 V 0.18 VDD = 300 V, VCC = Vboot = 15 V<br>0.24<br>0.15<br>0.20 TJ = 150 °C<br>0.12<br>0.16 TJ = 150 °C<br>0.09<br>0.12 TJ = 25 °C<br>TJ = 25 °C<br>0.06<br>0.08<br>0.04 0.03<br>0.00 0.00<br>0 1 2 3 4 5 6 7 IC (A) 0 1 2 3 4 5 6 7 IC (A)<br>**----- End of picture text -----**<br>


**DS13553** - **Rev 2** 

**page 17/24** 

**STGIPQ4C60T-HZ Electrical characteristics (curves)** 

**==> picture [258 x 185] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 18. Normalized transient thermal impedance for IGBT<br>K  Zthjc N2DIP-26L IGBT<br>10  [-1]<br>10  [-2]<br>10  [-3]<br>10  [-5] 10  [-4] 10  [-3] 10  [-2] 10  [-1] 10  [0] tp (s)<br>**----- End of picture text -----**<br>


**DS13553** - **Rev 2** 

**page 18/24** 

**STGIPQ4C60T-HZ Package information** 

**7 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 

## **7.1 N2DIP-26L type Z package information** 

**Figure 19. N2DIP-26L type Z package outline** 

8558322_typeZ_rev3 

**DS13553** - **Rev 2** 

**page 19/24** 

**STGIPQ4C60T-HZ N2DIP-26L type Z package information** 

**Table 15. N2DIP-26L type Z mechanical data** 

|**Di**|**mm**|**mm**|**mm**|
|---|---|---|---|
|**m.**|**Min.**|**Typ.**|**Max.**|
|A|4.80|5.10|5.40|
|A1|0.80|1.00|1.20|
|A2|4.00|4.10|4.20|
|A3|1.70|1.80|1.90|
|A4|1.70|1.80|1.90|
|A5|8.10|8.40|8.70|
|A6|1.75|||
|b|0.53||0.72|
|b2|0.83||1.02|
|c|0.46||0.59|
|D|32.05|32.15|32.25|
|D1|2.10|||
|D2|1.85|||
|D3|30.65|30.75|30.85|
|E|12.35|12.45|12.55|
|e|1.70|1.80|1.90|
|e1|2.40|2.50|2.60|
|eB1|16.10|16.40|16.70|
|eB2|21.18|21.48|21.78|
|L|0.85|1.05|1.25|
|Dia|3.10|3.20|3.30|



**DS13553** - **Rev 2** 

**page 20/24** 

**STGIPQ4C60T-HZ N2DIP-26L packing information** 

## **7.2 N2DIP-26L packing information** 

**Figure 20. N2DIP-26L tube (dimensions are in mm)** 

**==> picture [152 x 175] intentionally omitted <==**

**==> picture [50 x 113] intentionally omitted <==**

**DS13553** - **Rev 2** 

**page 21/24** 

**STGIPQ4C60T-HZ** 

## **Revision history** 

**Table 16. Document revision history** 

|**Date**|**Version**|**Changes**|
|---|---|---|
|03-Nov-2020|1|First release.|
|21-Jan-2021|2|UpdatedFeatures.<br>UpdatedTable 6. StaticandTable 7. Inductive load switching time and energy.<br>AddedSection  6  Electrical characteristics (curves).|



**DS13553** - **Rev 2** 

**page 22/24** 

**STGIPQ4C60T-HZ Contents** 

## **Contents** 

|**1**|**Internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2**|
|---|---|
|**2**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5**|
||**2.1**<br>Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
||**2.1.1**<br>Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7**|
||**3.1**<br>Inverter part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
||**3.2**<br>Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
||**3.2.1**<br>NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
||**3.3**<br>Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13|
|**4**|**Shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14**|
|**5**|**Application circuit example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15**|
||**5.1**<br>Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16|
|**6**|**Electrical characteristics (curves). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17**|
|**7**|**Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19**|
||**7.1**<br>N2DIP-26L type Z package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19|
||**7.2**<br>N2DIP-26L packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21|
|**Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22**||



**DS13553** - **Rev 2** 

**page 23/24** 

**STGIPQ4C60T-HZ** 

## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2021 STMicroelectronics – All rights reserved 

**DS13553** - **Rev 2** 

**page 24/24** 



## Links

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---

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