# Intelligent Power Module (IPM), IGBT, 600 V, 5 A, 1 kVrms, NSDIP, SLLIMM-nano

![Product image](https://novapart.co/image/farnell:4666056RL/)

**URL**: https://novapart.co/products/STGIPNS4C60T-H/intelligent-power-module-ipm-igbt-600-v-5-a-1
**SKU**: STGIPNS4C60T-H
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || Intelligent Power Modules
**Price**: €3.8400
**Stock**: 100+
**Lead Time**: 120 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| Isolation Voltage | 1kVrms |
| Current Rating (Ic / Id) | 5A |
| Voltage Rating (Vces / Vdss) | 600V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:4666056RL/)

**STGIPNS4C60T-H** 

Datasheet 

## SLLIMM nano IPM, 5 A, 600 V, 3-phase inverter IGBT 

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## **Features** 

- IPM 5 A, 600 V, 3-phase inverter IGBT including control ICs for gate driving and freewheeling diodes 

- Optimized for low electromagnetic interference 

- 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull-down/ pull-up resistors 

- Undervoltage lockout 

- Internal bootstrap diode 

- Interlocking function 

- Shutdown function 

- Comparator for fault protection against overcurrent 

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NSDIP-26L<br>**----- End of picture text -----**<br>


- Op-amp for advanced current sensing 

- Optimized pinout for easy board layout 

- NTC for temperature control (UL 1434 CA 2 and 4) 

- • Moisture sensitivity level (MSL) 3 for SMD package 

## **Applications** 

- 3-phase induction motor (ACIM) 

- Dishwasher 

- Refrigerators and freezers 

## **Product status link** ~~Saas~~ STGIPNS4C60T-H 

## **Description** 

|**Product summary**<br>~~Saas~~|**Product summary**<br>~~Saas~~|
|---|---|
|**Order code**|STGIPNS4C60T-H|
|**Marking**|GIPNS4C60T-H|
|**Package**|NSDIP-26L|
|**Packing**|Tape and reel|



This SLLIMM (small low-loss intelligent molded module) nano provides a compact, high-performance AC motor drive in a simple, rugged design. It is composed of six IGBTs and three half-bridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed. The package is optimized for thermal performance and compactness in built-in motor applications, or other low power applications where assembly space is limited. This IPM includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. 

**DS14683** - **Rev 1** - **June 2024** For further information contact your local STMicroelectronics sales office. 

www.st.com 

**STGIPNS4C60T-H Internal schematic diagram and pin configuration** 

## **1 Internal schematic diagram and pin configuration** 

**Figure 1. Internal schematic diagram** 

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GND (1) N W (26)<br>T / SD / OD (2) NTC<br>GND W, OUT W (25)<br>Vcc W (3) HVG<br>OUT Vboot W (24)<br>HIN W (4) VCC<br>HIN LVG<br>SD/OD<br>LINW (5) LIN Vboot<br>OP+ (6)<br>N V (23)<br>OPOUT (7) GND OP+<br>OPOUT<br>OP- HVG V, OUT V (22)<br>OP- (8)<br>OUT<br>VCC<br>Vcc V (9) HIN LVG<br>SD/OD<br>LIN Vboot<br>HIN V (10)<br>Vboot V (21)<br>LIN V (11)<br>GND N U (20)<br>CIN (12) CIN<br>HVG<br>Vcc U (13)<br>OUT U, OUT U (19)<br>VCC<br>HIN U (14) HIN LVG<br>SD/OD<br>LIN Vboot P (18)<br>T / SD / OD (15)<br>LIN U (16) Vboot U (17)<br>**----- End of picture text -----**<br>


GADG250120171448FSR 

**DS14683** - **Rev 1** 

**page 2/23** 

**STGIPNS4C60T-H Internal schematic diagram and pin configuration** 

**Table 1. Pin description** 

|**Pin**|**Symbol**|**Description**|
|---|---|---|
|1|GND|Ground|
|2|T/<br>SD/ OD|NTC thermistor terminal / shutdown logic input (active low) / open-drain (comparator output)|
|3|VCCW|Low voltage power supply W phase|
|4|HIN W|High-side logic input for W phase|
|5|LIN W|Low-side logic input for W phase|
|6|OP+|Op-amp non inverting input|
|7|OPOUT|Op-amp output|
|8|OP-|Op-amp inverting input|
|9|VCCV|Low voltage power supply V phase|
|10|HIN V|High-side logic input for V phase|
|11|LIN V|Low-side logic input for V phase|
|12|CIN|Comparator input|
|13|VCCU|Low voltage power supply for U phase|
|14|HIN U|High-side logic input for U phase|
|15|T/<br>SD/OD|NTC thermistor terminal / shutdown logic input (active low) / open-drain (comparator output)|
|16|LIN U|Low-side logic input for U phase|
|17|VBOOTU|Bootstrap voltage for U phase|
|18|P|Positive DC input|
|19|U, OUTU|U phase output|
|20|NU|Negative DC input for U phase|
|21|VBOOTV|Bootstrap voltage for V phase|
|22|V, OUTV|V phase output|
|23|NV|Negative DC input for V phase|
|24|VBOOTW|Bootstrap voltage for W phase|
|25|W, OUTW|W phase output|
|26|NW|Negative DC input for W phase|



**DS14683** - **Rev 1** 

**page 3/23** 

**STGIPNS4C60T-H Internal schematic diagram and pin configuration** 

**Figure 2. Pin layout (top view)** 

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(*) (*)<br>PIN #1 ID<br>**----- End of picture text -----**<br>


(*) Dummy pin internally connected to P (positive DC input). 

**DS14683** - **Rev 1** 

**page 4/23** 

**STGIPNS4C60T-H Electrical ratings** 

## **2 Electrical ratings** 

## **2.1 Absolute maximum ratings** 

**Table 2. Inverter part** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VCES|Collector-emitter voltage for each IGBT (VIN= 0 V)(1)|600|V|
|±IC|Continuous collector current each IGBT (TC= 25 °C)|5|A|
|±ICP(2)|Pulsed collector current each IGBT (less than 1 ms)|9|A|
|PTOT|Total power dissipation each IGBT (TC= 25 °C)|9|W|
|tSCW|Short-circuit withstand time<br>(VCE= 300 V, TJ= 125 °C, VCC= Vboot= 15 V,<br>VIN(1)= 0 to 5 V)|5|µs|



_1. Applied among HINi, LINi and GND for i = U, V, W_ 

_2. Pulse width limited by maximum junction temperature._ 

**Table 3. Control part** 

|**Symbol**|**Parameter**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|---|
|VOUT|Output voltage applied among OUTU, OUTV, OUTW- GND|Vboot- 21|Vboot+ 0.3|V|
|VCC|Low voltage power supply|- 0.3|21|V|
|VCIN|Comparator input voltage|- 0.3|VCC+ 0.3|V|
|Vop+|Op-amp non-inverting input|- 0.3|VCC+ 0.3|V|
|Vop-|Op-amp inverting input|- 0.3|VCC+ 0.3|V|
|Vboot|Bootstrap voltage|- 0.3|620|V|
|VIN|Logic input voltage applied among HIN, LIN and GND|- 0.3|15|V|
|VT/<br>SD/OD|Open-drain voltage|- 0.3|15|V|
|dvout/dt|Allowed output slew rate||50|V/ns|



**Table 4. Total system** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VISO|Isolation withstand voltage applied between each pin and<br>heatsink plate (AC voltage, t = 60 s)|1000|Vrms|
|TJ|Power chips operating junction temperature range|-40 to 150|°C|
|TC|Module case operating temperature range|-40 to 125|°C|



**DS14683** - **Rev 1** 

**page 5/23** 

**STGIPNS4C60T-H Electrical ratings** 

## **2.2 Thermal data** 

## **Table 5. Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|RthJC|Thermal resistance, junction-to-case, each IGBT|13.8|°C/W|
||Thermal resistance, junction-to-case, each diode|17.4||
|RthJA|Thermal resistance, junction-to-ambient, whole module|24|°C/W|



**DS14683** - **Rev 1** 

**page 6/23** 

**STGIPNS4C60T-H Electrical characteristics** 

## **3 Electrical characteristics** 

## **3.1 Inverter part** 

TJ = 25 °C unless otherwise specified 

## **Table 6. Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VCE(sat)|Collector-emitter saturation<br>voltage|VCC= Vboot= 15 V,<br>VIN(1)= 0 to 5 V, IC= 1 A|-|1.2|1.36|V|
|||VCC= Vboot= 15 V,<br>VIN(1)= 0 to 5 V, IC= 3 A|-|1.6|1.8||
|||VCC= Vboot= 15 V,<br>VIN(1)= 0 to 5 V, IC= 4 A|-|1.79|2.00||
|ICES|Collector-cut off current<br>(VIN(1)= 0 “logic state”)|VCE= 550 V,<br>VCC= Vboot= 15 V|-||250|µA|
|VF|Diode forward voltage|VIN(1)= 0 “logic state”,<br>IC= 4 A|-|1.9||V|



_1. Applied among HINi, LINi and GND for i = U,V,W._ 

**Table 7. Inductive load switching time and energy** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ton(1)|Turn-on time|VDD= 300 V,<br>VCC= Vboot= 15 V,<br>VIN(2)= 0 to 5 V, IC= 4 A<br>(seeFigure 4. Switching time<br>definition)|-|238|-|ns|
|tc(on)(1)|Crossover time (on)||-|102|-|ns|
|toff(1)|Turn-off time||-|736|-|ns|
|tc(off)(1)|Crossover time (off)||-|133|-|ns|
|trr|Reverse recovery time||-|320|-|ns|
|Eon|Turn-on switching energy||-|78|-|µJ|
|Eoff|Turn-off switching energy||-|67|-|µJ|



_1. ton and toff include the propagation delay time of the internal drive. tc(on) and tc(off) are the switching times of IGBT itself under the internally given gate driving condition._ 

_2. Applied among HINi, LINi and GND for i = U,V,W._ 

**DS14683** - **Rev 1** 

**page 7/23** 

**STGIPNS4C60T-H Electrical characteristics** 

**Figure 3. Switching time test circuit** 

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AM06019v2<br>**----- End of picture text -----**<br>


**Figure 4. Switching time definition** 

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100% IC  100% IC<br>t rr<br>VCE IC IC VCE<br>VIN VIN<br>t ON t OFF<br>t C(ON) t C(OFF)<br>VIN(ON) 10% IC 90% IC 10% VCE VIN(OFF) 10% VCE 10% IC<br>(a) turn-on (b) turn-off<br>ADG090820161404MT<br>**----- End of picture text -----**<br>


Figure 4. Switching time definition refers to HIN, LIN inputs (active high). 

**DS14683** - **Rev 1** 

**page 8/23** 

**STGIPNS4C60T-H Electrical characteristics** 

## **3.2 Control part** 

VCC = 15 V unless otherwise specified 

## **Table 8. Low voltage power supply** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VCC_hys|VCCUV hysteresis||1.2|1.5|1.8|V|
|VCC_thON|VCCUV turn-ON threshold||11.5|12|12.5|V|
|VCC_thOFF|VCCUV turn-OFF threshold||10|10.5|11|V|
|Iqccu|Undervoltage quiescent<br>supply current|VCC= 15 V, T/<br>SD/OD = 5 V,<br>LIN = 0 V, HIN = 0 V,<br>CIN = 0 V|||150|µA|
|Iqcc|Quiescent current|VCC= 15 V, T/<br>SD/OD = 5 V,<br>LIN = 0 V, HIN = 0 V,<br>CIN = 0 V|||1|mA|
|Vref|Internal comparator (CIN)<br>reference voltage||0.5|0.54|0.58|V|



**Table 9. Bootstrapped voltage** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VBS_hys|VBSUV hysteresis||1.2|1.5|1.8|V|
|VBS_thON|VBSUV turn-ON threshold||11.1|11.5|12.1|V|
|VBS_thOFF|VBSUV turn-OFF threshold||9.8|10|10.6|V|
|IQBSU|Undervoltage VBSquiescent<br>current|VBS< 9 V, T/<br>SD/OD = 5 V,<br>LIN = 0 V and HIN = 5 V,<br>CIN = 0 V||70|110|µA|
|IQBS|VBSquiescent current|VBS= 15 V, T/<br>SD/OD = 5 V,<br>LIN = 0 V and<br>HIN = 5 V, CIN = 0 V||200|300|µA|
|RDS(on)|Bootstrap driver on-resistance|LVG ON||120||Ω|



**DS14683** - **Rev 1** 

**page 9/23** 

**STGIPNS4C60T-H Electrical characteristics** 

## **Table 10. Logic inputs** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vil|Low logic level voltage||||0.8|V|
|Vih|High logic level voltage||2.25|||V|
|IHINh|HIN logic “1” input bias<br>current|HIN = 15 V|20|40|100|µA|
|IHINI|HIN logic “0” input bias<br>current|HIN = 0 V|||1|µA|
|ILINI|LIN logic “0” input bias current|LIN = 0 V|||1|µA|
|ILINh|LIN logic “1” input bias current|LIN = 15 V|20|40|100|µA|
|ISDh|SD logic “0” input bias current|SD = 15 V|200|350|500|µA|
|ISDI|SD logic “1” input bias current|SD = 0 V|||3|µA|
|Dt|Dead time|(seeFigure 9. Dead time and<br>interlocking waveform<br>definitions)||180||ns|



**Table 11. Op-amp characteristics** 

|**Symbol**|**Parameter**|**Test condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vio|Input offset voltage|Vic= 0 V, Vo= 7.5 V|||6|mV|
|Iio|Input offset current|Vic= 0 V, Vo= 7.5 V||4|40|nA|
|Iib|Input bias current(1)|||100|200|nA|
|VOL|Low level output voltage|RL= 10 kΩ to VCC||75|150|mV|
|VOH|High level output voltage|RL= 10 kΩ to GND|14|14.7||V|
|Io|Output short-circuit current|Source, Vid= + 1 V, Vo= 0 V|16|30||mA|
|||Sink, Vid= -1 V, Vo= VCC|50|80||mA|
|SR|Slew rate|Vi= 1 - 4 V, CL= 100 pF,<br>unity gain|2.5|3.8||V/µs|
|GBWP|Gain bandwidth product|Vo= 7.5 V|8|12||MHz|
|Avd|Large signal voltage gain|RL= 2 kΩ|70|85||dB|
|SVR|Supply voltage rejection ratio|vs. VCC|60|75||dB|
|CMRR|Common mode rejection ratio||55|70||dB|



_1. The direction of input current is out of the IC._ 

**DS14683** - **Rev 1** 

**page 10/23** 

**STGIPNS4C60T-H Electrical characteristics** 

**Table 12. Sense comparator characteristics** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Iib|Input bias current|VCIN= 1 V|||1|µA|
|Vod|Open-drain low level output<br>voltage|Iod= 3 mA|||0.5|V|
|RON_OD|Open-drain low level output|Iod= 3 mA||166||Ω|
|RPD_SD|SD pull-down resistor(1)|||125||kΩ|
|td_comp|Comparator delay|T/<br>SD/OD pulled to 5 V<br>through 100 kΩ resistor||90|130|ns|
|SR|Slew rate|CL= 180 pF; Rpu= 5 kΩ||60||V/µs|
|tsd|Shutdown to high- / low-side<br>driver propagation delay|VOUT= 0, Vboot= VCC,<br>VIN= 0 to 3.3 V|50|125|200|ns|
|tisd|Comparator triggering to<br>high- / low-side driver turn-off<br>propagation delay|Measured applying a voltage<br>step from 0 V to 3.3 V to pin<br>CIN|50|200|250|ns|



_1. Equivalent value derived from the resistances of three drivers in parallel._ 

## **Table 13. Truth table** 

|**Condition**|**Logic input (VI)**|**Logic input (VI)**|**Logic input (VI)**|**Output**|**Output**|
|---|---|---|---|---|---|
||**T/**<br>**SD/OD**|**LIN**|**HIN**|**LVG**|**HVG**|
|Shutdown enable half-bridge tri-state|L|X(1)|X(1)|L|L|
|Interlocking half-bridge tri-state|H|H|H|L|L|
|0 “logic state” half-bridge tri-state|H|L|L|L|L|
|1 “logic state” low- side direct driving|H|H|L|H|L|
|1 “logic state” high- side direct driving|H|L|H|L|H|



_1. X: don’t care._ 

**DS14683** - **Rev 1** 

**page 11/23** 

**STGIPNS4C60T-H Electrical characteristics** 

## **3.2.1 NTC thermistor** 

**Figure 5. Internal structure of SD and NTC** 

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GADG020120181050SA 

RPD_SD: equivalent value as result of resistances of three drivers in parallel. 

**Figure 6. Equivalent resistance (NTC//RPD_SD)** 

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140<br>120<br>100<br>80<br>60<br>40<br>20<br>0<br>-40 -20 0 20 40 60 80 100 120<br>Temperature (°C)<br>Equivalent Resistance (kΩ)<br>**----- End of picture text -----**<br>


**DS14683** - **Rev 1** 

**page 12/23** 

**STGIPNS4C60T-H Electrical characteristics** 

**Figure 7. Equivalent resistance (NTC//RPD_SD) zoom** 

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14<br>12<br>10<br>8<br>6<br>4<br>2<br>0<br>70 80 90 100 110 120<br>Temperature (°C)<br>Equivalent Resistance (kΩ)<br>**----- End of picture text -----**<br>


**Figure 8. Voltage of T/SD/OD pin according to NTC temperature** 

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5.0<br>SD/OD: high<br>4.5<br>VBias = 5 V<br>R SD = 2.2 kΩ<br>4.0<br>3.5<br>3.0 VBias = 3.3 V<br>RSD = 1.0 kΩ<br>2.5<br>2.0<br>25 50 75 100 125<br>Temperature (°C)<br>(V)<br>SD<br>V<br>**----- End of picture text -----**<br>


**DS14683** - **Rev 1** 

**page 13/23** 

**STGIPNS4C60T-H Electrical characteristics** 

## **3.3 Waveform definitions** 

**Figure 9. Dead time and interlocking waveform definitions** 

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GADG080120181131SA<br>INTERLOCKING INTERLOCKING G<br>**----- End of picture text -----**<br>


**DS14683** - **Rev 1** 

**page 14/23** 

**STGIPNS4C60T-H Shutdown function** 

**4 Shutdown function** 

The device is equipped with three half-bridge IC gate drivers and integrates a comparator for fault detection. The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting input pin (CIN) can be connected to an external shunt resistor for current monitoring. 

Since the comparator is embedded in the U IC gate driver, in case of fault it disables directly the U outputs, whereas the shutdown of V and W IC gate drivers depends on the RC value of the external SD circuitry, which fixes the disabling time. 

For an effective design of the shutdown circuit, please refer to Application note AN4966. 

**Figure 10. Shutdown timing waveforms** 

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GADG250120171515FSR<br>V REF wpe 1 etree:\<br>\<br>f<br>CI N ' J<br>'<br>4<br>q\<br>'<br>HIN or LIN<br>'1<br>U V, W<br>PROTECT ION<br>HVG or  LVG<br>— e e te<br>SD/ODor Vore ] I 4<br>— ‘<br>T/SD/OD !l !<br>1 '<br>Vin-------+-5 ee ee iis<br>i ee<br>‘ i)<br>A<br>to T B<br>open -drain gate<br>(internal)<br>L)t <—_____—__»-4#_________ t A ' t B >:'i)<br>Vorr — Vo Va — V,<br>SHUTDOWN CIRCUIT wen ney.<br>Vbi<br>O Ta = (Ron_op//Rsp//Rep_sp// [∗] Rwrc)* €sv = Ron_ov * sp<br>Rso Te = (Rsp//Rpv_sv// [∗] Ryrc)* €sp<br>V.= er:ut Vo = =,Ron_ov//Rpp_so//yn PR [∗] RuteND Hn Vvbi<br>[∗]<br>I csp Reo_so §$ *RNTC $i eMgreeese on (Ron_ov//Rep_ ≅ sv//Ron_opRyrc) +  RspV, mas<br>= =- + = Ron.ov+Rsp<br>Vi.= Rpp_so// ∗ [∗] Rye Vy<br>°1 (Rep _ so// Ryrc)+ Rso<br>RSD and CSD external circuitry must be designed to ensure  Von< Vi & Voge> Vin<br>Please refer to AN4966 for further details.<br>**----- End of picture text -----**<br>


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* RNTC to be considered only when the NTC is internally connected to the T/SD/OD pin.<br>**----- End of picture text -----**<br>


**DS14683** - **Rev 1** 

**page 15/23** 

**STGIPNS4C60T-H Application circuit example** 

**5 Application circuit example** 

## **Figure 11. Application circuit example** 

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MICROCONTROLLER<br>VDC<br>+ -<br>Cvdc<br>C4<br>M PWR_GN D<br>Rshunt<br>DZ2 DZ2 DZ2<br>C3 C3 C3<br>Cboot U Cboot V Cboot W<br>RS<br>Vboot U (17) P (18) U, OUT U (19) N U (20) Vboot V (21) V, OUT V (22) N V (23) Vboot W (24) W, OUT W (25) N W (26)<br>Vboot HVG OUT LVG CIN Vboot HVG OUT LVG OP+ Vboot HVG OUT LVG<br>LIN SD/OD HIN VCC GND LIN SD/OD HIN VCC OP- OPOUT GND LIN SD/OD HIN VCC GND<br>NTC<br>LIN U (16) T / SD / OD (15) HIN U (14) Vcc U (13) CIN (12) C SF LIN V (11) HIN V (10) Vcc V (9) OP- (8) C OP OPOUT (7) OP+ (6) LINW (5) HIN W (4) Vcc W (3) T / SD / OD (2) GND (1)<br>C1 C1 C1 C1 C1 C1 SGN_GN D DZ1<br>R SF R5<br>R1 R1 RS R1 R1 R4 C AD R1 R1 C2<br>Cvc c<br>R2 R3 R SD C SD<br>5V / 3.3V 5V / 3.3V<br>R1 + VCC -<br>RS<br>LIN U HIN U LIN V HIN V ADC LIN W HIN W<br>SD Temp. Monitoring<br>**----- End of picture text -----**<br>


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GAD250720161156FSR<br>**----- End of picture text -----**<br>


Application designers are free to use a different scheme according to the device specifications. 

**DS14683** - **Rev 1** 

**page 16/23** 

**STGIPNS4C60T-H Application circuit example** 

## **5.1 Guidelines** 

- Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-in for each input. To avoid input signal oscillation, the wiring of each input should be as short as possible, and the use of RC filters (R1, C1) on each input signal is suggested. The filters should be with a time constant of about 100 ns and placed as close as possible to the IPM input pins. 

- The use of a bypass capacitor CVCC (aluminum or tantalum) can reduce the transient circuit demand on the power supply. Also, to reduce any high-frequency switching noise distributed on the power lines, a decoupling capacitor C2 (100 to 220 nF, with low ESR and low ESL) should be placed as close as possible to the Vcc pin and in parallel with the bypass capacitor. 

- The use of an RC filter (RSF, CSF) is recommended to prevent protection circuit malfunction. The time constant (RSF x CSF) should be set to 1 μs and the filter must be placed as close as possible to the CIN pin. 

- The SD is an input/output pin (open-drain type if it is used as output). A built-in thermistor NTC is internally connected between the SD pin and GND. The voltage VSD-GND decreases as the temperature increases, due to the pull-up resistor RSD. In order to keep the voltage always higher than the high-level logic threshold, the pull-up resistor should be set to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU power supply, respectively. The capacitor CSD of the filter on SD should be fixed no higher than 3.3 nF in order to assure the SD activation time τA ≤ 500 ns. Besides, the filter should be placed as close as possible to the SD pin. 

- The decoupling capacitor C3 (from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with each Cboot, filters high-frequency disturbance. Both Cboot and C3 (if present) should be placed as close as possible to the U, V, W and Vboot pins. Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires. 

- To avoid overvoltage on the Vcc pin, a Zener diode (Dz1) can be used. Similarly on the Vboot pin, a Zener diode (Dz2) can be placed in parallel with each Cboot. 

- The use of the decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor Cvdc is useful to prevent surge destruction. Both capacitors C4 and Cvdc should be placed as close as possible to the IPM (C4 has priority over Cvdc). 

- By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an opto-couplers is possible. 

- Low-inductance shunt resistors have to be used for phase leg current sensing. 

- In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND should be as short as possible. 

- The connection of SGN_GND to PWR_GND on one point only (close to the shunt resistor terminal) can reduce the impact of power ground fluctuation. 

These guidelines ensure the device specifications for application designs. For further details, please refer to the relevant application note. 

**Table 14. Recommended operating conditions** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VPN|Supply voltage|Applied between P-Nu, Nv, Nw||300|500|V|
|VCC|Control supply voltage|Applied between VCC-GND|13.5|15|18|V|
|VBS|High-side bias voltage|Applied between VBOOTx-OUT<br>for x = U, V, W|13||18|V|
|tdead|Blanking time to prevent<br>arm-short|For each input signal|1.5|||μs|
|fPWM|PWM input signal|-40 °C < TC< 100 °C<br>-40 °C < TJ< 125 °C|||25|kHz|
|TC|Case operating temperature||||100|°C|



**DS14683** - **Rev 1** 

**page 17/23** 

**STGIPNS4C60T-H Package information** 

**6 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 

## **6.1 NSDIP-26L package information** 

**Figure 12. NSDIP-26L package outline** 

**==> picture [31 x 31] intentionally omitted <==**

**==> picture [104 x 78] intentionally omitted <==**

**==> picture [31 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
8374968_4<br>**----- End of picture text -----**<br>


**DS14683** - **Rev 1** 

**page 18/23** 

**STGIPNS4C60T-H Package information** 

**Table 15. NSDIP-26L package mechanical data** 

|**Di**|**mm**|**mm**|**mm**|
|---|---|---|---|
|**m.**|**Min.**|**Typ.**|**Max.**|
|A|||3.45|
|A1|0.10||0.25|
|A2|3.00|3.10|3.20|
|A3|1.10|1.30|1.50|
|b|0.47||0.57|
|b1|0.45|0.50|0.55|
|b2|0.63||0.67|
|c|0.47||0.57|
|c1|0.45|0.50|0.55|
|D|29.05|29.15|29.25|
|D1|0.70|||
|D2|0.45|||
|D3|0.90|||
|D4|||29.65|
|E|12.35|12.45|12.55|
|E1|16.70|17.00|17.30|
|E2|0.35|||
|e|1.70|1.80|1.90|
|e1|2.40|2.50|2.60|
|L|1.24|1.39|1.54|
|L1|1.00|1.15|1.30|
|L2|0.25 BSC|||
|L3|2.275 REF|||
|R1|0.25|0.40|0.55|
|R2|0.25|0.40|0.55|
|S||0.39|0.55|
|ϴ|0°||8°|
|ϴ1|3° BSC|||
|ϴ2|10°|12°|14°|



**DS14683** - **Rev 1** 

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**STGIPNS4C60T-H Package information** 

**Figure 13. NSDIP-26L recommended footprint (dimensions are in mm)** 

**==> picture [229 x 147] intentionally omitted <==**

8374968_4_fp 

**DS14683** - **Rev 1** 

**page 20/23** 

**STGIPNS4C60T-H** 

## **Revision history** 

## **Table 16. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|03-Jun-2024|1|First release.|



**DS14683** - **Rev 1** 

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**STGIPNS4C60T-H Contents** 

## **Contents** 

|**1**|**Internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2**|
|---|---|
|**2**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5**|
||**2.1**<br>Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
||**2.2**<br>Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7**|
||**3.1**<br>Inverter part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
||**3.2**<br>Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
||**3.2.1**<br>NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
||**3.3**<br>Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14|
|**4**|**Shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15**|
|**5**|**Application circuit example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16**|
||**5.1**<br>Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17|
|**6**|**Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18**|
||**6.1**<br>NSDIP-26L package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18|
|**Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21**||



**DS14683** - **Rev 1** 

**page 22/23** 

**STGIPNS4C60T-H** 

## **IMPORTANT NOTICE – READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2024 STMicroelectronics – All rights reserved 

**DS14683** - **Rev 1** 

**page 23/23** 



## Links

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---

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