# Intelligent Power Module (IPM), IGBT, 600 V, 3 A, 1 kV, NSDIP, SLLIMM-nano

![Product image](https://novapart.co/image/farnell:2980952RL/)

**URL**: https://novapart.co/products/STGIPNS3HD60-H/intelligent-power-module-ipm-igbt-600-v-3-a-1-kv
**SKU**: STGIPNS3HD60-H
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || Intelligent Power Modules
**Price**: €4.8500
**Stock**: 50+
**Lead Time**: 274 days (indicative)

## Description

IPM Power Device:IGBT; Voltage Rating (Vces / Vdss):600V; Current Rating (Ic / Id):3A; Isolation Voltage:1kV; IPM Case Style:NSDIP; IPM Series:SLLIMM-nano; Product Range:-; SVHC:No SV

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| Ipm Series | SLLIMM-nano |
| Product Range | - |
| Ipm Case Style | NSDIP |
| Ipm Power Device | IGBT |
| Isolation Voltage | 1kV |
| Current Rating (Ic / Id) | 3A |
| Voltage Rating (Vces / Vdss) | 600V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2980952RL/)

## **STGIPNS3HD60-H** 

SLLIMM™-nano small low-loss intelligent molded module IPM, 3 A, 600 V, 3-phase IGBT inverter bridge 

Datasheet - production data 

## **Applications** 

**==> picture [138 x 122] intentionally omitted <==**

**----- Start of picture text -----**<br>
16<br>17<br>1<br>26<br>NSDIP-26L<br>**----- End of picture text -----**<br>


## **Features** 

- IPM 3 A, 600 V, 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes 

- Optimized for low electromagnetic interference 

- VCE(sat) negative temperature coefficient 

- 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull-down/pull-up resistors 

- 3-phase inverters for motor drives 

- Dish washers, refrigerator compressors, heating systems, air-conditioning fans, draining and recirculation pumps 

## **Description** 

This SLLIMM (small low-loss intelligent molded module) nano provides a compact, highperformance AC motor drive in a simple, rugged design. It is composed of six IGBTs and three half-bridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed. The package is optimized for thermal performance and compactness in built-in motor applications, or other low-power applications where assembly space is limited. This IPM includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. SLLIMM™ is a trademark of STMicroelectronics. 

- Blanking time tdead ≥ 1 µs 

- Undervoltage lockout 

- Internal bootstrap diode 

- Interlocking function 

- Comparator for fault protection against overtemperature and overcurrent 

- Op-amp for advanced current sensing 

- Optimized pinout for easy board layout 

- Moisture sensitivity level (MSL) 3 

**Table 1: Device summary Order code Marking Package Packing** ~~_————~~ STGIPN3HD60-H GIPN3HD60-H NSDIP-26L Tape and reel 

This is information on a product in full production. 

_www.st.com_ 

January 2018 DocID030529 Rev 2 

1/22 

|**Contents**<br>**STGIPNS3HD60-H**|**Contents**<br>**STGIPNS3HD60-H**|
|---|---|
|**Contents**||
|**1**|**Internal schematic diagram and pin configuration ....................... 3**|
|**2**|**Electrical ratings ............................................................................. 6**|
||2.1<br>Absolute maximum ratings ................................................................ 6|
||2.2<br>Thermal data ..................................................................................... 7|
|**3**|**Electrical characteristics ................................................................ 8**|
||3.1<br>Inverter part ....................................................................................... 8|
||3.2<br>Control part ..................................................................................... 10|
||3.3<br>Waveform definitions ....................................................................... 12|
|**4**|**Smart shutdown function ............................................................. 13**|
|**5**|**Application circuit example .......................................................... 15**|
||5.1<br>Guidelines ....................................................................................... 16|
|**6**|**Package information ..................................................................... 18**|
||6.1<br>NSDIP-26L package information ..................................................... 18|
|**7**|**Revision history ............................................................................ 21**|



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**Internal schematic diagram and pin configuration** 

## **1 Internal schematic diagram and pin configuration** 

**Figure 1: Internal schematic diagram** 

**==> picture [406 x 428] intentionally omitted <==**

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## **Internal schematic diagram and pin configuration** 

**Table 2: Pin description** 

|**Pin**|**Symbol**|**Description**|
|---|---|---|
|1|GND|Ground|
|2|SD<br>/ OD|Shutdown logic input (active-low)/open-drain (comparator output)|
|3|VCCW|Low-voltagepower supplyWphase|
|4|HIN W|High-side logic input for Wphase|
|5|LIN W|Low-side logic input for Wphase|
|6|OP+|Op-ampnon-invertinginput|
|7|OPOUT|Op-ampoutput|
|8|OP-|Op-ampinvertinginput|
|9|VCCV|Low-voltagepower supplyVphase|
|10|HIN V|High-side logic input for Vphase|
|11|LIN V|Low-side logic input for Vphase|
|12|CIN|Comparator input|
|13|VCCU|Low-voltagepower supplyfor Uphase|
|14|HIN U|High-side logic input for Uphase|
|15|SD<br>/ OD|Shutdown logic input (active-low)/open-drain (comparator output)|
|16|LIN U|Low-side logic input for Uphase|
|17|VBOOTU|Bootstrapvoltage for Uphase|
|18|P|Positive DC input|
|19|U, OUTU|Uphase output|
|20|NU|Negative DC input for Uphase|
|21|VBOOTV|Bootstrapvoltage for Vphase|
|22|V, OUTV|Vphase output|
|23|NV|Negative DC input for Vphase|
|24|VBOOTW|Bootstrapvoltage for Wphase|
|25|W, OUTW|Wphase output|
|26|NW|Negative DC input for Wphase|



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**Internal schematic diagram and pin configuration** 

**Figure 2: Pin layout (top view)** 

**==> picture [406 x 240] intentionally omitted <==**

**----- Start of picture text -----**<br>
(*) (*)<br>PIN #1 ID<br>(*) Dummy pin internally connected toP (positive DC input).<br>**----- End of picture text -----**<br>


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**Electrical ratings** 

## **2 Electrical ratings** 

## **2.1 Absolute maximum ratings** 

**Table 3: Inverter part** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VCES|Each IGBT collector emitter voltage (VIN_(1)_= 0)|600|V|
|± IC_(2)_|Each IGBT continuous collector current at TC= 25°C|3|A|
|± ICP_(3)_|Each IGBTpulsed collector current|18|A|
|PTOT|Each IGBT total dissipation at TC= 25°C|7|W|



## **Notes:** 

(1)Applied between HINx, LINx and GND for x = U, V, W. 

- (2)Calculated according to the iterative formula: 

(3)Pulse width limited by max junction temperature. 

## **Table 4: Control part** 

|**Symbol**|**Parameter**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|---|
|VOUT|Output voltage applied between OUTU, OUTV,<br>OUTW- GND|Vboot- 21|Vboot+ 0.3|V|
|VCC|Low-voltagepower supply|- 0.3|21|V|
|VCIN|Comparator input voltage|- 0.3|VCC+ 0.3|V|
|Vop+|Op-ampnon-invertinginput|- 0.3|VCC+ 0.3|V|
|Vop-|Op-ampinvertinginput|- 0.3|VCC+ 0.3|V|
|Vboot|Bootstrapvoltage|- 0.3|620|V|
|VIN|Logic input voltage applied amongHIN, LIN and GND|- 0.3|15|V|
|~~V~~SD<br>OD<br>⁄|Open-drain voltage|- 0.3|15|V|
|∆VOUT/dT|Allowed output slew rate||50|V/ns|



**Table 5: Total system** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VISO|Isolation withstand voltage applied between each pin and the<br>heatsinkplate (AC voltage, t = 60 s)|1000|V|
|Tj|Power chips operating junction temperature|-40 to 150|°C|
|TC|Module case operation temperature|-40 to 125|°C|



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**Electrical ratings** 

## **2.2 Thermal data** 

||**Table 6: Thermal data**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|RthJA|Thermal resistance junction-ambient|44|°C/W|



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**Electrical characteristics** 

## **3 Electrical characteristics** 

## **3.1 Inverter part** 

TJ = 25 °C unless otherwise specified 

**Table 7: Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VCE(sat)|Collector-emitter saturation voltage|VCC= Vboot= 15 V, VIN_(1)_= 0 - 5 V,<br>IC= 1 A|-|2.15|2.6|V|
|||VCC= Vboot= 15 V, VIN_(1)_= 0 - 5 V,<br>IC= 1 A, TJ= 125 °C|-|1.65|||
|ICES|Collector cut-off current<br>(VIN_(1)_= 0 “logic state”)|VCE= 550 V, VCC= VBoot= 15 V|-||250|µA|
|VF|Diode forward voltage|VIN_(1)_= 0 “logic state”, IC= 1 A|-||1.7|V|



## **Notes:** 

(1)Applied between HINx, LINx and GND for x = U,V,W. 

**Table 8: Inductive load switching time and energy** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ton_(1)_|Turn-on time|VDD= 300 V, VCC= Vboot= 15 V,<br>VIN_(2)_= 0 - 5 V, IC= 1 A<br>(see_Figure 4: "Switching time_<br>_definition"_)|-|158|-|ns|
|tc(on)_(1)_|Crossover time (on)||-|60|-||
|toff_(1)_|Turn-off time||-|515|-||
|tc(off)_(1)_|Crossover time (off)||-|85|-||
|trr|Reverse recoverytime||-|82|-||
|Eon|Turn-on switchingenergy||-|16|-|µJ|
|Eoff|Turn-off switchingenergy||-|10|-||



## **Notes:** 

(1)tON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching times of the IGBT itself under the internally given gate driving condition. 

(2)Applied between HINx, LINx and GND for x = U,V,W. 

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**Electrical characteristics** 

**Figure 3: Switching time test circuit** 

**Figure 4: Switching time definition** 

_Figure 4: "Switching time definition"_ refers to the HIN and LIN inputs (active-high). 

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**Electrical characteristics** 

## **3.2 Control part** 

VCC = 15 V unless otherwise specified 

**Table 9: Low-voltage power supply** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VCC_hys|VCCUV hysteresis||1.2|1.5|1.8|V|
|VCC_thON|VCCUV turn-ON threshold||11.5|12|12.5|V|
|VCC_thOFF|VCCUV turn-OFF threshold||10|10.5|11|V|
|Iqccu|Undervoltage quiescent supply<br>current|VCC= 10 V, SD<br>/OD = 5 V,<br>LIN = 0 V, HIN = 0, CIN= 0|||150|µA|
|Iqcc|Quiescent current|Vcc= 15 V, SD<br>/OD = 5 V,<br>LIN = 0 V, HIN = 0, CIN= 0|||1|mA|
|Vref|Internal comparator (CIN) reference<br>voltage||0.5|0.54|0.58|V|



**Table 10: Bootstrapped voltage** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VBS_hys|VBSUV hysteresis||1.2|1.5|1.8|V|
|VBS_thON|VBSUV turn-ON threshold||11.1|11.5|12.1|V|
|VBS_thOFF|VBSUV turn-OFF threshold||9.8|10|10.6|V|
|IQBSU|Undervoltage VBSquiescent current|VBS< 9 V, SD<br>/OD = 5 V,<br>LIN = 0 V and HIN = 5 V, CIN= 0||70|110|µA|
|IQBS|VBSquiescent current|VBS= 15 V, SD<br>/OD = 5 V,<br>LIN = 0 V and HIN = 5 V, CIN= 0||200|300|µA|
|RDS(on)|Bootstrapdriver on-resistance|LVG ON||120||Ω|



**Table 11: Logic inputs** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vil|Low-logic level voltage||||0.8|V|
|Vih|High-logic level voltage||2.25|||V|
|IHINh|HIN logic “1” input bias current|HIN = 15 V|20|40|100|µA|
|IHINl|HIN logic “0” input bias current|HIN = 0 V|||1|µA|
|ILINl|LIN logic “0” input bias current|LIN = 0 V|||1|µA|
|ILINh|LIN logic “1” input bias current|LIN = 15 V|20|40|100|µA|
|ISDh|SD<br>logic “0” input bias current|SD<br>= 15 V|30|120|300|µA|
|ISDl|SD<br>logic “1” input bias current|SD<br>= 0 V|||3|µA|
|Dt|Dead time|See_Figure 5: "Dead time and_<br>_interlocking waveform definitions"_||360||ns|



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**Electrical characteristics** 

**Table 12: Op-amp characteristics** 

|**Symbol**|**Parameter**|**Test condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vio|Input offset voltage|Vic= 0 V, Vo= 7.5 V|||6|mV|
|Iio|Input offset current|Vic= 0 V, Vo= 7.5 V||4|40|nA|
|Iib|Input bias current_(1)_|||100|200|nA|
|VOL|Low-level output voltage|RL= 10 kΩ to VCC||75|150|mV|
|VOH|High-level output voltage|RL= 10 kΩ to GND|14|14.7||V|
|Io|Output short circuit current|Source, Vid= + 1 V, Vo= 0 V|16|30||mA|
|||Sink, Vid= -1 V, Vo= VCC|50|80||mA|
|SR|Slew rate|Vi= 1 - 4 V, CL= 100 pF,<br>unity gain|2.5|3.8||V/µs|
|GBWP|Gain bandwidth product|Vo= 7.5 V|8|12||MHz|
|Avd|Large signal voltagegain|RL= 2 kΩ|70|85||dB|
|SVR|Supplyvoltage rejection ratio|vs. VCC|60|75||dB|
|CMRR|Common mode rejection ratio||55|70||dB|



## **Notes:** 

(1)The direction of the input current is out of the IC. 

**Table 13: Sense comparator characteristics** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Iib|Input bias current|VCIN= 1 V|||1|µA|
|Vol|Open drain low level output voltage|Iod= 3 mA|||0.5|V|
|RON_OD|Open-drain low-level output|Iod= 3 mA||166||Ω|
|RPD_SD|SD<br>pull-down resistor_(1)_|||125||kΩ|
|td_comp|Comparator delay|SD<br>/OD pulled to 5 V through<br>100 kΩ resistor||90|130|ns|
|SR|Slew rate|CL= 180pF; Rpu= 5 kΩ||60||V/µs|
|tsd|Shutdown to high- / low-side driver<br>propagation delay|VOUT= 0, Vboot= VCC,<br>VIN= 0 to 3.3 V|50|125|200|ns|
|tisd|Comparator triggering to high- /<br>low-side driver turn-off propagation<br>delay|Measured applying a voltage step<br>from 0 V to 3.3 V to pin CIN|50|200|250||



## **Notes:** 

(1)Equivalent values as a result of the resistances of three drivers in parallel. 

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## **Electrical characteristics** 

|**Table 14: Truth table**|**Table 14: Truth table**|||||
|---|---|---|---|---|---|
|**Condition**|**Logic**|**input (VI) **||**Output**||
||**SD**<br>**/OD**|**LIN**|**HIN**|**LVG**|**HVG**|
|Shutdown enable half-bridge tri-state|L|X_(1)_|X_(1)_|L|L|
|Interlockinghalf-bridge tri-state|H|H|H|L|L|
|0 “logic state” half-bridge tri-state|H|L|L|L|L|
|1 “logic state” low side direct driving|H|H|L|H|L|
|1 “logic state” high side direct driving|H|L|H|L|H|



## **Notes:** 

(1)X: don’t care. 

## **3.3 Waveform definitions** 

**Figure 5: Dead time and interlocking waveform definitions** 

**==> picture [408 x 353] intentionally omitted <==**

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**Smart shutdown function** 

## **4 Smart shutdown function** 

The device integrates a comparator for fault sensing purposes. The comparator has an internal voltage reference (VREF) connected to the inverting input, while the non-inverting input on the pin (CIN) can be connected to an external shunt resistor for simple overcurrent protection. 

When the comparator triggers, the device is set to the shutdown state and both of its outputs are switched to the low-level setting, causing the half bridge to enter a tri-state. 

In common overcurrent protection architectures, the comparator output is usually connected to the shutdown input through an RC network that provides a monostable circuit which implements a protection time following a fault condition. 

Our smart shutdown architecture immediately turns off the output gate driver in case of overcurrent along a preferential path for the fault signal which directly switches off the outputs. The time delay between the fault and output shutdown does no longer depend on the RC values of the external network connected to the shutdown pin. At the same time, the DMOS connected to the open-drain output (SD/OD pin) is turned on by the internal logic, which holds it on until the shutdown voltage is lower than the logic input lower threshold (Vil). 

Moreover, the smart shutdown function allows to increase the real disable time without increasing the constant time of the external RC network. 

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**STGIPNS3HD60-H** 

**Figure 6: Smart shutdown timing waveforms** 

**==> picture [406 x 477] intentionally omitted <==**

**----- Start of picture text -----**<br>
comp Vref<br>CP+<br>HIN/LIN<br>PROTECTION<br>HVG/LVG<br>SD/OD<br>open-drain gate<br>(internal)<br>disable time<br>Fast shutdown :<br>the driver outputs are set to the SD state as soon as the comparator<br>triggers even if the SD signal hasn’t reached the lowest input threshold<br>An approximation of the disable time is given by:<br>SHUTDOWN CIRCUIT<br>Vbias<br>R_SD<br>VSD/OD<br>C_SD RPD_SD RON_OD SMART SD<br>LOGIC<br>GADG171120161315SA<br>**----- End of picture text -----**<br>


Please refer to _Table 13: "Sense comparator characteristics"_ for details on the internal propagation delay time. 

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**Application circuit example** 

## **5 Application circuit example** 

**Figure 7: Application circuit example** 

**==> picture [408 x 528] intentionally omitted <==**

Application designers are free to use a different scheme according to the device specifications. 

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**Application circuit example** 

## **5.1 Guidelines** 

- Input signals HIN, LIN are active-high logic. A 375 kΩ (typ.) pull-down resistor is builtin for each input. To prevent input signal oscillation, the wiring of each input should be as short as possible and the use of RC filters (R1, C1) on each input signal is suggested. The filters should be done within a time constant of about 100 ns and placed as close as possible to the IPM input pins. 

- The use of a CVCC bypass capacitor (aluminum or tantalum) can help to reduce the transient circuit demand on the power supply. Also, to reduce any high-frequency switching noise distributed on the power lines, it is suggested to place a C2 decoupling capacitor (100 to 220 nF, with low ESR and low ESL) as close as possible to the Vcc pin and in parallel whit the bypass capacitor. 

- The use of an RC filter (RSF, CSF) for preventing protection circuit malfunction is recommended. The time constant (RSF x CSF) should be set to 1 µs and the filter must be placed as close as possible to the CIN pin. 

- The SD is an input/output pin (open-drain type if used as output). The CSD 

capacitor of the filter on SD should be fixed no higher than 3.3 nF in order to assure 

an SD activation time of т1 ≤ 500 ns, in addition the filter should be placed as close 

as possible to the SD pin. 

- The C3 decoupling capacitor (from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with each Cboot, is useful to filter any high-frequency disturbance. Both Cboot and C3 (if present) should be placed as close as possible to the U, V, W and Vboot pins. Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires. 

- To prevent overvoltage on the Vcc pin, a Zener diode (Dz1) can be used. Similarly, a Zener diode (Dz2) can be placed on the Vboot pin in parallel with each Cboot. 

- The use of the decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor Cvdc is useful to prevent surge destruction. Both capacitors C4 and Cvdc should be placed as close as possible to the IPM (C4 has priority over Cvdc). 

- By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an opto-coupler is possible. 

- Use low-inductance shunt resistors for phase leg current sensing. 

- To avoid any malfunctions, the wiring between the N pins, the shunt resistor and PWR_GND should be as short as possible. 

- The connection of SGN_GND to PWR_GND at only one point (close to the shunt resistor terminal) can help to reduce the impact of power ground fluctuation. 

These guidelines ensure the device specifications for application designs. For further details, please refer to the relevant application note. 

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**Application circuit example** 

**Table 15: Recommended operating conditions** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VPN|Supplyvoltage|Applied between P-Nu, Nv, Nw||300|500|V|
|VCC|Control supplyvoltage|Applied between VCC-GND|13.5|15|18|V|
|VBS|High-side bias voltage|Applied between VBOOTi-OUTifor<br>i = U, V, W|13||18|V|
|tdead|Blanking time to prevent<br>Arm-short|For each input signal|1|||µs|
|fPWM|PWM input signal|-40°C < Tc< 100 °C<br>-40°C < Tj< 125 °C|||25|kHz|
|TC|Case operation<br>temperature||||100|°C|



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**Package information** 

## **6 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **6.1 NSDIP-26L package information** 

**Figure 8: NSDIP-26L package outline** 

**==> picture [408 x 457] intentionally omitted <==**

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**Package information** 

**Table 16: NSDIP-26L package mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|||3.45|
|A1|0.10||0.25|
|A2|3.00|3.10|3.20|
|A3|1.70|1.80|1.90|
|b|0.47||0.57|
|b1|0.45|0.50|0.55|
|b2|0.63||0.67|
|c|0.47||0.57|
|c1|0.45|0.50|0.55|
|D|29.05|29.15|29.25|
|D1|0.70|||
|D2|0.45|||
|D3|0.90|||
|D4|||29.65|
|E|12.35|12.45|12.55|
|E1|16.70|17.00|17.30|
|E2|0.35|||
|e|1.70|1.80|1.90|
|e1|2.40|2.50|2.60|
|L|1.24|1.39|1.54|
|L1|1.00|1.15|1.30|
|L2||0.25 BSC||
|L3||2.275 REF||
|R1|0.25|0.40|0.55|
|R2|0.25|0.40|0.55|
|S||0.39|0.55|
|ϴ|0°||8°|
|ϴ1||3° BSC||
|ϴ2|10°|12°|14°|



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**Package information** 

**Figure 9: NSDIP-26L recommended footprint (dimensions are in mm)** 

**==> picture [408 x 247] intentionally omitted <==**

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**Revision history** 

## **7 Revision history** 

**Table 17: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|19-Apr-2017|1|Initial release|
|19-Jan-2018|2|Datasheet status promoted from preliminary to production data.<br>Updated features on cover page.<br>Updated_Table 3: "Inverter part"_,_Table 5: "Total system"_,_Table 6:_<br>_"Thermal data"_,_Table 9: "Low-voltage power supply"_,_Table 10:_<br>_"Bootstrapped voltage"_and_Table 13: "Sense comparator_<br>_characteristics"_.<br>Updated_Figure 6: "Smart shutdown timing waveforms"_.<br>Updated_Section 6.1: "NSDIP-26L package information"_.<br>Minor text changes|



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**STGIPNS3HD60-H** 

## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

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- © 2018 STMicroelectronics – All rights reserved 

22/22 

DocID030529 Rev 2 



## Links

- [View this product on Novapart](https://novapart.co/products/STGIPNS3HD60-H/intelligent-power-module-ipm-igbt-600-v-3-a-1-kv)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/stmicroelectronics/stgipns3hd60-h/power-module-igbt-3a-600v-nsdip/dp/2980952RL)
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